| blob | b540388c608c4ec9addf0a3d66c9664f6d2d5ac6 |
1 /*
2 * Lite5200B board Device Tree Source
3 *
4 * Copyright 2006-2007 Secret Lab Technologies Ltd.
5 * Grant Likely <grant.likely@secretlab.ca>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
13 /*
14 * WARNING: Do not depend on this tree layout remaining static just yet.
15 * The MPC5200 device tree conventions are still in flux
16 * Keep an eye on the linuxppc-dev mailing list for more details
17 */
19 / {
20 model = "fsl,lite5200b";
21 // revision = "1.0";
22 compatible = "fsl,lite5200b","generic-mpc5200";
23 #address-cells = <1>;
24 #size-cells = <1>;
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
30 PowerPC,5200@0 {
31 device_type = "cpu";
32 reg = <0>;
33 d-cache-line-size = <20>;
34 i-cache-line-size = <20>;
35 d-cache-size = <4000>; // L1, 16K
36 i-cache-size = <4000>; // L1, 16K
37 timebase-frequency = <0>; // from bootloader
38 bus-frequency = <0>; // from bootloader
39 clock-frequency = <0>; // from bootloader
40 };
41 };
43 memory {
44 device_type = "memory";
45 reg = <00000000 10000000>; // 256MB
46 };
48 soc5200@f0000000 {
49 model = "fsl,mpc5200b";
50 compatible = "mpc5200";
51 revision = ""; // from bootloader
52 device_type = "soc";
53 ranges = <0 f0000000 0000c000>;
54 reg = <f0000000 00000100>;
55 bus-frequency = <0>; // from bootloader
56 system-frequency = <0>; // from bootloader
58 cdm@200 {
59 compatible = "mpc5200b-cdm","mpc5200-cdm";
60 reg = <200 38>;
61 };
63 mpc5200_pic: pic@500 {
64 // 5200 interrupts are encoded into two levels;
65 interrupt-controller;
66 #interrupt-cells = <3>;
67 device_type = "interrupt-controller";
68 compatible = "mpc5200b-pic","mpc5200-pic";
69 reg = <500 80>;
70 };
72 gpt@600 { // General Purpose Timer
73 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
74 cell-index = <0>;
75 reg = <600 10>;
76 interrupts = <1 9 0>;
77 interrupt-parent = <&mpc5200_pic>;
78 fsl,has-wdt;
79 };
81 gpt@610 { // General Purpose Timer
82 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
83 cell-index = <1>;
84 reg = <610 10>;
85 interrupts = <1 a 0>;
86 interrupt-parent = <&mpc5200_pic>;
87 };
89 gpt@620 { // General Purpose Timer
90 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
91 cell-index = <2>;
92 reg = <620 10>;
93 interrupts = <1 b 0>;
94 interrupt-parent = <&mpc5200_pic>;
95 };
97 gpt@630 { // General Purpose Timer
98 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
99 cell-index = <3>;
100 reg = <630 10>;
101 interrupts = <1 c 0>;
102 interrupt-parent = <&mpc5200_pic>;
103 };
105 gpt@640 { // General Purpose Timer
106 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
107 cell-index = <4>;
108 reg = <640 10>;
109 interrupts = <1 d 0>;
110 interrupt-parent = <&mpc5200_pic>;
111 };
113 gpt@650 { // General Purpose Timer
114 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
115 cell-index = <5>;
116 reg = <650 10>;
117 interrupts = <1 e 0>;
118 interrupt-parent = <&mpc5200_pic>;
119 };
121 gpt@660 { // General Purpose Timer
122 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
123 cell-index = <6>;
124 reg = <660 10>;
125 interrupts = <1 f 0>;
126 interrupt-parent = <&mpc5200_pic>;
127 };
129 gpt@670 { // General Purpose Timer
130 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
131 cell-index = <7>;
132 reg = <670 10>;
133 interrupts = <1 10 0>;
134 interrupt-parent = <&mpc5200_pic>;
135 };
137 rtc@800 { // Real time clock
138 compatible = "mpc5200b-rtc","mpc5200-rtc";
139 device_type = "rtc";
140 reg = <800 100>;
141 interrupts = <1 5 0 1 6 0>;
142 interrupt-parent = <&mpc5200_pic>;
143 };
145 mscan@900 {
146 device_type = "mscan";
147 compatible = "mpc5200b-mscan","mpc5200-mscan";
148 cell-index = <0>;
149 interrupts = <2 11 0>;
150 interrupt-parent = <&mpc5200_pic>;
151 reg = <900 80>;
152 };
154 mscan@980 {
155 device_type = "mscan";
156 compatible = "mpc5200b-mscan","mpc5200-mscan";
157 cell-index = <1>;
158 interrupts = <2 12 0>;
159 interrupt-parent = <&mpc5200_pic>;
160 reg = <980 80>;
161 };
163 gpio@b00 {
164 compatible = "mpc5200b-gpio","mpc5200-gpio";
165 reg = <b00 40>;
166 interrupts = <1 7 0>;
167 interrupt-parent = <&mpc5200_pic>;
168 };
170 gpio-wkup@c00 {
171 compatible = "mpc5200b-gpio-wkup","mpc5200-gpio-wkup";
172 reg = <c00 40>;
173 interrupts = <1 8 0 0 3 0>;
174 interrupt-parent = <&mpc5200_pic>;
175 };
177 spi@f00 {
178 device_type = "spi";
179 compatible = "mpc5200b-spi","mpc5200-spi";
180 reg = <f00 20>;
181 interrupts = <2 d 0 2 e 0>;
182 interrupt-parent = <&mpc5200_pic>;
183 };
185 usb@1000 {
186 device_type = "usb-ohci-be";
187 compatible = "mpc5200b-ohci","mpc5200-ohci","ohci-be";
188 reg = <1000 ff>;
189 interrupts = <2 6 0>;
190 interrupt-parent = <&mpc5200_pic>;
191 };
193 bestcomm@1200 {
194 device_type = "dma-controller";
195 compatible = "mpc5200b-bestcomm","mpc5200-bestcomm";
196 reg = <1200 80>;
197 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
198 3 4 0 3 5 0 3 6 0 3 7 0
199 3 8 0 3 9 0 3 a 0 3 b 0
200 3 c 0 3 d 0 3 e 0 3 f 0>;
201 interrupt-parent = <&mpc5200_pic>;
202 };
204 xlb@1f00 {
205 compatible = "mpc5200b-xlb","mpc5200-xlb";
206 reg = <1f00 100>;
207 };
209 serial@2000 { // PSC1
210 device_type = "serial";
211 compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
212 port-number = <0>; // Logical port assignment
213 cell-index = <0>;
214 reg = <2000 100>;
215 interrupts = <2 1 0>;
216 interrupt-parent = <&mpc5200_pic>;
217 };
219 // PSC2 in ac97 mode example
220 //ac97@2200 { // PSC2
221 // device_type = "sound";
222 // compatible = "mpc5200b-psc-ac97","mpc5200-psc-ac97";
223 // cell-index = <1>;
224 // reg = <2200 100>;
225 // interrupts = <2 2 0>;
226 // interrupt-parent = <&mpc5200_pic>;
227 //};
229 // PSC3 in CODEC mode example
230 //i2s@2400 { // PSC3
231 // device_type = "sound";
232 // compatible = "mpc5200b-psc-i2s"; //not 5200 compatible
233 // cell-index = <2>;
234 // reg = <2400 100>;
235 // interrupts = <2 3 0>;
236 // interrupt-parent = <&mpc5200_pic>;
237 //};
239 // PSC4 in uart mode example
240 //serial@2600 { // PSC4
241 // device_type = "serial";
242 // compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
243 // cell-index = <3>;
244 // reg = <2600 100>;
245 // interrupts = <2 b 0>;
246 // interrupt-parent = <&mpc5200_pic>;
247 //};
249 // PSC5 in uart mode example
250 //serial@2800 { // PSC5
251 // device_type = "serial";
252 // compatible = "mpc5200b-psc-uart","mpc5200-psc-uart";
253 // cell-index = <4>;
254 // reg = <2800 100>;
255 // interrupts = <2 c 0>;
256 // interrupt-parent = <&mpc5200_pic>;
257 //};
259 // PSC6 in spi mode example
260 //spi@2c00 { // PSC6
261 // device_type = "spi";
262 // compatible = "mpc5200b-psc-spi","mpc5200-psc-spi";
263 // cell-index = <5>;
264 // reg = <2c00 100>;
265 // interrupts = <2 4 0>;
266 // interrupt-parent = <&mpc5200_pic>;
267 //};
269 ethernet@3000 {
270 device_type = "network";
271 compatible = "mpc5200b-fec","mpc5200-fec";
272 reg = <3000 400>;
273 mac-address = [ 02 03 04 05 06 07 ]; // Bad!
274 interrupts = <2 5 0>;
275 interrupt-parent = <&mpc5200_pic>;
276 phy-handle = <&phy0>;
277 };
279 mdio@3000 {
280 #address-cells = <1>;
281 #size-cells = <0>;
282 device_type = "mdio";
283 compatible = "mpc5200b-fec-phy";
284 reg = <3000 400>; // fec range, since we need to setup fec interrupts
285 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
286 interrupt-parent = <&mpc5200_pic>;
288 phy0:ethernet-phy@0 {
289 device_type = "ethernet-phy";
290 reg = <0>;
291 };
292 };
294 ata@3a00 {
295 device_type = "ata";
296 compatible = "mpc5200b-ata","mpc5200-ata";
297 reg = <3a00 100>;
298 interrupts = <2 7 0>;
299 interrupt-parent = <&mpc5200_pic>;
300 };
302 i2c@3d00 {
303 device_type = "i2c";
304 compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
305 cell-index = <0>;
306 reg = <3d00 40>;
307 interrupts = <2 f 0>;
308 interrupt-parent = <&mpc5200_pic>;
309 fsl5200-clocking;
310 };
312 i2c@3d40 {
313 device_type = "i2c";
314 compatible = "mpc5200b-i2c","mpc5200-i2c","fsl-i2c";
315 cell-index = <1>;
316 reg = <3d40 40>;
317 interrupts = <2 10 0>;
318 interrupt-parent = <&mpc5200_pic>;
319 fsl5200-clocking;
320 };
321 sram@8000 {
322 device_type = "sram";
323 compatible = "mpc5200b-sram","mpc5200-sram","sram";
324 reg = <8000 4000>;
325 };
326 };
328 pci@f0000d00 {
329 #interrupt-cells = <1>;
330 #size-cells = <2>;
331 #address-cells = <3>;
332 device_type = "pci";
333 compatible = "mpc5200b-pci","mpc5200-pci";
334 reg = <f0000d00 100>;
335 interrupt-map-mask = <f800 0 0 7>;
336 interrupt-map = <c000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
337 c000 0 0 2 &mpc5200_pic 1 1 3
338 c000 0 0 3 &mpc5200_pic 1 2 3
339 c000 0 0 4 &mpc5200_pic 1 3 3
341 c800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
342 c800 0 0 2 &mpc5200_pic 1 2 3
343 c800 0 0 3 &mpc5200_pic 1 3 3
344 c800 0 0 4 &mpc5200_pic 0 0 3>;
345 clock-frequency = <0>; // From boot loader
346 interrupts = <2 8 0 2 9 0 2 a 0>;
347 interrupt-parent = <&mpc5200_pic>;
348 bus-range = <0 0>;
349 ranges = <42000000 0 80000000 80000000 0 20000000
350 02000000 0 a0000000 a0000000 0 10000000
351 01000000 0 00000000 b0000000 0 01000000>;
352 };
353 };