| blob | 54394372b12afb5db116318e63f688272166d137 |
1 /*
2 * MPC8568E MDS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
13 /*
14 /memreserve/ 00000000 1000000;
15 */
17 / {
18 model = "MPC8568EMDS";
19 compatible = "MPC8568EMDS", "MPC85xxMDS";
20 #address-cells = <1>;
21 #size-cells = <1>;
23 cpus {
24 #address-cells = <1>;
25 #size-cells = <0>;
27 PowerPC,8568@0 {
28 device_type = "cpu";
29 reg = <0>;
30 d-cache-line-size = <20>; // 32 bytes
31 i-cache-line-size = <20>; // 32 bytes
32 d-cache-size = <8000>; // L1, 32K
33 i-cache-size = <8000>; // L1, 32K
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
37 };
38 };
40 memory {
41 device_type = "memory";
42 reg = <00000000 10000000>;
43 };
45 bcsr@f8000000 {
46 device_type = "board-control";
47 reg = <f8000000 8000>;
48 };
50 soc8568@e0000000 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 device_type = "soc";
54 ranges = <0 e0000000 00100000>;
55 reg = <e0000000 00001000>;
56 bus-frequency = <0>;
58 memory-controller@2000 {
59 compatible = "fsl,8568-memory-controller";
60 reg = <2000 1000>;
61 interrupt-parent = <&mpic>;
62 interrupts = <12 2>;
63 };
65 l2-cache-controller@20000 {
66 compatible = "fsl,8568-l2-cache-controller";
67 reg = <20000 1000>;
68 cache-line-size = <20>; // 32 bytes
69 cache-size = <80000>; // L2, 512K
70 interrupt-parent = <&mpic>;
71 interrupts = <10 2>;
72 };
74 i2c@3000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 device_type = "i2c";
78 compatible = "fsl-i2c";
79 reg = <3000 100>;
80 interrupts = <2b 2>;
81 interrupt-parent = <&mpic>;
82 dfsrr;
84 rtc@68 {
85 compatible = "dallas,ds1374";
86 reg = <68>;
87 };
88 };
90 i2c@3100 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 device_type = "i2c";
94 compatible = "fsl-i2c";
95 reg = <3100 100>;
96 interrupts = <2b 2>;
97 interrupt-parent = <&mpic>;
98 dfsrr;
99 };
101 mdio@24520 {
102 #address-cells = <1>;
103 #size-cells = <0>;
104 device_type = "mdio";
105 compatible = "gianfar";
106 reg = <24520 20>;
107 phy0: ethernet-phy@7 {
108 interrupt-parent = <&mpic>;
109 interrupts = <1 1>;
110 reg = <7>;
111 device_type = "ethernet-phy";
112 };
113 phy1: ethernet-phy@1 {
114 interrupt-parent = <&mpic>;
115 interrupts = <2 1>;
116 reg = <1>;
117 device_type = "ethernet-phy";
118 };
119 phy2: ethernet-phy@2 {
120 interrupt-parent = <&mpic>;
121 interrupts = <1 1>;
122 reg = <2>;
123 device_type = "ethernet-phy";
124 };
125 phy3: ethernet-phy@3 {
126 interrupt-parent = <&mpic>;
127 interrupts = <2 1>;
128 reg = <3>;
129 device_type = "ethernet-phy";
130 };
131 };
133 ethernet@24000 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 device_type = "network";
137 model = "eTSEC";
138 compatible = "gianfar";
139 reg = <24000 1000>;
140 /*
141 * mac-address is deprecated and will be removed
142 * in 2.6.25. Only recent versions of
143 * U-Boot support local-mac-address, however.
144 */
145 mac-address = [ 00 00 00 00 00 00 ];
146 local-mac-address = [ 00 00 00 00 00 00 ];
147 interrupts = <1d 2 1e 2 22 2>;
148 interrupt-parent = <&mpic>;
149 phy-handle = <&phy2>;
150 };
152 ethernet@25000 {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 device_type = "network";
156 model = "eTSEC";
157 compatible = "gianfar";
158 reg = <25000 1000>;
159 /*
160 * mac-address is deprecated and will be removed
161 * in 2.6.25. Only recent versions of
162 * U-Boot support local-mac-address, however.
163 */
164 mac-address = [ 00 00 00 00 00 00 ];
165 local-mac-address = [ 00 00 00 00 00 00 ];
166 interrupts = <23 2 24 2 28 2>;
167 interrupt-parent = <&mpic>;
168 phy-handle = <&phy3>;
169 };
171 serial@4500 {
172 device_type = "serial";
173 compatible = "ns16550";
174 reg = <4500 100>;
175 clock-frequency = <0>;
176 interrupts = <2a 2>;
177 interrupt-parent = <&mpic>;
178 };
180 global-utilities@e0000 { //global utilities block
181 compatible = "fsl,mpc8548-guts";
182 reg = <e0000 1000>;
183 fsl,has-rstcr;
184 };
186 serial@4600 {
187 device_type = "serial";
188 compatible = "ns16550";
189 reg = <4600 100>;
190 clock-frequency = <0>;
191 interrupts = <2a 2>;
192 interrupt-parent = <&mpic>;
193 };
195 crypto@30000 {
196 device_type = "crypto";
197 model = "SEC2";
198 compatible = "talitos";
199 reg = <30000 f000>;
200 interrupts = <2d 2>;
201 interrupt-parent = <&mpic>;
202 num-channels = <4>;
203 channel-fifo-len = <18>;
204 exec-units-mask = <000000fe>;
205 descriptor-types-mask = <012b0ebf>;
206 };
208 mpic: pic@40000 {
209 clock-frequency = <0>;
210 interrupt-controller;
211 #address-cells = <0>;
212 #interrupt-cells = <2>;
213 reg = <40000 40000>;
214 compatible = "chrp,open-pic";
215 device_type = "open-pic";
216 big-endian;
217 };
219 par_io@e0100 {
220 reg = <e0100 100>;
221 device_type = "par_io";
222 num-ports = <7>;
224 pio1: ucc_pin@01 {
225 pio-map = <
226 /* port pin dir open_drain assignment has_irq */
227 4 0a 1 0 2 0 /* TxD0 */
228 4 09 1 0 2 0 /* TxD1 */
229 4 08 1 0 2 0 /* TxD2 */
230 4 07 1 0 2 0 /* TxD3 */
231 4 17 1 0 2 0 /* TxD4 */
232 4 16 1 0 2 0 /* TxD5 */
233 4 15 1 0 2 0 /* TxD6 */
234 4 14 1 0 2 0 /* TxD7 */
235 4 0f 2 0 2 0 /* RxD0 */
236 4 0e 2 0 2 0 /* RxD1 */
237 4 0d 2 0 2 0 /* RxD2 */
238 4 0c 2 0 2 0 /* RxD3 */
239 4 1d 2 0 2 0 /* RxD4 */
240 4 1c 2 0 2 0 /* RxD5 */
241 4 1b 2 0 2 0 /* RxD6 */
242 4 1a 2 0 2 0 /* RxD7 */
243 4 0b 1 0 2 0 /* TX_EN */
244 4 18 1 0 2 0 /* TX_ER */
245 4 10 2 0 2 0 /* RX_DV */
246 4 1e 2 0 2 0 /* RX_ER */
247 4 11 2 0 2 0 /* RX_CLK */
248 4 13 1 0 2 0 /* GTX_CLK */
249 1 1f 2 0 3 0>; /* GTX125 */
250 };
252 pio2: ucc_pin@02 {
253 pio-map = <
254 /* port pin dir open_drain assignment has_irq */
255 5 0a 1 0 2 0 /* TxD0 */
256 5 09 1 0 2 0 /* TxD1 */
257 5 08 1 0 2 0 /* TxD2 */
258 5 07 1 0 2 0 /* TxD3 */
259 5 17 1 0 2 0 /* TxD4 */
260 5 16 1 0 2 0 /* TxD5 */
261 5 15 1 0 2 0 /* TxD6 */
262 5 14 1 0 2 0 /* TxD7 */
263 5 0f 2 0 2 0 /* RxD0 */
264 5 0e 2 0 2 0 /* RxD1 */
265 5 0d 2 0 2 0 /* RxD2 */
266 5 0c 2 0 2 0 /* RxD3 */
267 5 1d 2 0 2 0 /* RxD4 */
268 5 1c 2 0 2 0 /* RxD5 */
269 5 1b 2 0 2 0 /* RxD6 */
270 5 1a 2 0 2 0 /* RxD7 */
271 5 0b 1 0 2 0 /* TX_EN */
272 5 18 1 0 2 0 /* TX_ER */
273 5 10 2 0 2 0 /* RX_DV */
274 5 1e 2 0 2 0 /* RX_ER */
275 5 11 2 0 2 0 /* RX_CLK */
276 5 13 1 0 2 0 /* GTX_CLK */
277 1 1f 2 0 3 0 /* GTX125 */
278 4 06 3 0 2 0 /* MDIO */
279 4 05 1 0 2 0>; /* MDC */
280 };
281 };
282 };
284 qe@e0080000 {
285 #address-cells = <1>;
286 #size-cells = <1>;
287 device_type = "qe";
288 model = "QE";
289 ranges = <0 e0080000 00040000>;
290 reg = <e0080000 480>;
291 brg-frequency = <0>;
292 bus-frequency = <179A7B00>;
294 muram@10000 {
295 device_type = "muram";
296 ranges = <0 00010000 0000c000>;
298 data-only@0{
299 reg = <0 c000>;
300 };
301 };
303 spi@4c0 {
304 device_type = "spi";
305 compatible = "fsl_spi";
306 reg = <4c0 40>;
307 interrupts = <2>;
308 interrupt-parent = <&qeic>;
309 mode = "cpu";
310 };
312 spi@500 {
313 device_type = "spi";
314 compatible = "fsl_spi";
315 reg = <500 40>;
316 interrupts = <1>;
317 interrupt-parent = <&qeic>;
318 mode = "cpu";
319 };
321 ucc@2000 {
322 device_type = "network";
323 compatible = "ucc_geth";
324 model = "UCC";
325 device-id = <1>;
326 reg = <2000 200>;
327 interrupts = <20>;
328 interrupt-parent = <&qeic>;
329 /*
330 * mac-address is deprecated and will be removed
331 * in 2.6.25. Only recent versions of
332 * U-Boot support local-mac-address, however.
333 */
334 mac-address = [ 00 00 00 00 00 00 ];
335 local-mac-address = [ 00 00 00 00 00 00 ];
336 rx-clock = <0>;
337 tx-clock = <20>;
338 pio-handle = <&pio1>;
339 phy-handle = <&phy0>;
340 phy-connection-type = "rgmii-id";
341 };
343 ucc@3000 {
344 device_type = "network";
345 compatible = "ucc_geth";
346 model = "UCC";
347 device-id = <2>;
348 reg = <3000 200>;
349 interrupts = <21>;
350 interrupt-parent = <&qeic>;
351 /*
352 * mac-address is deprecated and will be removed
353 * in 2.6.25. Only recent versions of
354 * U-Boot support local-mac-address, however.
355 */
356 mac-address = [ 00 00 00 00 00 00 ];
357 local-mac-address = [ 00 00 00 00 00 00 ];
358 rx-clock = <0>;
359 tx-clock = <20>;
360 pio-handle = <&pio2>;
361 phy-handle = <&phy1>;
362 phy-connection-type = "rgmii-id";
363 };
365 mdio@2120 {
366 #address-cells = <1>;
367 #size-cells = <0>;
368 reg = <2120 18>;
369 device_type = "mdio";
370 compatible = "ucc_geth_phy";
372 /* These are the same PHYs as on
373 * gianfar's MDIO bus */
374 qe_phy0: ethernet-phy@07 {
375 interrupt-parent = <&mpic>;
376 interrupts = <1 1>;
377 reg = <7>;
378 device_type = "ethernet-phy";
379 };
380 qe_phy1: ethernet-phy@01 {
381 interrupt-parent = <&mpic>;
382 interrupts = <2 1>;
383 reg = <1>;
384 device_type = "ethernet-phy";
385 };
386 qe_phy2: ethernet-phy@02 {
387 interrupt-parent = <&mpic>;
388 interrupts = <1 1>;
389 reg = <2>;
390 device_type = "ethernet-phy";
391 };
392 qe_phy3: ethernet-phy@03 {
393 interrupt-parent = <&mpic>;
394 interrupts = <2 1>;
395 reg = <3>;
396 device_type = "ethernet-phy";
397 };
398 };
400 qeic: qeic@80 {
401 interrupt-controller;
402 device_type = "qeic";
403 #address-cells = <0>;
404 #interrupt-cells = <1>;
405 reg = <80 80>;
406 big-endian;
407 interrupts = <2e 2 2e 2>; //high:30 low:30
408 interrupt-parent = <&mpic>;
409 };
411 };
413 pci@e0008000 {
414 interrupt-map-mask = <f800 0 0 7>;
415 interrupt-map = <
416 /* IDSEL 0x12 AD18 */
417 9000 0 0 1 &mpic 5 1
418 9000 0 0 2 &mpic 6 1
419 9000 0 0 3 &mpic 7 1
420 9000 0 0 4 &mpic 4 1
422 /* IDSEL 0x13 AD19 */
423 9800 0 0 1 &mpic 6 1
424 9800 0 0 2 &mpic 7 1
425 9800 0 0 3 &mpic 4 1
426 9800 0 0 4 &mpic 5 1>;
428 interrupt-parent = <&mpic>;
429 interrupts = <18 2>;
430 bus-range = <0 ff>;
431 ranges = <02000000 0 80000000 80000000 0 20000000
432 01000000 0 00000000 e2000000 0 00800000>;
433 clock-frequency = <3f940aa>;
434 #interrupt-cells = <1>;
435 #size-cells = <2>;
436 #address-cells = <3>;
437 reg = <e0008000 1000>;
438 compatible = "fsl,mpc8540-pci";
439 device_type = "pci";
440 };
442 /* PCI Express */
443 pcie@e000a000 {
444 interrupt-map-mask = <f800 0 0 7>;
445 interrupt-map = <
447 /* IDSEL 0x0 (PEX) */
448 00000 0 0 1 &mpic 0 1
449 00000 0 0 2 &mpic 1 1
450 00000 0 0 3 &mpic 2 1
451 00000 0 0 4 &mpic 3 1>;
453 interrupt-parent = <&mpic>;
454 interrupts = <1a 2>;
455 bus-range = <0 ff>;
456 ranges = <02000000 0 a0000000 a0000000 0 10000000
457 01000000 0 00000000 e2800000 0 00800000>;
458 clock-frequency = <1fca055>;
459 #interrupt-cells = <1>;
460 #size-cells = <2>;
461 #address-cells = <3>;
462 reg = <e000a000 1000>;
463 compatible = "fsl,mpc8548-pcie";
464 device_type = "pci";
465 pcie@0 {
466 reg = <0 0 0 0 0>;
467 #size-cells = <2>;
468 #address-cells = <3>;
469 device_type = "pci";
470 ranges = <02000000 0 a0000000
471 02000000 0 a0000000
472 0 10000000
474 01000000 0 00000000
475 01000000 0 00000000
476 0 00800000>;
477 };
478 };
479 };