| blob | 0eb44fb9647dbccf50177d452d0486af529b51ae |
1 /*
2 * MPC8572 DS Device Tree Source
3 *
4 * Copyright 2007 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 / {
13 model = "fsl,MPC8572DS";
14 compatible = "fsl,MPC8572DS";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
22 PowerPC,8572@0 {
23 device_type = "cpu";
24 reg = <0>;
25 d-cache-line-size = <20>; // 32 bytes
26 i-cache-line-size = <20>; // 32 bytes
27 d-cache-size = <8000>; // L1, 32K
28 i-cache-size = <8000>; // L1, 32K
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
32 };
33 };
35 memory {
36 device_type = "memory";
37 reg = <00000000 00000000>; // Filled by U-Boot
38 };
40 soc8572@ffe00000 {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 device_type = "soc";
44 ranges = <00000000 ffe00000 00100000>;
45 reg = <ffe00000 00001000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
46 bus-frequency = <0>; // Filled out by uboot.
48 memory-controller@2000 {
49 compatible = "fsl,mpc8572-memory-controller";
50 reg = <2000 1000>;
51 interrupt-parent = <&mpic>;
52 interrupts = <12 2>;
53 };
55 memory-controller@6000 {
56 compatible = "fsl,mpc8572-memory-controller";
57 reg = <6000 1000>;
58 interrupt-parent = <&mpic>;
59 interrupts = <12 2>;
60 };
62 l2-cache-controller@20000 {
63 compatible = "fsl,mpc8572-l2-cache-controller";
64 reg = <20000 1000>;
65 cache-line-size = <20>; // 32 bytes
66 cache-size = <80000>; // L2, 512K
67 interrupt-parent = <&mpic>;
68 interrupts = <10 2>;
69 };
71 i2c@3000 {
72 device_type = "i2c";
73 compatible = "fsl-i2c";
74 reg = <3000 100>;
75 interrupts = <2b 2>;
76 interrupt-parent = <&mpic>;
77 dfsrr;
78 };
80 i2c@3100 {
81 device_type = "i2c";
82 compatible = "fsl-i2c";
83 reg = <3100 100>;
84 interrupts = <2b 2>;
85 interrupt-parent = <&mpic>;
86 dfsrr;
87 };
89 mdio@24520 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 device_type = "mdio";
93 compatible = "gianfar";
94 reg = <24520 20>;
95 phy0: ethernet-phy@0 {
96 interrupt-parent = <&mpic>;
97 interrupts = <a 1>;
98 reg = <0>;
99 };
100 phy1: ethernet-phy@1 {
101 interrupt-parent = <&mpic>;
102 interrupts = <a 1>;
103 reg = <1>;
104 };
105 phy2: ethernet-phy@2 {
106 interrupt-parent = <&mpic>;
107 interrupts = <a 1>;
108 reg = <2>;
109 };
110 phy3: ethernet-phy@3 {
111 interrupt-parent = <&mpic>;
112 interrupts = <a 1>;
113 reg = <3>;
114 };
115 };
117 ethernet@24000 {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 device_type = "network";
121 model = "eTSEC";
122 compatible = "gianfar";
123 reg = <24000 1000>;
124 local-mac-address = [ 00 00 00 00 00 00 ];
125 interrupts = <1d 2 1e 2 22 2>;
126 interrupt-parent = <&mpic>;
127 phy-handle = <&phy0>;
128 phy-connection-type = "rgmii-id";
129 };
131 ethernet@25000 {
132 #address-cells = <1>;
133 #size-cells = <0>;
134 device_type = "network";
135 model = "eTSEC";
136 compatible = "gianfar";
137 reg = <25000 1000>;
138 local-mac-address = [ 00 00 00 00 00 00 ];
139 interrupts = <23 2 24 2 28 2>;
140 interrupt-parent = <&mpic>;
141 phy-handle = <&phy1>;
142 phy-connection-type = "rgmii-id";
143 };
145 ethernet@26000 {
146 #address-cells = <1>;
147 #size-cells = <0>;
148 device_type = "network";
149 model = "eTSEC";
150 compatible = "gianfar";
151 reg = <26000 1000>;
152 local-mac-address = [ 00 00 00 00 00 00 ];
153 interrupts = <1f 2 20 2 21 2>;
154 interrupt-parent = <&mpic>;
155 phy-handle = <&phy2>;
156 phy-connection-type = "rgmii-id";
157 };
159 ethernet@27000 {
160 #address-cells = <1>;
161 #size-cells = <0>;
162 device_type = "network";
163 model = "eTSEC";
164 compatible = "gianfar";
165 reg = <27000 1000>;
166 local-mac-address = [ 00 00 00 00 00 00 ];
167 interrupts = <25 2 26 2 27 2>;
168 interrupt-parent = <&mpic>;
169 phy-handle = <&phy3>;
170 phy-connection-type = "rgmii-id";
171 };
173 serial@4500 {
174 device_type = "serial";
175 compatible = "ns16550";
176 reg = <4500 100>;
177 clock-frequency = <0>;
178 interrupts = <2a 2>;
179 interrupt-parent = <&mpic>;
180 };
182 serial@4600 {
183 device_type = "serial";
184 compatible = "ns16550";
185 reg = <4600 100>;
186 clock-frequency = <0>;
187 interrupts = <2a 2>;
188 interrupt-parent = <&mpic>;
189 };
191 global-utilities@e0000 { //global utilities block
192 compatible = "fsl,mpc8572-guts";
193 reg = <e0000 1000>;
194 fsl,has-rstcr;
195 };
197 mpic: pic@40000 {
198 clock-frequency = <0>;
199 interrupt-controller;
200 #address-cells = <0>;
201 #interrupt-cells = <2>;
202 reg = <40000 40000>;
203 compatible = "chrp,open-pic";
204 device_type = "open-pic";
205 big-endian;
206 };
207 };
209 pcie@ffe08000 {
210 compatible = "fsl,mpc8548-pcie";
211 device_type = "pci";
212 #interrupt-cells = <1>;
213 #size-cells = <2>;
214 #address-cells = <3>;
215 reg = <ffe08000 1000>;
216 bus-range = <0 ff>;
217 ranges = <02000000 0 80000000 80000000 0 20000000
218 01000000 0 00000000 ffc00000 0 00010000>;
219 clock-frequency = <1fca055>;
220 interrupt-parent = <&mpic>;
221 interrupts = <18 2>;
222 interrupt-map-mask = <ff00 0 0 7>;
223 interrupt-map = <
224 /* IDSEL 0x11 func 0 - PCI slot 1 */
225 8800 0 0 1 &mpic 2 1
226 8800 0 0 2 &mpic 3 1
227 8800 0 0 3 &mpic 4 1
228 8800 0 0 4 &mpic 1 1
230 /* IDSEL 0x11 func 1 - PCI slot 1 */
231 8900 0 0 1 &mpic 2 1
232 8900 0 0 2 &mpic 3 1
233 8900 0 0 3 &mpic 4 1
234 8900 0 0 4 &mpic 1 1
236 /* IDSEL 0x11 func 2 - PCI slot 1 */
237 8a00 0 0 1 &mpic 2 1
238 8a00 0 0 2 &mpic 3 1
239 8a00 0 0 3 &mpic 4 1
240 8a00 0 0 4 &mpic 1 1
242 /* IDSEL 0x11 func 3 - PCI slot 1 */
243 8b00 0 0 1 &mpic 2 1
244 8b00 0 0 2 &mpic 3 1
245 8b00 0 0 3 &mpic 4 1
246 8b00 0 0 4 &mpic 1 1
248 /* IDSEL 0x11 func 4 - PCI slot 1 */
249 8c00 0 0 1 &mpic 2 1
250 8c00 0 0 2 &mpic 3 1
251 8c00 0 0 3 &mpic 4 1
252 8c00 0 0 4 &mpic 1 1
254 /* IDSEL 0x11 func 5 - PCI slot 1 */
255 8d00 0 0 1 &mpic 2 1
256 8d00 0 0 2 &mpic 3 1
257 8d00 0 0 3 &mpic 4 1
258 8d00 0 0 4 &mpic 1 1
260 /* IDSEL 0x11 func 6 - PCI slot 1 */
261 8e00 0 0 1 &mpic 2 1
262 8e00 0 0 2 &mpic 3 1
263 8e00 0 0 3 &mpic 4 1
264 8e00 0 0 4 &mpic 1 1
266 /* IDSEL 0x11 func 7 - PCI slot 1 */
267 8f00 0 0 1 &mpic 2 1
268 8f00 0 0 2 &mpic 3 1
269 8f00 0 0 3 &mpic 4 1
270 8f00 0 0 4 &mpic 1 1
272 /* IDSEL 0x12 func 0 - PCI slot 2 */
273 9000 0 0 1 &mpic 3 1
274 9000 0 0 2 &mpic 4 1
275 9000 0 0 3 &mpic 1 1
276 9000 0 0 4 &mpic 2 1
278 /* IDSEL 0x12 func 1 - PCI slot 2 */
279 9100 0 0 1 &mpic 3 1
280 9100 0 0 2 &mpic 4 1
281 9100 0 0 3 &mpic 1 1
282 9100 0 0 4 &mpic 2 1
284 /* IDSEL 0x12 func 2 - PCI slot 2 */
285 9200 0 0 1 &mpic 3 1
286 9200 0 0 2 &mpic 4 1
287 9200 0 0 3 &mpic 1 1
288 9200 0 0 4 &mpic 2 1
290 /* IDSEL 0x12 func 3 - PCI slot 2 */
291 9300 0 0 1 &mpic 3 1
292 9300 0 0 2 &mpic 4 1
293 9300 0 0 3 &mpic 1 1
294 9300 0 0 4 &mpic 2 1
296 /* IDSEL 0x12 func 4 - PCI slot 2 */
297 9400 0 0 1 &mpic 3 1
298 9400 0 0 2 &mpic 4 1
299 9400 0 0 3 &mpic 1 1
300 9400 0 0 4 &mpic 2 1
302 /* IDSEL 0x12 func 5 - PCI slot 2 */
303 9500 0 0 1 &mpic 3 1
304 9500 0 0 2 &mpic 4 1
305 9500 0 0 3 &mpic 1 1
306 9500 0 0 4 &mpic 2 1
308 /* IDSEL 0x12 func 6 - PCI slot 2 */
309 9600 0 0 1 &mpic 3 1
310 9600 0 0 2 &mpic 4 1
311 9600 0 0 3 &mpic 1 1
312 9600 0 0 4 &mpic 2 1
314 /* IDSEL 0x12 func 7 - PCI slot 2 */
315 9700 0 0 1 &mpic 3 1
316 9700 0 0 2 &mpic 4 1
317 9700 0 0 3 &mpic 1 1
318 9700 0 0 4 &mpic 2 1
320 // IDSEL 0x1c USB
321 e000 0 0 1 &i8259 c 2
322 e100 0 0 1 &i8259 9 2
323 e200 0 0 1 &i8259 a 2
324 e300 0 0 1 &i8259 b 2
326 // IDSEL 0x1d Audio
327 e800 0 0 1 &i8259 6 2
329 // IDSEL 0x1e Legacy
330 f000 0 0 1 &i8259 7 2
331 f100 0 0 1 &i8259 7 2
333 // IDSEL 0x1f IDE/SATA
334 f800 0 0 1 &i8259 e 2
335 f900 0 0 1 &i8259 5 2
337 >;
339 pcie@0 {
340 reg = <0 0 0 0 0>;
341 #size-cells = <2>;
342 #address-cells = <3>;
343 device_type = "pci";
344 ranges = <02000000 0 80000000
345 02000000 0 80000000
346 0 20000000
348 01000000 0 00000000
349 01000000 0 00000000
350 0 00100000>;
351 uli1575@0 {
352 reg = <0 0 0 0 0>;
353 #size-cells = <2>;
354 #address-cells = <3>;
355 ranges = <02000000 0 80000000
356 02000000 0 80000000
357 0 20000000
359 01000000 0 00000000
360 01000000 0 00000000
361 0 00100000>;
362 isa@1e {
363 device_type = "isa";
364 #interrupt-cells = <2>;
365 #size-cells = <1>;
366 #address-cells = <2>;
367 reg = <f000 0 0 0 0>;
368 ranges = <1 0 01000000 0 0
369 00001000>;
370 interrupt-parent = <&i8259>;
372 i8259: interrupt-controller@20 {
373 reg = <1 20 2
374 1 a0 2
375 1 4d0 2>;
376 interrupt-controller;
377 device_type = "interrupt-controller";
378 #address-cells = <0>;
379 #interrupt-cells = <2>;
380 compatible = "chrp,iic";
381 interrupts = <9 2>;
382 interrupt-parent = <&mpic>;
383 };
385 i8042@60 {
386 #size-cells = <0>;
387 #address-cells = <1>;
388 reg = <1 60 1 1 64 1>;
389 interrupts = <1 3 c 3>;
390 interrupt-parent =
391 <&i8259>;
393 keyboard@0 {
394 reg = <0>;
395 compatible = "pnpPNP,303";
396 };
398 mouse@1 {
399 reg = <1>;
400 compatible = "pnpPNP,f03";
401 };
402 };
404 rtc@70 {
405 compatible = "pnpPNP,b00";
406 reg = <1 70 2>;
407 };
409 gpio@400 {
410 reg = <1 400 80>;
411 };
412 };
413 };
414 };
416 };
418 pcie@ffe09000 {
419 compatible = "fsl,mpc8548-pcie";
420 device_type = "pci";
421 #interrupt-cells = <1>;
422 #size-cells = <2>;
423 #address-cells = <3>;
424 reg = <ffe09000 1000>;
425 bus-range = <0 ff>;
426 ranges = <02000000 0 a0000000 a0000000 0 20000000
427 01000000 0 00000000 ffc10000 0 00010000>;
428 clock-frequency = <1fca055>;
429 interrupt-parent = <&mpic>;
430 interrupts = <1a 2>;
431 interrupt-map-mask = <f800 0 0 7>;
432 interrupt-map = <
433 /* IDSEL 0x0 */
434 0000 0 0 1 &mpic 4 1
435 0000 0 0 2 &mpic 5 1
436 0000 0 0 3 &mpic 6 1
437 0000 0 0 4 &mpic 7 1
438 >;
439 pcie@0 {
440 reg = <0 0 0 0 0>;
441 #size-cells = <2>;
442 #address-cells = <3>;
443 device_type = "pci";
444 ranges = <02000000 0 a0000000
445 02000000 0 a0000000
446 0 20000000
448 01000000 0 00000000
449 01000000 0 00000000
450 0 00100000>;
451 };
452 };
454 pcie@ffe0a000 {
455 compatible = "fsl,mpc8548-pcie";
456 device_type = "pci";
457 #interrupt-cells = <1>;
458 #size-cells = <2>;
459 #address-cells = <3>;
460 reg = <ffe0a000 1000>;
461 bus-range = <0 ff>;
462 ranges = <02000000 0 c0000000 c0000000 0 20000000
463 01000000 0 00000000 ffc20000 0 00010000>;
464 clock-frequency = <1fca055>;
465 interrupt-parent = <&mpic>;
466 interrupts = <1b 2>;
467 interrupt-map = <
468 /* IDSEL 0x0 */
469 0000 0 0 1 &mpic 0 1
470 0000 0 0 2 &mpic 1 1
471 0000 0 0 3 &mpic 2 1
472 0000 0 0 4 &mpic 3 1
473 >;
474 pcie@0 {
475 reg = <0 0 0 0 0>;
476 #size-cells = <2>;
477 #address-cells = <3>;
478 device_type = "pci";
479 ranges = <02000000 0 c0000000
480 02000000 0 c0000000
481 0 20000000
483 01000000 0 00000000
484 01000000 0 00000000
485 0 00100000>;
486 };
487 };
488 };