| blob | e0c850d85c530b933515a123bf66fb42d81ebed2 |
1 /*
2 * This file contains miscellaneous low-level functions.
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
6 * and Paul Mackerras.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 *
13 */
15 #include <linux/sys.h>
16 #include <asm/unistd.h>
17 #include <asm/errno.h>
18 #include <asm/processor.h>
19 #include <asm/page.h>
20 #include <asm/cache.h>
21 #include <asm/cputable.h>
22 #include <asm/mmu.h>
23 #include <asm/ppc_asm.h>
24 #include <asm/thread_info.h>
25 #include <asm/asm-offsets.h>
27 #ifdef CONFIG_8xx
28 #define ISYNC_8xx isync
29 #else
30 #define ISYNC_8xx
31 #endif
32 .text
34 .align 5
35 _GLOBAL(__delay)
36 cmpwi 0,r3,0
37 mtctr r3
38 beqlr
39 1: bdnz 1b
40 blr
42 /*
43 * Returns (address we're running at) - (address we were linked at)
44 * for use before the text and data are mapped to KERNELBASE.
45 */
46 _GLOBAL(reloc_offset)
47 mflr r0
48 bl 1f
49 1: mflr r3
50 lis r4,1b@ha
51 addi r4,r4,1b@l
52 subf r3,r4,r3
53 mtlr r0
54 blr
56 /*
57 * add_reloc_offset(x) returns x + reloc_offset().
58 */
59 _GLOBAL(add_reloc_offset)
60 mflr r0
61 bl 1f
62 1: mflr r5
63 lis r4,1b@ha
64 addi r4,r4,1b@l
65 subf r5,r4,r5
66 add r3,r3,r5
67 mtlr r0
68 blr
70 /*
71 * sub_reloc_offset(x) returns x - reloc_offset().
72 */
73 _GLOBAL(sub_reloc_offset)
74 mflr r0
75 bl 1f
76 1: mflr r5
77 lis r4,1b@ha
78 addi r4,r4,1b@l
79 subf r5,r4,r5
80 subf r3,r5,r3
81 mtlr r0
82 blr
84 /*
85 * reloc_got2 runs through the .got2 section adding an offset
86 * to each entry.
87 */
88 _GLOBAL(reloc_got2)
89 mflr r11
90 lis r7,__got2_start@ha
91 addi r7,r7,__got2_start@l
92 lis r8,__got2_end@ha
93 addi r8,r8,__got2_end@l
94 subf r8,r7,r8
95 srwi. r8,r8,2
96 beqlr
97 mtctr r8
98 bl 1f
99 1: mflr r0
100 lis r4,1b@ha
101 addi r4,r4,1b@l
102 subf r0,r4,r0
103 add r7,r0,r7
104 2: lwz r0,0(r7)
105 add r0,r0,r3
106 stw r0,0(r7)
107 addi r7,r7,4
108 bdnz 2b
109 mtlr r11
110 blr
112 /*
113 * call_setup_cpu - call the setup_cpu function for this cpu
114 * r3 = data offset, r24 = cpu number
115 *
116 * Setup function is called with:
117 * r3 = data offset
118 * r4 = ptr to CPU spec (relocated)
119 */
120 _GLOBAL(call_setup_cpu)
121 addis r4,r3,cur_cpu_spec@ha
122 addi r4,r4,cur_cpu_spec@l
123 lwz r4,0(r4)
124 add r4,r4,r3
125 lwz r5,CPU_SPEC_SETUP(r4)
126 cmpi 0,r5,0
127 add r5,r5,r3
128 beqlr
129 mtctr r5
130 bctr
132 /*
133 * complement mask on the msr then "or" some values on.
134 * _nmask_and_or_msr(nmask, value_to_or)
135 */
136 _GLOBAL(_nmask_and_or_msr)
137 mfmsr r0 /* Get current msr */
138 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
139 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
140 SYNC /* Some chip revs have problems here... */
141 mtmsr r0 /* Update machine state */
142 isync
143 blr /* Done */
146 /*
147 * Flush MMU TLB
148 */
149 _GLOBAL(_tlbia)
150 #if defined(CONFIG_40x)
151 sync /* Flush to memory before changing mapping */
152 tlbia
153 isync /* Flush shadow TLB */
154 #elif defined(CONFIG_44x)
155 li r3,0
156 sync
158 /* Load high watermark */
159 lis r4,tlb_44x_hwater@ha
160 lwz r5,tlb_44x_hwater@l(r4)
162 1: tlbwe r3,r3,PPC44x_TLB_PAGEID
163 addi r3,r3,1
164 cmpw 0,r3,r5
165 ble 1b
167 isync
168 #elif defined(CONFIG_FSL_BOOKE)
169 /* Invalidate all entries in TLB0 */
170 li r3, 0x04
171 tlbivax 0,3
172 /* Invalidate all entries in TLB1 */
173 li r3, 0x0c
174 tlbivax 0,3
175 /* Invalidate all entries in TLB2 */
176 li r3, 0x14
177 tlbivax 0,3
178 /* Invalidate all entries in TLB3 */
179 li r3, 0x1c
180 tlbivax 0,3
181 msync
182 #ifdef CONFIG_SMP
183 tlbsync
184 #endif /* CONFIG_SMP */
185 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
186 #if defined(CONFIG_SMP)
187 rlwinm r8,r1,0,0,18
188 lwz r8,TI_CPU(r8)
189 oris r8,r8,10
190 mfmsr r10
191 SYNC
192 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
193 rlwinm r0,r0,0,28,26 /* clear DR */
194 mtmsr r0
195 SYNC_601
196 isync
197 lis r9,mmu_hash_lock@h
198 ori r9,r9,mmu_hash_lock@l
199 tophys(r9,r9)
200 10: lwarx r7,0,r9
201 cmpwi 0,r7,0
202 bne- 10b
203 stwcx. r8,0,r9
204 bne- 10b
205 sync
206 tlbia
207 sync
208 TLBSYNC
209 li r0,0
210 stw r0,0(r9) /* clear mmu_hash_lock */
211 mtmsr r10
212 SYNC_601
213 isync
214 #else /* CONFIG_SMP */
215 sync
216 tlbia
217 sync
218 #endif /* CONFIG_SMP */
219 #endif /* ! defined(CONFIG_40x) */
220 blr
222 /*
223 * Flush MMU TLB for a particular address
224 */
225 _GLOBAL(_tlbie)
226 #if defined(CONFIG_40x)
227 /* We run the search with interrupts disabled because we have to change
228 * the PID and I don't want to preempt when that happens.
229 */
230 mfmsr r5
231 mfspr r6,SPRN_PID
232 wrteei 0
233 mtspr SPRN_PID,r4
234 tlbsx. r3, 0, r3
235 mtspr SPRN_PID,r6
236 wrtee r5
237 bne 10f
238 sync
239 /* There are only 64 TLB entries, so r3 < 64, which means bit 25 is clear.
240 * Since 25 is the V bit in the TLB_TAG, loading this value will invalidate
241 * the TLB entry. */
242 tlbwe r3, r3, TLB_TAG
243 isync
244 10:
245 #elif defined(CONFIG_44x)
246 mfspr r5,SPRN_MMUCR
247 rlwimi r5,r4,0,24,31 /* Set TID */
249 /* We have to run the search with interrupts disabled, even critical
250 * and debug interrupts (in fact the only critical exceptions we have
251 * are debug and machine check). Otherwise an interrupt which causes
252 * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */
253 mfmsr r4
254 lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha
255 addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l
256 andc r6,r4,r6
257 mtmsr r6
258 mtspr SPRN_MMUCR,r5
259 tlbsx. r3, 0, r3
260 mtmsr r4
261 bne 10f
262 sync
263 /* There are only 64 TLB entries, so r3 < 64,
264 * which means bit 22, is clear. Since 22 is
265 * the V bit in the TLB_PAGEID, loading this
266 * value will invalidate the TLB entry.
267 */
268 tlbwe r3, r3, PPC44x_TLB_PAGEID
269 isync
270 10:
271 #elif defined(CONFIG_FSL_BOOKE)
272 rlwinm r4, r3, 0, 0, 19
273 ori r5, r4, 0x08 /* TLBSEL = 1 */
274 ori r6, r4, 0x10 /* TLBSEL = 2 */
275 ori r7, r4, 0x18 /* TLBSEL = 3 */
276 tlbivax 0, r4
277 tlbivax 0, r5
278 tlbivax 0, r6
279 tlbivax 0, r7
280 msync
281 #if defined(CONFIG_SMP)
282 tlbsync
283 #endif /* CONFIG_SMP */
284 #else /* !(CONFIG_40x || CONFIG_44x || CONFIG_FSL_BOOKE) */
285 #if defined(CONFIG_SMP)
286 rlwinm r8,r1,0,0,18
287 lwz r8,TI_CPU(r8)
288 oris r8,r8,11
289 mfmsr r10
290 SYNC
291 rlwinm r0,r10,0,17,15 /* clear bit 16 (MSR_EE) */
292 rlwinm r0,r0,0,28,26 /* clear DR */
293 mtmsr r0
294 SYNC_601
295 isync
296 lis r9,mmu_hash_lock@h
297 ori r9,r9,mmu_hash_lock@l
298 tophys(r9,r9)
299 10: lwarx r7,0,r9
300 cmpwi 0,r7,0
301 bne- 10b
302 stwcx. r8,0,r9
303 bne- 10b
304 eieio
305 tlbie r3
306 sync
307 TLBSYNC
308 li r0,0
309 stw r0,0(r9) /* clear mmu_hash_lock */
310 mtmsr r10
311 SYNC_601
312 isync
313 #else /* CONFIG_SMP */
314 tlbie r3
315 sync
316 #endif /* CONFIG_SMP */
317 #endif /* ! CONFIG_40x */
318 blr
320 /*
321 * Flush instruction cache.
322 * This is a no-op on the 601.
323 */
324 _GLOBAL(flush_instruction_cache)
325 #if defined(CONFIG_8xx)
326 isync
327 lis r5, IDC_INVALL@h
328 mtspr SPRN_IC_CST, r5
329 #elif defined(CONFIG_4xx)
330 #ifdef CONFIG_403GCX
331 li r3, 512
332 mtctr r3
333 lis r4, KERNELBASE@h
334 1: iccci 0, r4
335 addi r4, r4, 16
336 bdnz 1b
337 #else
338 lis r3, KERNELBASE@h
339 iccci 0,r3
340 #endif
341 #elif CONFIG_FSL_BOOKE
342 BEGIN_FTR_SECTION
343 mfspr r3,SPRN_L1CSR0
344 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
345 /* msync; isync recommended here */
346 mtspr SPRN_L1CSR0,r3
347 isync
348 blr
349 END_FTR_SECTION_IFSET(CPU_FTR_UNIFIED_ID_CACHE)
350 mfspr r3,SPRN_L1CSR1
351 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
352 mtspr SPRN_L1CSR1,r3
353 #else
354 mfspr r3,SPRN_PVR
355 rlwinm r3,r3,16,16,31
356 cmpwi 0,r3,1
357 beqlr /* for 601, do nothing */
358 /* 603/604 processor - use invalidate-all bit in HID0 */
359 mfspr r3,SPRN_HID0
360 ori r3,r3,HID0_ICFI
361 mtspr SPRN_HID0,r3
362 #endif /* CONFIG_8xx/4xx */
363 isync
364 blr
366 /*
367 * Write any modified data cache blocks out to memory
368 * and invalidate the corresponding instruction cache blocks.
369 * This is a no-op on the 601.
370 *
371 * __flush_icache_range(unsigned long start, unsigned long stop)
372 */
373 _GLOBAL(__flush_icache_range)
374 BEGIN_FTR_SECTION
375 blr /* for 601, do nothing */
376 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
377 li r5,L1_CACHE_BYTES-1
378 andc r3,r3,r5
379 subf r4,r3,r4
380 add r4,r4,r5
381 srwi. r4,r4,L1_CACHE_SHIFT
382 beqlr
383 mtctr r4
384 mr r6,r3
385 1: dcbst 0,r3
386 addi r3,r3,L1_CACHE_BYTES
387 bdnz 1b
388 sync /* wait for dcbst's to get to ram */
389 mtctr r4
390 2: icbi 0,r6
391 addi r6,r6,L1_CACHE_BYTES
392 bdnz 2b
393 sync /* additional sync needed on g4 */
394 isync
395 blr
396 /*
397 * Write any modified data cache blocks out to memory.
398 * Does not invalidate the corresponding cache lines (especially for
399 * any corresponding instruction cache).
400 *
401 * clean_dcache_range(unsigned long start, unsigned long stop)
402 */
403 _GLOBAL(clean_dcache_range)
404 li r5,L1_CACHE_BYTES-1
405 andc r3,r3,r5
406 subf r4,r3,r4
407 add r4,r4,r5
408 srwi. r4,r4,L1_CACHE_SHIFT
409 beqlr
410 mtctr r4
412 1: dcbst 0,r3
413 addi r3,r3,L1_CACHE_BYTES
414 bdnz 1b
415 sync /* wait for dcbst's to get to ram */
416 blr
418 /*
419 * Write any modified data cache blocks out to memory and invalidate them.
420 * Does not invalidate the corresponding instruction cache blocks.
421 *
422 * flush_dcache_range(unsigned long start, unsigned long stop)
423 */
424 _GLOBAL(flush_dcache_range)
425 li r5,L1_CACHE_BYTES-1
426 andc r3,r3,r5
427 subf r4,r3,r4
428 add r4,r4,r5
429 srwi. r4,r4,L1_CACHE_SHIFT
430 beqlr
431 mtctr r4
433 1: dcbf 0,r3
434 addi r3,r3,L1_CACHE_BYTES
435 bdnz 1b
436 sync /* wait for dcbst's to get to ram */
437 blr
439 /*
440 * Like above, but invalidate the D-cache. This is used by the 8xx
441 * to invalidate the cache so the PPC core doesn't get stale data
442 * from the CPM (no cache snooping here :-).
443 *
444 * invalidate_dcache_range(unsigned long start, unsigned long stop)
445 */
446 _GLOBAL(invalidate_dcache_range)
447 li r5,L1_CACHE_BYTES-1
448 andc r3,r3,r5
449 subf r4,r3,r4
450 add r4,r4,r5
451 srwi. r4,r4,L1_CACHE_SHIFT
452 beqlr
453 mtctr r4
455 1: dcbi 0,r3
456 addi r3,r3,L1_CACHE_BYTES
457 bdnz 1b
458 sync /* wait for dcbi's to get to ram */
459 blr
461 #ifdef CONFIG_NOT_COHERENT_CACHE
462 /*
463 * 40x cores have 8K or 16K dcache and 32 byte line size.
464 * 44x has a 32K dcache and 32 byte line size.
465 * 8xx has 1, 2, 4, 8K variants.
466 * For now, cover the worst case of the 44x.
467 * Must be called with external interrupts disabled.
468 */
469 #define CACHE_NWAYS 64
470 #define CACHE_NLINES 16
472 _GLOBAL(flush_dcache_all)
473 li r4, (2 * CACHE_NWAYS * CACHE_NLINES)
474 mtctr r4
475 lis r5, KERNELBASE@h
476 1: lwz r3, 0(r5) /* Load one word from every line */
477 addi r5, r5, L1_CACHE_BYTES
478 bdnz 1b
479 blr
480 #endif /* CONFIG_NOT_COHERENT_CACHE */
482 /*
483 * Flush a particular page from the data cache to RAM.
484 * Note: this is necessary because the instruction cache does *not*
485 * snoop from the data cache.
486 * This is a no-op on the 601 which has a unified cache.
487 *
488 * void __flush_dcache_icache(void *page)
489 */
490 _GLOBAL(__flush_dcache_icache)
491 BEGIN_FTR_SECTION
492 blr /* for 601, do nothing */
493 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
494 rlwinm r3,r3,0,0,19 /* Get page base address */
495 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
496 mtctr r4
497 mr r6,r3
498 0: dcbst 0,r3 /* Write line to ram */
499 addi r3,r3,L1_CACHE_BYTES
500 bdnz 0b
501 sync
502 #ifndef CONFIG_44x
503 /* We don't flush the icache on 44x. Those have a virtual icache
504 * and we don't have access to the virtual address here (it's
505 * not the page vaddr but where it's mapped in user space). The
506 * flushing of the icache on these is handled elsewhere, when
507 * a change in the address space occurs, before returning to
508 * user space
509 */
510 mtctr r4
511 1: icbi 0,r6
512 addi r6,r6,L1_CACHE_BYTES
513 bdnz 1b
514 sync
515 isync
516 #endif /* CONFIG_44x */
517 blr
519 /*
520 * Flush a particular page from the data cache to RAM, identified
521 * by its physical address. We turn off the MMU so we can just use
522 * the physical address (this may be a highmem page without a kernel
523 * mapping).
524 *
525 * void __flush_dcache_icache_phys(unsigned long physaddr)
526 */
527 _GLOBAL(__flush_dcache_icache_phys)
528 BEGIN_FTR_SECTION
529 blr /* for 601, do nothing */
530 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
531 mfmsr r10
532 rlwinm r0,r10,0,28,26 /* clear DR */
533 mtmsr r0
534 isync
535 rlwinm r3,r3,0,0,19 /* Get page base address */
536 li r4,4096/L1_CACHE_BYTES /* Number of lines in a page */
537 mtctr r4
538 mr r6,r3
539 0: dcbst 0,r3 /* Write line to ram */
540 addi r3,r3,L1_CACHE_BYTES
541 bdnz 0b
542 sync
543 mtctr r4
544 1: icbi 0,r6
545 addi r6,r6,L1_CACHE_BYTES
546 bdnz 1b
547 sync
548 mtmsr r10 /* restore DR */
549 isync
550 blr
552 /*
553 * Clear pages using the dcbz instruction, which doesn't cause any
554 * memory traffic (except to write out any cache lines which get
555 * displaced). This only works on cacheable memory.
556 *
557 * void clear_pages(void *page, int order) ;
558 */
559 _GLOBAL(clear_pages)
560 li r0,4096/L1_CACHE_BYTES
561 slw r0,r0,r4
562 mtctr r0
563 #ifdef CONFIG_8xx
564 li r4, 0
565 1: stw r4, 0(r3)
566 stw r4, 4(r3)
567 stw r4, 8(r3)
568 stw r4, 12(r3)
569 #else
570 1: dcbz 0,r3
571 #endif
572 addi r3,r3,L1_CACHE_BYTES
573 bdnz 1b
574 blr
576 /*
577 * Copy a whole page. We use the dcbz instruction on the destination
578 * to reduce memory traffic (it eliminates the unnecessary reads of
579 * the destination into cache). This requires that the destination
580 * is cacheable.
581 */
582 #define COPY_16_BYTES \
583 lwz r6,4(r4); \
584 lwz r7,8(r4); \
585 lwz r8,12(r4); \
586 lwzu r9,16(r4); \
587 stw r6,4(r3); \
588 stw r7,8(r3); \
589 stw r8,12(r3); \
590 stwu r9,16(r3)
592 _GLOBAL(copy_page)
593 addi r3,r3,-4
594 addi r4,r4,-4
596 #ifdef CONFIG_8xx
597 /* don't use prefetch on 8xx */
598 li r0,4096/L1_CACHE_BYTES
599 mtctr r0
600 1: COPY_16_BYTES
601 bdnz 1b
602 blr
604 #else /* not 8xx, we can prefetch */
605 li r5,4
607 #if MAX_COPY_PREFETCH > 1
608 li r0,MAX_COPY_PREFETCH
609 li r11,4
610 mtctr r0
611 11: dcbt r11,r4
612 addi r11,r11,L1_CACHE_BYTES
613 bdnz 11b
614 #else /* MAX_COPY_PREFETCH == 1 */
615 dcbt r5,r4
616 li r11,L1_CACHE_BYTES+4
617 #endif /* MAX_COPY_PREFETCH */
618 li r0,4096/L1_CACHE_BYTES - MAX_COPY_PREFETCH
619 crclr 4*cr0+eq
620 2:
621 mtctr r0
622 1:
623 dcbt r11,r4
624 dcbz r5,r3
625 COPY_16_BYTES
626 #if L1_CACHE_BYTES >= 32
627 COPY_16_BYTES
628 #if L1_CACHE_BYTES >= 64
629 COPY_16_BYTES
630 COPY_16_BYTES
631 #if L1_CACHE_BYTES >= 128
632 COPY_16_BYTES
633 COPY_16_BYTES
634 COPY_16_BYTES
635 COPY_16_BYTES
636 #endif
637 #endif
638 #endif
639 bdnz 1b
640 beqlr
641 crnot 4*cr0+eq,4*cr0+eq
642 li r0,MAX_COPY_PREFETCH
643 li r11,4
644 b 2b
645 #endif /* CONFIG_8xx */
647 /*
648 * void atomic_clear_mask(atomic_t mask, atomic_t *addr)
649 * void atomic_set_mask(atomic_t mask, atomic_t *addr);
650 */
651 _GLOBAL(atomic_clear_mask)
652 10: lwarx r5,0,r4
653 andc r5,r5,r3
654 PPC405_ERR77(0,r4)
655 stwcx. r5,0,r4
656 bne- 10b
657 blr
658 _GLOBAL(atomic_set_mask)
659 10: lwarx r5,0,r4
660 or r5,r5,r3
661 PPC405_ERR77(0,r4)
662 stwcx. r5,0,r4
663 bne- 10b
664 blr
666 /*
667 * I/O string operations
668 *
669 * insb(port, buf, len)
670 * outsb(port, buf, len)
671 * insw(port, buf, len)
672 * outsw(port, buf, len)
673 * insl(port, buf, len)
674 * outsl(port, buf, len)
675 * insw_ns(port, buf, len)
676 * outsw_ns(port, buf, len)
677 * insl_ns(port, buf, len)
678 * outsl_ns(port, buf, len)
679 *
680 * The *_ns versions don't do byte-swapping.
681 */
682 _GLOBAL(_insb)
683 cmpwi 0,r5,0
684 mtctr r5
685 subi r4,r4,1
686 blelr-
687 00: lbz r5,0(r3)
688 01: eieio
689 02: stbu r5,1(r4)
690 ISYNC_8xx
691 .section .fixup,"ax"
692 03: blr
693 .text
694 .section __ex_table, "a"
695 .align 2
696 .long 00b, 03b
697 .long 01b, 03b
698 .long 02b, 03b
699 .text
700 bdnz 00b
701 blr
703 _GLOBAL(_outsb)
704 cmpwi 0,r5,0
705 mtctr r5
706 subi r4,r4,1
707 blelr-
708 00: lbzu r5,1(r4)
709 01: stb r5,0(r3)
710 02: eieio
711 ISYNC_8xx
712 .section .fixup,"ax"
713 03: blr
714 .text
715 .section __ex_table, "a"
716 .align 2
717 .long 00b, 03b
718 .long 01b, 03b
719 .long 02b, 03b
720 .text
721 bdnz 00b
722 blr
724 _GLOBAL(_insw_ns)
725 cmpwi 0,r5,0
726 mtctr r5
727 subi r4,r4,2
728 blelr-
729 00: lhz r5,0(r3)
730 01: eieio
731 02: sthu r5,2(r4)
732 ISYNC_8xx
733 .section .fixup,"ax"
734 03: blr
735 .text
736 .section __ex_table, "a"
737 .align 2
738 .long 00b, 03b
739 .long 01b, 03b
740 .long 02b, 03b
741 .text
742 bdnz 00b
743 blr
745 _GLOBAL(_outsw_ns)
746 cmpwi 0,r5,0
747 mtctr r5
748 subi r4,r4,2
749 blelr-
750 00: lhzu r5,2(r4)
751 01: sth r5,0(r3)
752 02: eieio
753 ISYNC_8xx
754 .section .fixup,"ax"
755 03: blr
756 .text
757 .section __ex_table, "a"
758 .align 2
759 .long 00b, 03b
760 .long 01b, 03b
761 .long 02b, 03b
762 .text
763 bdnz 00b
764 blr
766 _GLOBAL(_insl_ns)
767 cmpwi 0,r5,0
768 mtctr r5
769 subi r4,r4,4
770 blelr-
771 00: lwz r5,0(r3)
772 01: eieio
773 02: stwu r5,4(r4)
774 ISYNC_8xx
775 .section .fixup,"ax"
776 03: blr
777 .text
778 .section __ex_table, "a"
779 .align 2
780 .long 00b, 03b
781 .long 01b, 03b
782 .long 02b, 03b
783 .text
784 bdnz 00b
785 blr
787 _GLOBAL(_outsl_ns)
788 cmpwi 0,r5,0
789 mtctr r5
790 subi r4,r4,4
791 blelr-
792 00: lwzu r5,4(r4)
793 01: stw r5,0(r3)
794 02: eieio
795 ISYNC_8xx
796 .section .fixup,"ax"
797 03: blr
798 .text
799 .section __ex_table, "a"
800 .align 2
801 .long 00b, 03b
802 .long 01b, 03b
803 .long 02b, 03b
804 .text
805 bdnz 00b
806 blr
808 /*
809 * Extended precision shifts.
810 *
811 * Updated to be valid for shift counts from 0 to 63 inclusive.
812 * -- Gabriel
813 *
814 * R3/R4 has 64 bit value
815 * R5 has shift count
816 * result in R3/R4
817 *
818 * ashrdi3: arithmetic right shift (sign propagation)
819 * lshrdi3: logical right shift
820 * ashldi3: left shift
821 */
822 _GLOBAL(__ashrdi3)
823 subfic r6,r5,32
824 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
825 addi r7,r5,32 # could be xori, or addi with -32
826 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
827 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
828 sraw r7,r3,r7 # t2 = MSW >> (count-32)
829 or r4,r4,r6 # LSW |= t1
830 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
831 sraw r3,r3,r5 # MSW = MSW >> count
832 or r4,r4,r7 # LSW |= t2
833 blr
835 _GLOBAL(__ashldi3)
836 subfic r6,r5,32
837 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
838 addi r7,r5,32 # could be xori, or addi with -32
839 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
840 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
841 or r3,r3,r6 # MSW |= t1
842 slw r4,r4,r5 # LSW = LSW << count
843 or r3,r3,r7 # MSW |= t2
844 blr
846 _GLOBAL(__lshrdi3)
847 subfic r6,r5,32
848 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
849 addi r7,r5,32 # could be xori, or addi with -32
850 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
851 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
852 or r4,r4,r6 # LSW |= t1
853 srw r3,r3,r5 # MSW = MSW >> count
854 or r4,r4,r7 # LSW |= t2
855 blr
857 _GLOBAL(abs)
858 srawi r4,r3,31
859 xor r3,r3,r4
860 sub r3,r3,r4
861 blr
863 _GLOBAL(_get_SP)
864 mr r3,r1 /* Close enough */
865 blr
867 /*
868 * Create a kernel thread
869 * kernel_thread(fn, arg, flags)
870 */
871 _GLOBAL(kernel_thread)
872 stwu r1,-16(r1)
873 stw r30,8(r1)
874 stw r31,12(r1)
875 mr r30,r3 /* function */
876 mr r31,r4 /* argument */
877 ori r3,r5,CLONE_VM /* flags */
878 oris r3,r3,CLONE_UNTRACED>>16
879 li r4,0 /* new sp (unused) */
880 li r0,__NR_clone
881 sc
882 cmpwi 0,r3,0 /* parent or child? */
883 bne 1f /* return if parent */
884 li r0,0 /* make top-level stack frame */
885 stwu r0,-16(r1)
886 mtlr r30 /* fn addr in lr */
887 mr r3,r31 /* load arg and call fn */
888 PPC440EP_ERR42
889 blrl
890 li r0,__NR_exit /* exit if function returns */
891 li r3,0
892 sc
893 1: lwz r30,8(r1)
894 lwz r31,12(r1)
895 addi r1,r1,16
896 blr
898 _GLOBAL(kernel_execve)
899 li r0,__NR_execve
900 sc
901 bnslr
902 neg r3,r3
903 blr
905 /*
906 * This routine is just here to keep GCC happy - sigh...
907 */
908 _GLOBAL(__main)
909 blr