?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86: add PAGE_KERNEL_EXEC_NOCACHE
[wrt350n-kernel.git] / arch / ppc / kernel / ppc_htab.c
blob9ed36dd9cbff3a08f4db0c79e4aa5f62fb68ae8f
1 /*
2 * PowerPC hash table management proc entry. Will show information
3 * about the current hash table and will allow changes to it.
4 *
5 * Written by Cort Dougan (cort@cs.nmt.edu)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/proc_fs.h>
16 #include <linux/stat.h>
17 #include <linux/sysctl.h>
18 #include <linux/capability.h>
19 #include <linux/ctype.h>
20 #include <linux/threads.h>
21 #include <linux/seq_file.h>
22 #include <linux/init.h>
23 #include <linux/bitops.h>
24
25 #include <asm/uaccess.h>
26 #include <asm/mmu.h>
27 #include <asm/residual.h>
28 #include <asm/io.h>
29 #include <asm/pgtable.h>
30 #include <asm/cputable.h>
31 #include <asm/system.h>
32 #include <asm/reg.h>
33
34 static int ppc_htab_show(struct seq_file *m, void *v);
35 static ssize_t ppc_htab_write(struct file * file, const char __user * buffer,
36 size_t count, loff_t *ppos);
37 extern PTE *Hash, *Hash_end;
38 extern unsigned long Hash_size, Hash_mask;
39 extern unsigned long _SDR1;
40 extern unsigned long htab_reloads;
41 extern unsigned long htab_preloads;
42 extern unsigned long htab_evicts;
43 extern unsigned long pte_misses;
44 extern unsigned long pte_errors;
45 extern unsigned int primary_pteg_full;
46 extern unsigned int htab_hash_searches;
47
48 static int ppc_htab_open(struct inode *inode, struct file *file)
49 {
50 return single_open(file, ppc_htab_show, NULL);
51 }
52
53 const struct file_operations ppc_htab_operations = {
54 .open = ppc_htab_open,
55 .read = seq_read,
56 .llseek = seq_lseek,
57 .write = ppc_htab_write,
58 .release = single_release,
59 };
60
61 static char *pmc1_lookup(unsigned long mmcr0)
62 {
63 switch ( mmcr0 & (0x7f<<7) )
64 {
65 case 0x0:
66 return "none";
67 case MMCR0_PMC1_CYCLES:
68 return "cycles";
69 case MMCR0_PMC1_ICACHEMISS:
70 return "ic miss";
71 case MMCR0_PMC1_DTLB:
72 return "dtlb miss";
73 default:
74 return "unknown";
75 }
76 }
77
78 static char *pmc2_lookup(unsigned long mmcr0)
79 {
80 switch ( mmcr0 & 0x3f )
81 {
82 case 0x0:
83 return "none";
84 case MMCR0_PMC2_CYCLES:
85 return "cycles";
86 case MMCR0_PMC2_DCACHEMISS:
87 return "dc miss";
88 case MMCR0_PMC2_ITLB:
89 return "itlb miss";
90 case MMCR0_PMC2_LOADMISSTIME:
91 return "load miss time";
92 default:
93 return "unknown";
94 }
95 }
96
97 /*
98 * print some useful info about the hash table. This function
99 * is _REALLY_ slow (see the nested for loops below) but nothing
100 * in here should be really timing critical. -- Cort
101 */
102 static int ppc_htab_show(struct seq_file *m, void *v)
103 {
104 unsigned long mmcr0 = 0, pmc1 = 0, pmc2 = 0;
105 #if defined(CONFIG_PPC_STD_MMU)
106 unsigned int kptes = 0, uptes = 0;
107 PTE *ptr;
108 #endif /* CONFIG_PPC_STD_MMU */
109
110 if (cpu_has_feature(CPU_FTR_604_PERF_MON)) {
111 mmcr0 = mfspr(SPRN_MMCR0);
112 pmc1 = mfspr(SPRN_PMC1);
113 pmc2 = mfspr(SPRN_PMC2);
114 seq_printf(m,
115 "604 Performance Monitoring\n"
116 "MMCR0\t\t: %08lx %s%s ",
117 mmcr0,
118 ( mmcr0>>28 & 0x2 ) ? "(user mode counted)" : "",
119 ( mmcr0>>28 & 0x4 ) ? "(kernel mode counted)" : "");
120 seq_printf(m,
121 "\nPMC1\t\t: %08lx (%s)\n"
122 "PMC2\t\t: %08lx (%s)\n",
123 pmc1, pmc1_lookup(mmcr0),
124 pmc2, pmc2_lookup(mmcr0));
125 }
126
127 #ifdef CONFIG_PPC_STD_MMU
128 /* if we don't have a htab */
129 if ( Hash_size == 0 ) {
130 seq_printf(m, "No Hash Table used\n");
131 return 0;
132 }
133
134 for (ptr = Hash; ptr < Hash_end; ptr++) {
135 unsigned int mctx, vsid;
136
137 if (!ptr->v)
138 continue;
139 /* undo the esid skew */
140 vsid = ptr->vsid;
141 mctx = ((vsid - (vsid & 0xf) * 0x111) >> 4) & 0xfffff;
142 if (mctx == 0)
143 kptes++;
144 else
145 uptes++;
146 }
147
148 seq_printf(m,
149 "PTE Hash Table Information\n"
150 "Size\t\t: %luKb\n"
151 "Buckets\t\t: %lu\n"
152 "Address\t\t: %08lx\n"
153 "Entries\t\t: %lu\n"
154 "User ptes\t: %u\n"
155 "Kernel ptes\t: %u\n"
156 "Percent full\t: %lu%%\n"
157 , (unsigned long)(Hash_size>>10),
158 (Hash_size/(sizeof(PTE)*8)),
159 (unsigned long)Hash,
160 Hash_size/sizeof(PTE)
161 , uptes,
162 kptes,
163 ((kptes+uptes)*100) / (Hash_size/sizeof(PTE))
164 );
165
166 seq_printf(m,
167 "Reloads\t\t: %lu\n"
168 "Preloads\t: %lu\n"
169 "Searches\t: %u\n"
170 "Overflows\t: %u\n"
171 "Evicts\t\t: %lu\n",
172 htab_reloads, htab_preloads, htab_hash_searches,
173 primary_pteg_full, htab_evicts);
174 #endif /* CONFIG_PPC_STD_MMU */
175
176 seq_printf(m,
177 "Non-error misses: %lu\n"
178 "Error misses\t: %lu\n",
179 pte_misses, pte_errors);
180 return 0;
181 }
182
183 /*
184 * Allow user to define performance counters and resize the hash table
185 */
186 static ssize_t ppc_htab_write(struct file * file, const char __user * ubuffer,
187 size_t count, loff_t *ppos)
188 {
189 #ifdef CONFIG_PPC_STD_MMU
190 unsigned long tmp;
191 char buffer[16];
192
193 if (!capable(CAP_SYS_ADMIN))
194 return -EACCES;
195 if (strncpy_from_user(buffer, ubuffer, 15))
196 return -EFAULT;
197 buffer[15] = 0;
198
199 /* don't set the htab size for now */
200 if ( !strncmp( buffer, "size ", 5) )
201 return -EBUSY;
202
203 if ( !strncmp( buffer, "reset", 5) )
204 {
205 if (cpu_has_feature(CPU_FTR_604_PERF_MON)) {
206 /* reset PMC1 and PMC2 */
207 mtspr(SPRN_PMC1, 0);
208 mtspr(SPRN_PMC2, 0);
209 }
210 htab_reloads = 0;
211 htab_evicts = 0;
212 pte_misses = 0;
213 pte_errors = 0;
214 }
215
216 /* Everything below here requires the performance monitor feature. */
217 if (!cpu_has_feature(CPU_FTR_604_PERF_MON))
218 return count;
219
220 /* turn off performance monitoring */
221 if ( !strncmp( buffer, "off", 3) )
222 {
223 mtspr(SPRN_MMCR0, 0);
224 mtspr(SPRN_PMC1, 0);
225 mtspr(SPRN_PMC2, 0);
226 }
227
228 if ( !strncmp( buffer, "user", 4) )
229 {
230 /* setup mmcr0 and clear the correct pmc */
231 tmp = (mfspr(SPRN_MMCR0) & ~(0x60000000)) | 0x20000000;
232 mtspr(SPRN_MMCR0, tmp);
233 mtspr(SPRN_PMC1, 0);
234 mtspr(SPRN_PMC2, 0);
235 }
236
237 if ( !strncmp( buffer, "kernel", 6) )
238 {
239 /* setup mmcr0 and clear the correct pmc */
240 tmp = (mfspr(SPRN_MMCR0) & ~(0x60000000)) | 0x40000000;
241 mtspr(SPRN_MMCR0, tmp);
242 mtspr(SPRN_PMC1, 0);
243 mtspr(SPRN_PMC2, 0);
244 }
245
246 /* PMC1 values */
247 if ( !strncmp( buffer, "dtlb", 4) )
248 {
249 /* setup mmcr0 and clear the correct pmc */
250 tmp = (mfspr(SPRN_MMCR0) & ~(0x7F << 7)) | MMCR0_PMC1_DTLB;
251 mtspr(SPRN_MMCR0, tmp);
252 mtspr(SPRN_PMC1, 0);
253 }
254
255 if ( !strncmp( buffer, "ic miss", 7) )
256 {
257 /* setup mmcr0 and clear the correct pmc */
258 tmp = (mfspr(SPRN_MMCR0) & ~(0x7F<<7)) | MMCR0_PMC1_ICACHEMISS;
259 mtspr(SPRN_MMCR0, tmp);
260 mtspr(SPRN_PMC1, 0);
261 }
262
263 /* PMC2 values */
264 if ( !strncmp( buffer, "load miss time", 14) )
265 {
266 /* setup mmcr0 and clear the correct pmc */
267 asm volatile(
268 "mfspr %0,%1\n\t" /* get current mccr0 */
269 "rlwinm %0,%0,0,0,31-6\n\t" /* clear bits [26-31] */
270 "ori %0,%0,%2 \n\t" /* or in mmcr0 settings */
271 "mtspr %1,%0 \n\t" /* set new mccr0 */
272 "mtspr %3,%4 \n\t" /* reset the pmc */
273 : "=r" (tmp)
274 : "i" (SPRN_MMCR0),
275 "i" (MMCR0_PMC2_LOADMISSTIME),
276 "i" (SPRN_PMC2), "r" (0) );
277 }
278
279 if ( !strncmp( buffer, "itlb", 4) )
280 {
281 /* setup mmcr0 and clear the correct pmc */
282 asm volatile(
283 "mfspr %0,%1\n\t" /* get current mccr0 */
284 "rlwinm %0,%0,0,0,31-6\n\t" /* clear bits [26-31] */
285 "ori %0,%0,%2 \n\t" /* or in mmcr0 settings */
286 "mtspr %1,%0 \n\t" /* set new mccr0 */
287 "mtspr %3,%4 \n\t" /* reset the pmc */
288 : "=r" (tmp)
289 : "i" (SPRN_MMCR0), "i" (MMCR0_PMC2_ITLB),
290 "i" (SPRN_PMC2), "r" (0) );
291 }
292
293 if ( !strncmp( buffer, "dc miss", 7) )
294 {
295 /* setup mmcr0 and clear the correct pmc */
296 asm volatile(
297 "mfspr %0,%1\n\t" /* get current mccr0 */
298 "rlwinm %0,%0,0,0,31-6\n\t" /* clear bits [26-31] */
299 "ori %0,%0,%2 \n\t" /* or in mmcr0 settings */
300 "mtspr %1,%0 \n\t" /* set new mccr0 */
301 "mtspr %3,%4 \n\t" /* reset the pmc */
302 : "=r" (tmp)
303 : "i" (SPRN_MMCR0), "i" (MMCR0_PMC2_DCACHEMISS),
304 "i" (SPRN_PMC2), "r" (0) );
305 }
306
307 return count;
308 #else /* CONFIG_PPC_STD_MMU */
309 return 0;
310 #endif /* CONFIG_PPC_STD_MMU */
311 }
312
313 int proc_dol2crvec(ctl_table *table, int write, struct file *filp,
314 void __user *buffer_arg, size_t *lenp, loff_t *ppos)
315 {
316 int vleft, first=1, len, left, val;
317 char __user *buffer = (char __user *) buffer_arg;
318 #define TMPBUFLEN 256
319 char buf[TMPBUFLEN], *p;
320 static const char *sizestrings[4] = {
321 "2MB", "256KB", "512KB", "1MB"
322 };
323 static const char *clockstrings[8] = {
324 "clock disabled", "+1 clock", "+1.5 clock", "reserved(3)",
325 "+2 clock", "+2.5 clock", "+3 clock", "reserved(7)"
326 };
327 static const char *typestrings[4] = {
328 "flow-through burst SRAM", "reserved SRAM",
329 "pipelined burst SRAM", "pipelined late-write SRAM"
330 };
331 static const char *holdstrings[4] = {
332 "0.5", "1.0", "(reserved2)", "(reserved3)"
333 };
334
335 if (!cpu_has_feature(CPU_FTR_L2CR))
336 return -EFAULT;
337
338 if ( /*!table->maxlen ||*/ (*ppos && !write)) {
339 *lenp = 0;
340 return 0;
341 }
342
343 vleft = table->maxlen / sizeof(int);
344 left = *lenp;
345
346 for (; left /*&& vleft--*/; first=0) {
347 if (write) {
348 while (left) {
349 char c;
350 if(get_user(c, buffer))
351 return -EFAULT;
352 if (!isspace(c))
353 break;
354 left--;
355 buffer++;
356 }
357 if (!left)
358 break;
359 len = left;
360 if (len > TMPBUFLEN-1)
361 len = TMPBUFLEN-1;
362 if(copy_from_user(buf, buffer, len))
363 return -EFAULT;
364 buf[len] = 0;
365 p = buf;
366 if (*p < '0' || *p > '9')
367 break;
368 val = simple_strtoul(p, &p, 0);
369 len = p-buf;
370 if ((len < left) && *p && !isspace(*p))
371 break;
372 buffer += len;
373 left -= len;
374 _set_L2CR(val);
375 } else {
376 p = buf;
377 if (!first)
378 *p++ = '\t';
379 val = _get_L2CR();
380 p += sprintf(p, "0x%08x: ", val);
381 p += sprintf(p, " %s", (val >> 31) & 1 ? "enabled" :
382 "disabled");
383 p += sprintf(p, ", %sparity", (val>>30)&1 ? "" : "no ");
384 p += sprintf(p, ", %s", sizestrings[(val >> 28) & 3]);
385 p += sprintf(p, ", %s", clockstrings[(val >> 25) & 7]);
386 p += sprintf(p, ", %s", typestrings[(val >> 23) & 2]);
387 p += sprintf(p, "%s", (val>>22)&1 ? ", data only" : "");
388 p += sprintf(p, "%s", (val>>20)&1 ? ", ZZ enabled": "");
389 p += sprintf(p, ", %s", (val>>19)&1 ? "write-through" :
390 "copy-back");
391 p += sprintf(p, "%s", (val>>18)&1 ? ", testing" : "");
392 p += sprintf(p, ", %sns hold",holdstrings[(val>>16)&3]);
393 p += sprintf(p, "%s", (val>>15)&1 ? ", DLL slow" : "");
394 p += sprintf(p, "%s", (val>>14)&1 ? ", diff clock" :"");
395 p += sprintf(p, "%s", (val>>13)&1 ? ", DLL bypass" :"");
396
397 p += sprintf(p,"\n");
398
399 len = strlen(buf);
400 if (len > left)
401 len = left;
402 if (copy_to_user(buffer, buf, len))
403 return -EFAULT;
404 left -= len;
405 buffer += len;
406 break;
407 }
408 }
409
410 if (!write && !first && left) {
411 if(put_user('\n', (char __user *) buffer))
412 return -EFAULT;
413 left--, buffer++;
414 }
415 if (write) {
416 char __user *s = (char __user *) buffer;
417 while (left) {
418 char c;
419 if(get_user(c, s++))
420 return -EFAULT;
421 if (!isspace(c))
422 break;
423 left--;
424 }
425 }
426 if (write && first)
427 return -EINVAL;
428 *lenp -= left;
429 *ppos += *lenp;
430 return 0;
431 }
432
433 #ifdef CONFIG_SYSCTL
434 /*
435 * Register our sysctl.
436 */
437 static ctl_table htab_ctl_table[]={
438 {
439 .procname = "l2cr",
440 .mode = 0644,
441 .proc_handler = &proc_dol2crvec,
442 },
443 {}
444 };
445 static ctl_table htab_sysctl_root[] = {
446 {
447 .ctl_name = CTL_KERN,
448 .procname = "kernel",
449 .mode = 0555,
450 .child = htab_ctl_table,
451 },
452 {}
453 };
454
455 static int __init
456 register_ppc_htab_sysctl(void)
457 {
458 register_sysctl_table(htab_sysctl_root);
459
460 return 0;
461 }
462
463 __initcall(register_ppc_htab_sysctl);
464 #endif
WRT350N Kernel Patches