include/asm-sparc64/system.h

   1 #ifndef __SPARC64_SYSTEM_H
   2 #define __SPARC64_SYSTEM_H
   3
   4 #include <asm/ptrace.h>
   5 #include <asm/processor.h>
   6 #include <asm/visasm.h>
   7
   8 #ifndef __ASSEMBLY__
   9
  10 #include <linux/irqflags.h>
  11
  12 /*
  13  * Sparc (general) CPU types
  14  */
  15 enum sparc_cpu {
  16   sun4        = 0x00,
  17   sun4c       = 0x01,
  18   sun4m       = 0x02,
  19   sun4d       = 0x03,
  20   sun4e       = 0x04,
  21   sun4u       = 0x05, /* V8 ploos ploos */
  22   sun_unknown = 0x06,
  23   ap1000      = 0x07, /* almost a sun4m */
  24 };
  25
  26 #define sparc_cpu_model sun4u
  27
  28 /* This cannot ever be a sun4c nor sun4 :) That's just history. */
  29 #define ARCH_SUN4C_SUN4 0
  30 #define ARCH_SUN4 0
  31
  32 /* These are here in an effort to more fully work around Spitfire Errata
  33  * #51.  Essentially, if a memory barrier occurs soon after a mispredicted
  34  * branch, the chip can stop executing instructions until a trap occurs.
  35  * Therefore, if interrupts are disabled, the chip can hang forever.
  36  *
  37  * It used to be believed that the memory barrier had to be right in the
  38  * delay slot, but a case has been traced recently wherein the memory barrier
  39  * was one instruction after the branch delay slot and the chip still hung.
  40  * The offending sequence was the following in sym_wakeup_done() of the
  41  * sym53c8xx_2 driver:
  42  *
  43  *      call    sym_ccb_from_dsa, 0
  44  *       movge  %icc, 0, %l0
  45  *      brz,pn  %o0, .LL1303
  46  *       mov    %o0, %l2
  47  *      membar  #LoadLoad
  48  *
  49  * The branch has to be mispredicted for the bug to occur.  Therefore, we put
  50  * the memory barrier explicitly into a "branch always, predicted taken"
  51  * delay slot to avoid the problem case.
  52  */
  53 #define membar_safe(type) \
  54 do {    __asm__ __volatile__("ba,pt     %%xcc, 1f\n\t" \
  55                              " membar   " type "\n" \
  56                              "1:\n" \
  57                              : : : "memory"); \
  58 } while (0)
  59
  60 #define mb()    \
  61         membar_safe("#LoadLoad | #LoadStore | #StoreStore | #StoreLoad")
  62 #define rmb()   \
  63         membar_safe("#LoadLoad")
  64 #define wmb()   \
  65         membar_safe("#StoreStore")
  66 #define membar_storeload() \
  67         membar_safe("#StoreLoad")
  68 #define membar_storeload_storestore() \
  69         membar_safe("#StoreLoad | #StoreStore")
  70 #define membar_storeload_loadload() \
  71         membar_safe("#StoreLoad | #LoadLoad")
  72 #define membar_storestore_loadstore() \
  73         membar_safe("#StoreStore | #LoadStore")
  74
  75 #endif
  76
  77 #define nop()           __asm__ __volatile__ ("nop")
  78
  79 #define read_barrier_depends()          do { } while(0)
  80 #define set_mb(__var, __value) \
  81         do { __var = __value; membar_storeload_storestore(); } while(0)
  82
  83 #ifdef CONFIG_SMP
  84 #define smp_mb()        mb()
  85 #define smp_rmb()       rmb()
  86 #define smp_wmb()       wmb()
  87 #define smp_read_barrier_depends()      read_barrier_depends()
  88 #else
  89 #define smp_mb()        __asm__ __volatile__("":::"memory")
  90 #define smp_rmb()       __asm__ __volatile__("":::"memory")
  91 #define smp_wmb()       __asm__ __volatile__("":::"memory")
  92 #define smp_read_barrier_depends()      do { } while(0)
  93 #endif
  94
  95 #define flushi(addr)    __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
  96
  97 #define flushw_all()    __asm__ __volatile__("flushw")
  98
  99 /* Performance counter register access. */
 100 #define read_pcr(__p)  __asm__ __volatile__("rd %%pcr, %0" : "=r" (__p))
 101 #define write_pcr(__p) __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (__p))
 102 #define read_pic(__p)  __asm__ __volatile__("rd %%pic, %0" : "=r" (__p))
 103
 104 /* Blackbird errata workaround.  See commentary in
 105  * arch/sparc64/kernel/smp.c:smp_percpu_timer_interrupt()
 106  * for more information.
 107  */
 108 #define reset_pic()                                             \
 109         __asm__ __volatile__("ba,pt     %xcc, 99f\n\t"          \
 110                              ".align    64\n"                   \
 111                           "99:wr        %g0, 0x0, %pic\n\t"     \
 112                              "rd        %pic, %g0")
 113
 114 #ifndef __ASSEMBLY__
 115
 116 extern void sun_do_break(void);
 117 extern int stop_a_enabled;
 118
 119 extern void synchronize_user_stack(void);
 120
 121 extern void __flushw_user(void);
 122 #define flushw_user() __flushw_user()
 123
 124 #define flush_user_windows flushw_user
 125 #define flush_register_windows flushw_all
 126
 127 /* Don't hold the runqueue lock over context switch */
 128 #define __ARCH_WANT_UNLOCKED_CTXSW
 129 #define prepare_arch_switch(next)               \
 130 do {                                            \
 131         flushw_all();                           \
 132 } while (0)
 133
 134         /* See what happens when you design the chip correctly?
 135          *
 136          * We tell gcc we clobber all non-fixed-usage registers except
 137          * for l0/l1.  It will use one for 'next' and the other to hold
 138          * the output value of 'last'.  'next' is not referenced again
 139          * past the invocation of switch_to in the scheduler, so we need
 140          * not preserve it's value.  Hairy, but it lets us remove 2 loads
 141          * and 2 stores in this critical code path.  -DaveM
 142          */
 143 #define switch_to(prev, next, last)                                     \
 144 do {    if (test_thread_flag(TIF_PERFCTR)) {                            \
 145                 unsigned long __tmp;                                    \
 146                 read_pcr(__tmp);                                        \
 147                 current_thread_info()->pcr_reg = __tmp;                 \
 148                 read_pic(__tmp);                                        \
 149                 current_thread_info()->kernel_cntd0 += (unsigned int)(__tmp);\
 150                 current_thread_info()->kernel_cntd1 += ((__tmp) >> 32); \
 151         }                                                               \
 152         flush_tlb_pending();                                            \
 153         save_and_clear_fpu();                                           \
 154         /* If you are tempted to conditionalize the following */        \
 155         /* so that ASI is only written if it changes, think again. */   \
 156         __asm__ __volatile__("wr %%g0, %0, %%asi"                       \
 157         : : "r" (__thread_flag_byte_ptr(task_thread_info(next))[TI_FLAG_BYTE_CURRENT_DS]));\
 158         trap_block[current_thread_info()->cpu].thread =                 \
 159                 task_thread_info(next);                                 \
 160         __asm__ __volatile__(                                           \
 161         "mov    %%g4, %%g7\n\t"                                         \
 162         "stx    %%i6, [%%sp + 2047 + 0x70]\n\t"                         \
 163         "stx    %%i7, [%%sp + 2047 + 0x78]\n\t"                         \
 164         "rdpr   %%wstate, %%o5\n\t"                                     \
 165         "stx    %%o6, [%%g6 + %6]\n\t"                                  \
 166         "stb    %%o5, [%%g6 + %5]\n\t"                                  \
 167         "rdpr   %%cwp, %%o5\n\t"                                        \
 168         "stb    %%o5, [%%g6 + %8]\n\t"                                  \
 169         "mov    %4, %%g6\n\t"                                           \
 170         "ldub   [%4 + %8], %%g1\n\t"                                    \
 171         "wrpr   %%g1, %%cwp\n\t"                                        \
 172         "ldx    [%%g6 + %6], %%o6\n\t"                                  \
 173         "ldub   [%%g6 + %5], %%o5\n\t"                                  \
 174         "ldub   [%%g6 + %7], %%o7\n\t"                                  \
 175         "wrpr   %%o5, 0x0, %%wstate\n\t"                                \
 176         "ldx    [%%sp + 2047 + 0x70], %%i6\n\t"                         \
 177         "ldx    [%%sp + 2047 + 0x78], %%i7\n\t"                         \
 178         "ldx    [%%g6 + %9], %%g4\n\t"                                  \
 179         "brz,pt %%o7, 1f\n\t"                                           \
 180         " mov   %%g7, %0\n\t"                                           \
 181         "sethi  %%hi(ret_from_syscall), %%g1\n\t"                       \
 182         "jmpl   %%g1 + %%lo(ret_from_syscall), %%g0\n\t"                \
 183         " nop\n\t"                                                      \
 184         "1:\n\t"                                                        \
 185         : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \
 186           "=r" (__local_per_cpu_offset)                                 \
 187         : "0" (task_thread_info(next)),                                 \
 188           "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD),            \
 189           "i" (TI_CWP), "i" (TI_TASK)                                   \
 190         : "cc",                                                         \
 191                 "g1", "g2", "g3",                   "g7",               \
 192                 "l1", "l2", "l3", "l4", "l5", "l6", "l7",               \
 193           "i0", "i1", "i2", "i3", "i4", "i5",                           \
 194           "o0", "o1", "o2", "o3", "o4", "o5",       "o7");              \
 195         /* If you fuck with this, update ret_from_syscall code too. */  \
 196         if (test_thread_flag(TIF_PERFCTR)) {                            \
 197                 write_pcr(current_thread_info()->pcr_reg);              \
 198                 reset_pic();                                            \
 199         }                                                               \
 200 } while(0)
 201
 202 static inline unsigned long xchg32(__volatile__ unsigned int *m, unsigned int val)
 203 {
 204         unsigned long tmp1, tmp2;
 205
 206         __asm__ __volatile__(
 207 "       membar          #StoreLoad | #LoadLoad\n"
 208 "       mov             %0, %1\n"
 209 "1:     lduw            [%4], %2\n"
 210 "       cas             [%4], %2, %0\n"
 211 "       cmp             %2, %0\n"
 212 "       bne,a,pn        %%icc, 1b\n"
 213 "        mov            %1, %0\n"
 214 "       membar          #StoreLoad | #StoreStore\n"
 215         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
 216         : "0" (val), "r" (m)
 217         : "cc", "memory");
 218         return val;
 219 }
 220
 221 static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long val)
 222 {
 223         unsigned long tmp1, tmp2;
 224
 225         __asm__ __volatile__(
 226 "       membar          #StoreLoad | #LoadLoad\n"
 227 "       mov             %0, %1\n"
 228 "1:     ldx             [%4], %2\n"
 229 "       casx            [%4], %2, %0\n"
 230 "       cmp             %2, %0\n"
 231 "       bne,a,pn        %%xcc, 1b\n"
 232 "        mov            %1, %0\n"
 233 "       membar          #StoreLoad | #StoreStore\n"
 234         : "=&r" (val), "=&r" (tmp1), "=&r" (tmp2)
 235         : "0" (val), "r" (m)
 236         : "cc", "memory");
 237         return val;
 238 }
 239
 240 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 241
 242 extern void __xchg_called_with_bad_pointer(void);
 243
 244 static inline unsigned long __xchg(unsigned long x, __volatile__ void * ptr,
 245                                        int size)
 246 {
 247         switch (size) {
 248         case 4:
 249                 return xchg32(ptr, x);
 250         case 8:
 251                 return xchg64(ptr, x);
 252         };
 253         __xchg_called_with_bad_pointer();
 254         return x;
 255 }
 256
 257 extern void die_if_kernel(char *str, struct pt_regs *regs) __attribute__ ((noreturn));
 258
 259 /*
 260  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
 261  * store NEW in MEM.  Return the initial value in MEM.  Success is
 262  * indicated by comparing RETURN with OLD.
 263  */
 264
 265 #define __HAVE_ARCH_CMPXCHG 1
 266
 267 static inline unsigned long
 268 __cmpxchg_u32(volatile int *m, int old, int new)
 269 {
 270         __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
 271                              "cas [%2], %3, %0\n\t"
 272                              "membar #StoreLoad | #StoreStore"
 273                              : "=&r" (new)
 274                              : "0" (new), "r" (m), "r" (old)
 275                              : "memory");
 276
 277         return new;
 278 }
 279
 280 static inline unsigned long
 281 __cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
 282 {
 283         __asm__ __volatile__("membar #StoreLoad | #LoadLoad\n"
 284                              "casx [%2], %3, %0\n\t"
 285                              "membar #StoreLoad | #StoreStore"
 286                              : "=&r" (new)
 287                              : "0" (new), "r" (m), "r" (old)
 288                              : "memory");
 289
 290         return new;
 291 }
 292
 293 /* This function doesn't exist, so you'll get a linker error
 294    if something tries to do an invalid cmpxchg().  */
 295 extern void __cmpxchg_called_with_bad_pointer(void);
 296
 297 static inline unsigned long
 298 __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
 299 {
 300         switch (size) {
 301                 case 4:
 302                         return __cmpxchg_u32(ptr, old, new);
 303                 case 8:
 304                         return __cmpxchg_u64(ptr, old, new);
 305         }
 306         __cmpxchg_called_with_bad_pointer();
 307         return old;
 308 }
 309
 310 #define cmpxchg(ptr,o,n)                                                 \
 311   ({                                                                     \
 312      __typeof__(*(ptr)) _o_ = (o);                                       \
 313      __typeof__(*(ptr)) _n_ = (n);                                       \
 314      (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
 315                                     (unsigned long)_n_, sizeof(*(ptr))); \
 316   })
 317
 318 #endif /* !(__ASSEMBLY__) */
 319
 320 #define arch_align_stack(x) (x)
 321
 322 #endif /* !(__SPARC64_SYSTEM_H) */