4 #include <asm/pgtable.h>
5 #include <asm/cacheflush.h>
8 * Functions to keep the agpgart mappings coherent with the MMU. The
9 * GART gives the CPU a physical alias of pages in memory. The alias
10 * region is mapped uncacheable. Make sure there are no conflicting
11 * mappings with different cachability attributes for the same
12 * page. This avoids data corruption on some CPUs.
15 #define map_page_into_agp(page) set_pages_uc(page, 1)
16 #define unmap_page_from_agp(page) set_pages_wb(page, 1)
17 #define flush_agp_mappings() do { } while (0)
20 * Could use CLFLUSH here if the cpu supports it. But then it would
21 * need to be called for each cacheline of the whole page so it may
22 * not be worth it. Would need a page for it.
24 #define flush_agp_cache() wbinvd()
26 /* Convert a physical address to an address suitable for the GART. */
27 #define phys_to_gart(x) (x)
28 #define gart_to_phys(x) (x)
30 /* GATT allocation. Returns/accepts GATT kernel virtual address. */
31 #define alloc_gatt_pages(order) \
32 ((char *)__get_free_pages(GFP_KERNEL, (order)))
33 #define free_gatt_pages(table, order) \
34 free_pages((unsigned long)(table), (order))