drivers/video/geode/video_cs5530.c

   1 /*
   2  * drivers/video/geode/video_cs5530.c
   3  *   -- CS5530 video device
   4  *
   5  * Copyright (C) 2005 Arcom Control Systems Ltd.
   6  *
   7  * Based on AMD's original 2.4 driver:
   8  *   Copyright (C) 2004 Advanced Micro Devices, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15 #include <linux/fb.h>
  16 #include <linux/delay.h>
  17 #include <asm/io.h>
  18 #include <asm/delay.h>
  19
  20 #include "geodefb.h"
  21 #include "video_cs5530.h"
  22
  23 /*
  24  * CS5530 PLL table. This maps pixclocks to the appropriate PLL register
  25  * value.
  26  */
  27 struct cs5530_pll_entry {
  28         long pixclock; /* ps */
  29         u32 pll_value;
  30 };
  31
  32 static const struct cs5530_pll_entry cs5530_pll_table[] = {
  33         { 39721, 0x31C45801, }, /*  25.1750 MHz */
  34         { 35308, 0x20E36802, }, /*  28.3220 */
  35         { 31746, 0x33915801, }, /*  31.5000 */
  36         { 27777, 0x31EC4801, }, /*  36.0000 */
  37         { 26666, 0x21E22801, }, /*  37.5000 */
  38         { 25000, 0x33088801, }, /*  40.0000 */
  39         { 22271, 0x33E22801, }, /*  44.9000 */
  40         { 20202, 0x336C4801, }, /*  49.5000 */
  41         { 20000, 0x23088801, }, /*  50.0000 */
  42         { 19860, 0x23088801, }, /*  50.3500 */
  43         { 18518, 0x3708A801, }, /*  54.0000 */
  44         { 17777, 0x23E36802, }, /*  56.2500 */
  45         { 17733, 0x23E36802, }, /*  56.3916 */
  46         { 17653, 0x23E36802, }, /*  56.6444 */
  47         { 16949, 0x37C45801, }, /*  59.0000 */
  48         { 15873, 0x23EC4801, }, /*  63.0000 */
  49         { 15384, 0x37911801, }, /*  65.0000 */
  50         { 14814, 0x37963803, }, /*  67.5000 */
  51         { 14124, 0x37058803, }, /*  70.8000 */
  52         { 13888, 0x3710C805, }, /*  72.0000 */
  53         { 13333, 0x37E22801, }, /*  75.0000 */
  54         { 12698, 0x27915801, }, /*  78.7500 */
  55         { 12500, 0x37D8D802, }, /*  80.0000 */
  56         { 11135, 0x27588802, }, /*  89.8000 */
  57         { 10582, 0x27EC4802, }, /*  94.5000 */
  58         { 10101, 0x27AC6803, }, /*  99.0000 */
  59         { 10000, 0x27088801, }, /* 100.0000 */
  60         {  9259, 0x2710C805, }, /* 108.0000 */
  61         {  8888, 0x27E36802, }, /* 112.5000 */
  62         {  7692, 0x27C58803, }, /* 130.0000 */
  63         {  7407, 0x27316803, }, /* 135.0000 */
  64         {  6349, 0x2F915801, }, /* 157.5000 */
  65         {  6172, 0x2F08A801, }, /* 162.0000 */
  66         {  5714, 0x2FB11802, }, /* 175.0000 */
  67         {  5291, 0x2FEC4802, }, /* 189.0000 */
  68         {  4950, 0x2F963803, }, /* 202.0000 */
  69         {  4310, 0x2FB1B802, }, /* 232.0000 */
  70 };
  71
  72 static void cs5530_set_dclk_frequency(struct fb_info *info)
  73 {
  74         struct geodefb_par *par = info->par;
  75         int i;
  76         u32 value;
  77         long min, diff;
  78
  79         /* Search the table for the closest pixclock. */
  80         value = cs5530_pll_table[0].pll_value;
  81         min = cs5530_pll_table[0].pixclock - info->var.pixclock;
  82         if (min < 0) min = -min;
  83         for (i = 1; i < ARRAY_SIZE(cs5530_pll_table); i++) {
  84                 diff = cs5530_pll_table[i].pixclock - info->var.pixclock;
  85                 if (diff < 0L) diff = -diff;
  86                 if (diff < min) {
  87                         min = diff;
  88                         value = cs5530_pll_table[i].pll_value;
  89                 }
  90         }
  91
  92         writel(value, par->vid_regs + CS5530_DOT_CLK_CONFIG);
  93         writel(value | 0x80000100, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* set reset and bypass */
  94         udelay(500); /* wait for PLL to settle */
  95         writel(value & 0x7FFFFFFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear reset */
  96         writel(value & 0x7FFFFEFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear bypass */
  97 }
  98
  99 static void cs5530_configure_display(struct fb_info *info)
 100 {
 101         struct geodefb_par *par = info->par;
 102         u32 dcfg;
 103
 104         dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG);
 105
 106         /* Clear bits from existing mode. */
 107         dcfg &= ~(CS5530_DCFG_CRT_SYNC_SKW_MASK | CS5530_DCFG_PWR_SEQ_DLY_MASK
 108                   | CS5530_DCFG_CRT_HSYNC_POL   | CS5530_DCFG_CRT_VSYNC_POL
 109                   | CS5530_DCFG_FP_PWR_EN       | CS5530_DCFG_FP_DATA_EN
 110                   | CS5530_DCFG_DAC_PWR_EN      | CS5530_DCFG_VSYNC_EN
 111                   | CS5530_DCFG_HSYNC_EN);
 112
 113         /* Set default sync skew and power sequence delays.  */
 114         dcfg |= (CS5530_DCFG_CRT_SYNC_SKW_INIT | CS5530_DCFG_PWR_SEQ_DLY_INIT
 115                  | CS5530_DCFG_GV_PAL_BYP);
 116
 117         /* Enable DACs, hsync and vsync for CRTs */
 118         if (par->enable_crt) {
 119                 dcfg |= CS5530_DCFG_DAC_PWR_EN;
 120                 dcfg |= CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN;
 121         }
 122         /* Enable panel power and data if using a flat panel. */
 123         if (par->panel_x > 0) {
 124                 dcfg |= CS5530_DCFG_FP_PWR_EN;
 125                 dcfg |= CS5530_DCFG_FP_DATA_EN;
 126         }
 127
 128         /* Sync polarities. */
 129         if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 130                 dcfg |= CS5530_DCFG_CRT_HSYNC_POL;
 131         if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 132                 dcfg |= CS5530_DCFG_CRT_VSYNC_POL;
 133
 134         writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG);
 135 }
 136
 137 static int cs5530_blank_display(struct fb_info *info, int blank_mode)
 138 {
 139         struct geodefb_par *par = info->par;
 140         u32 dcfg;
 141         int blank, hsync, vsync;
 142
 143         switch (blank_mode) {
 144         case FB_BLANK_UNBLANK:
 145                 blank = 0; hsync = 1; vsync = 1;
 146                 break;
 147         case FB_BLANK_NORMAL:
 148                 blank = 1; hsync = 1; vsync = 1;
 149                 break;
 150         case FB_BLANK_VSYNC_SUSPEND:
 151                 blank = 1; hsync = 1; vsync = 0;
 152                 break;
 153         case FB_BLANK_HSYNC_SUSPEND:
 154                 blank = 1; hsync = 0; vsync = 1;
 155                 break;
 156         case FB_BLANK_POWERDOWN:
 157                 blank = 1; hsync = 0; vsync = 0;
 158                 break;
 159         default:
 160                 return -EINVAL;
 161         }
 162
 163         dcfg = readl(par->vid_regs + CS5530_DISPLAY_CONFIG);
 164
 165         dcfg &= ~(CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN
 166                   | CS5530_DCFG_HSYNC_EN | CS5530_DCFG_VSYNC_EN
 167                   | CS5530_DCFG_FP_DATA_EN | CS5530_DCFG_FP_PWR_EN);
 168
 169         if (par->enable_crt) {
 170                 if (!blank)
 171                         dcfg |= CS5530_DCFG_DAC_BL_EN | CS5530_DCFG_DAC_PWR_EN;
 172                 if (hsync)
 173                         dcfg |= CS5530_DCFG_HSYNC_EN;
 174                 if (vsync)
 175                         dcfg |= CS5530_DCFG_VSYNC_EN;
 176         }
 177         if (par->panel_x > 0) {
 178                 if (!blank)
 179                         dcfg |= CS5530_DCFG_FP_DATA_EN;
 180                 if (hsync && vsync)
 181                         dcfg |= CS5530_DCFG_FP_PWR_EN;
 182         }
 183
 184         writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG);
 185
 186         return 0;
 187 }
 188
 189 struct geode_vid_ops cs5530_vid_ops = {
 190         .set_dclk          = cs5530_set_dclk_frequency,
 191         .configure_display = cs5530_configure_display,
 192         .blank_display     = cs5530_blank_display,
 193 };