arch/ppc/platforms/85xx/mpc85xx_ads_common.c

   1 /*
   2  * MPC85xx ADS board common routines
   3  *
   4  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
   5  *
   6  * Copyright 2004 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/stddef.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/reboot.h>
  19 #include <linux/pci.h>
  20 #include <linux/kdev_t.h>
  21 #include <linux/major.h>
  22 #include <linux/console.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/serial.h>
  26 #include <linux/module.h>
  27
  28 #include <asm/system.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/page.h>
  31 #include <asm/atomic.h>
  32 #include <asm/time.h>
  33 #include <asm/io.h>
  34 #include <asm/machdep.h>
  35 #include <asm/open_pic.h>
  36 #include <asm/bootinfo.h>
  37 #include <asm/pci-bridge.h>
  38 #include <asm/mpc85xx.h>
  39 #include <asm/irq.h>
  40 #include <asm/immap_85xx.h>
  41 #include <asm/ppc_sys.h>
  42
  43 #include <mm/mmu_decl.h>
  44
  45 #include <syslib/ppc85xx_rio.h>
  46
  47 #include <platforms/85xx/mpc85xx_ads_common.h>
  48
  49 #ifndef CONFIG_PCI
  50 unsigned long isa_io_base = 0;
  51 unsigned long isa_mem_base = 0;
  52 #endif
  53
  54 extern unsigned long total_memory;      /* in mm/init */
  55
  56 unsigned char __res[sizeof (bd_t)];
  57
  58 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
  59 static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
  60         MPC85XX_INTERNAL_IRQ_SENSES,
  61         0x0,                                            /* External  0: */
  62 #if defined(CONFIG_PCI)
  63         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 1: PCI slot 0 */
  64         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 2: PCI slot 1 */
  65         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 3: PCI slot 2 */
  66         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 4: PCI slot 3 */
  67 #else
  68         0x0,                            /* External  1: */
  69         0x0,                            /* External  2: */
  70         0x0,                            /* External  3: */
  71         0x0,                            /* External  4: */
  72 #endif
  73         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 5: PHY */
  74         0x0,                            /* External  6: */
  75         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 7: PHY */
  76         0x0,                            /* External  8: */
  77         0x0,                            /* External  9: */
  78         0x0,                            /* External 10: */
  79         0x0,                            /* External 11: */
  80 };
  81
  82 /* ************************************************************************ */
  83 int
  84 mpc85xx_ads_show_cpuinfo(struct seq_file *m)
  85 {
  86         uint pvid, svid, phid1;
  87         uint memsize = total_memory;
  88         bd_t *binfo = (bd_t *) __res;
  89         unsigned int freq;
  90
  91         /* get the core frequency */
  92         freq = binfo->bi_intfreq;
  93
  94         pvid = mfspr(SPRN_PVR);
  95         svid = mfspr(SPRN_SVR);
  96
  97         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
  98         seq_printf(m, "Machine\t\t: mpc%sads\n", cur_ppc_sys_spec->ppc_sys_name);
  99         seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
 100         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 101         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 102
 103         /* Display cpu Pll setting */
 104         phid1 = mfspr(SPRN_HID1);
 105         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 106
 107         /* Display the amount of memory */
 108         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 109
 110         return 0;
 111 }
 112
 113 void __init
 114 mpc85xx_ads_init_IRQ(void)
 115 {
 116         bd_t *binfo = (bd_t *) __res;
 117         /* Determine the Physical Address of the OpenPIC regs */
 118         phys_addr_t OpenPIC_PAddr =
 119             binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
 120         OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
 121         OpenPIC_InitSenses = mpc85xx_ads_openpic_initsenses;
 122         OpenPIC_NumInitSenses = sizeof (mpc85xx_ads_openpic_initsenses);
 123
 124         /* Skip reserved space and internal sources */
 125         openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
 126         /* Map PIC IRQs 0-11 */
 127         openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
 128
 129         /* we let openpic interrupts starting from an offset, to
 130          * leave space for cascading interrupts underneath.
 131          */
 132         openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
 133
 134         return;
 135 }
 136
 137 #ifdef CONFIG_PCI
 138 /*
 139  * interrupt routing
 140  */
 141
 142 int
 143 mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 144 {
 145         static char pci_irq_table[][4] =
 146             /*
 147              * This is little evil, but works around the fact
 148              * that revA boards have IDSEL starting at 18
 149              * and others boards (older) start at 12
 150              *
 151              *      PCI IDSEL/INTPIN->INTLINE
 152              *       A      B      C      D
 153              */
 154         {
 155                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 2 */
 156                 {PIRQD, PIRQA, PIRQB, PIRQC},
 157                 {PIRQC, PIRQD, PIRQA, PIRQB},
 158                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 5 */
 159                 {0, 0, 0, 0},   /* -- */
 160                 {0, 0, 0, 0},   /* -- */
 161                 {0, 0, 0, 0},   /* -- */
 162                 {0, 0, 0, 0},   /* -- */
 163                 {0, 0, 0, 0},   /* -- */
 164                 {0, 0, 0, 0},   /* -- */
 165                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 12 */
 166                 {PIRQD, PIRQA, PIRQB, PIRQC},
 167                 {PIRQC, PIRQD, PIRQA, PIRQB},
 168                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 15 */
 169                 {0, 0, 0, 0},   /* -- */
 170                 {0, 0, 0, 0},   /* -- */
 171                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 18 */
 172                 {PIRQD, PIRQA, PIRQB, PIRQC},
 173                 {PIRQC, PIRQD, PIRQA, PIRQB},
 174                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 21 */
 175         };
 176
 177         const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
 178         return PCI_IRQ_TABLE_LOOKUP;
 179 }
 180
 181 int
 182 mpc85xx_exclude_device(u_char bus, u_char devfn)
 183 {
 184         if (bus == 0 && PCI_SLOT(devfn) == 0)
 185                 return PCIBIOS_DEVICE_NOT_FOUND;
 186         else
 187                 return PCIBIOS_SUCCESSFUL;
 188 }
 189
 190 #endif /* CONFIG_PCI */
 191
 192 #ifdef CONFIG_RAPIDIO
 193 void platform_rio_init(void)
 194 {
 195         /* 512MB RIO LAW at 0xc0000000 */
 196         mpc85xx_rio_setup(0xc0000000, 0x20000000);
 197 }
 198 #endif /* CONFIG_RAPIDIO */