arch/ppc/platforms/85xx/stx_gp3.c

   1 /*
   2  * STx GP3 board specific routines
   3  *
   4  * Dan Malek <dan@embeddededge.com>
   5  * Copyright 2004 Embedded Edge, LLC
   6  *
   7  * Copied from mpc8560_ads.c
   8  * Copyright 2002, 2003 Motorola Inc.
   9  *
  10  * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
  11  * Copyright 2004-2005 MontaVista Software, Inc.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/reboot.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/major.h>
  27 #include <linux/blkdev.h>
  28 #include <linux/console.h>
  29 #include <linux/delay.h>
  30 #include <linux/root_dev.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/serial.h>
  33 #include <linux/initrd.h>
  34 #include <linux/module.h>
  35 #include <linux/fsl_devices.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/rio.h>
  38
  39 #include <asm/system.h>
  40 #include <asm/pgtable.h>
  41 #include <asm/page.h>
  42 #include <asm/atomic.h>
  43 #include <asm/time.h>
  44 #include <asm/io.h>
  45 #include <asm/machdep.h>
  46 #include <asm/open_pic.h>
  47 #include <asm/bootinfo.h>
  48 #include <asm/pci-bridge.h>
  49 #include <asm/mpc85xx.h>
  50 #include <asm/irq.h>
  51 #include <asm/immap_85xx.h>
  52 #include <asm/cpm2.h>
  53 #include <asm/mpc85xx.h>
  54 #include <asm/ppc_sys.h>
  55
  56 #include <syslib/cpm2_pic.h>
  57 #include <syslib/ppc85xx_common.h>
  58 #include <syslib/ppc85xx_rio.h>
  59
  60
  61 unsigned char __res[sizeof(bd_t)];
  62
  63 #ifndef CONFIG_PCI
  64 unsigned long isa_io_base = 0;
  65 unsigned long isa_mem_base = 0;
  66 unsigned long pci_dram_offset = 0;
  67 #endif
  68
  69 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
  70 static u8 gp3_openpic_initsenses[] __initdata = {
  71         MPC85XX_INTERNAL_IRQ_SENSES,
  72         0x0,                                            /* External  0: */
  73 #if defined(CONFIG_PCI)
  74         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 1: PCI slot 0 */
  75         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 2: PCI slot 1 */
  76         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 3: PCI slot 2 */
  77         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 4: PCI slot 3 */
  78 #else
  79         0x0,                            /* External  1: */
  80         0x0,                            /* External  2: */
  81         0x0,                            /* External  3: */
  82         0x0,                            /* External  4: */
  83 #endif
  84         0x0,                            /* External  5: */
  85         0x0,                            /* External  6: */
  86         0x0,                            /* External  7: */
  87         0x0,                            /* External  8: */
  88         0x0,                            /* External  9: */
  89         0x0,                            /* External 10: */
  90         0x0,                            /* External 11: */
  91 };
  92
  93 /*
  94  * Setup the architecture
  95  */
  96 static void __init
  97 gp3_setup_arch(void)
  98 {
  99         bd_t *binfo = (bd_t *) __res;
 100         unsigned int freq;
 101         struct gianfar_platform_data *pdata;
 102         struct gianfar_mdio_data *mdata;
 103
 104         cpm2_reset();
 105
 106         /* get the core frequency */
 107         freq = binfo->bi_intfreq;
 108
 109         if (ppc_md.progress)
 110                 ppc_md.progress("gp3_setup_arch()", 0);
 111
 112         /* Set loops_per_jiffy to a half-way reasonable value,
 113            for use until calibrate_delay gets called. */
 114         loops_per_jiffy = freq / HZ;
 115
 116 #ifdef CONFIG_PCI
 117         /* setup PCI host bridges */
 118         mpc85xx_setup_hose();
 119 #endif
 120
 121         /* setup the board related info for the MDIO bus */
 122         mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
 123
 124         mdata->irq[2] = MPC85xx_IRQ_EXT5;
 125         mdata->irq[4] = MPC85xx_IRQ_EXT5;
 126         mdata->irq[31] = PHY_POLL;
 127
 128         /* setup the board related information for the enet controllers */
 129         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
 130         if (pdata) {
 131         /*      pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
 132                 pdata->bus_id = 0;
 133                 pdata->phy_id = 2;
 134                 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
 135         }
 136
 137         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
 138         if (pdata) {
 139         /*      pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR; */
 140                 pdata->bus_id = 0;
 141                 pdata->phy_id = 4;
 142                 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
 143         }
 144
 145 #ifdef CONFIG_BLK_DEV_INITRD
 146         if (initrd_start)
 147                 ROOT_DEV = Root_RAM0;
 148         else
 149 #endif
 150 #ifdef  CONFIG_ROOT_NFS
 151                 ROOT_DEV = Root_NFS;
 152 #else
 153                 ROOT_DEV = Root_HDA1;
 154 #endif
 155
 156         printk ("bi_immr_base = %8.8lx\n", binfo->bi_immr_base);
 157 }
 158
 159 static irqreturn_t cpm2_cascade(int irq, void *dev_id)
 160 {
 161         while ((irq = cpm2_get_irq()) >= 0)
 162                 __do_IRQ(irq);
 163
 164         return IRQ_HANDLED;
 165 }
 166
 167 static struct irqaction cpm2_irqaction = {
 168         .handler        = cpm2_cascade,
 169         .flags          = IRQF_DISABLED,
 170         .mask           = CPU_MASK_NONE,
 171         .name           = "cpm2_cascade",
 172 };
 173
 174 static void __init
 175 gp3_init_IRQ(void)
 176 {
 177         bd_t *binfo = (bd_t *) __res;
 178
 179         /*
 180          * Setup OpenPIC
 181          */
 182
 183         /* Determine the Physical Address of the OpenPIC regs */
 184         phys_addr_t OpenPIC_PAddr =
 185             binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
 186         OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
 187         OpenPIC_InitSenses = gp3_openpic_initsenses;
 188         OpenPIC_NumInitSenses = sizeof (gp3_openpic_initsenses);
 189
 190         /* Skip reserved space and internal sources */
 191         openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
 192
 193         /* Map PIC IRQs 0-11 */
 194         openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
 195
 196         /*
 197          * Let openpic interrupts starting from an offset, to
 198          * leave space for cascading interrupts underneath.
 199          */
 200         openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
 201
 202         /* Setup CPM2 PIC */
 203         cpm2_init_IRQ();
 204
 205         setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
 206
 207         return;
 208 }
 209
 210 static int
 211 gp3_show_cpuinfo(struct seq_file *m)
 212 {
 213         uint pvid, svid, phid1;
 214         bd_t *binfo = (bd_t *) __res;
 215         uint    memsize;
 216         unsigned int freq;
 217         extern unsigned long total_memory;      /* in mm/init */
 218
 219         /* get the core frequency */
 220         freq = binfo->bi_intfreq;
 221
 222         pvid = mfspr(SPRN_PVR);
 223         svid = mfspr(SPRN_SVR);
 224
 225         memsize = total_memory;
 226
 227         seq_printf(m, "Vendor\t\t: RPC Electronics STx \n");
 228         seq_printf(m, "Machine\t\t: GP3 - MPC%s\n", cur_ppc_sys_spec->ppc_sys_name);
 229         seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
 230                    freq % 1000000);
 231         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 232         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 233
 234         /* Display cpu Pll setting */
 235         phid1 = mfspr(SPRN_HID1);
 236         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 237
 238         /* Display the amount of memory */
 239         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 240
 241         return 0;
 242 }
 243
 244 #ifdef CONFIG_PCI
 245 int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel,
 246                     unsigned char pin)
 247 {
 248         static char pci_irq_table[][4] =
 249             /*
 250              *      PCI IDSEL/INTPIN->INTLINE
 251              *        A      B      C      D
 252              */
 253         {
 254                 {PIRQA, PIRQB, PIRQC, PIRQD},
 255                 {PIRQD, PIRQA, PIRQB, PIRQC},
 256                 {PIRQC, PIRQD, PIRQA, PIRQB},
 257                 {PIRQB, PIRQC, PIRQD, PIRQA},
 258         };
 259
 260         const long min_idsel = 12, max_idsel = 15, irqs_per_slot = 4;
 261         return PCI_IRQ_TABLE_LOOKUP;
 262 }
 263
 264 int mpc85xx_exclude_device(u_char bus, u_char devfn)
 265 {
 266         if (bus == 0 && PCI_SLOT(devfn) == 0)
 267                 return PCIBIOS_DEVICE_NOT_FOUND;
 268         else
 269                 return PCIBIOS_SUCCESSFUL;
 270 }
 271 #endif /* CONFIG_PCI */
 272
 273 #ifdef CONFIG_RAPIDIO
 274 void
 275 platform_rio_init(void)
 276 {
 277         /*
 278          * The STx firmware configures the RapidIO Local Access Window
 279          * at 0xc0000000 with a size of 512MB.
 280          */
 281         mpc85xx_rio_setup(0xc0000000, 0x20000000);
 282 }
 283 #endif /* CONFIG_RAPIDIO */
 284
 285 void __init
 286 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 287               unsigned long r6, unsigned long r7)
 288 {
 289         /* parse_bootinfo must always be called first */
 290         parse_bootinfo(find_bootinfo());
 291
 292         /*
 293          * If we were passed in a board information, copy it into the
 294          * residual data area.
 295          */
 296         if (r3) {
 297                 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
 298                        sizeof (bd_t));
 299
 300         }
 301 #if defined(CONFIG_BLK_DEV_INITRD)
 302         /*
 303          * If the init RAM disk has been configured in, and there's a valid
 304          * starting address for it, set it up.
 305          */
 306         if (r4) {
 307                 initrd_start = r4 + KERNELBASE;
 308                 initrd_end = r5 + KERNELBASE;
 309         }
 310 #endif                          /* CONFIG_BLK_DEV_INITRD */
 311
 312         /* Copy the kernel command line arguments to a safe place. */
 313
 314         if (r6) {
 315                 *(char *) (r7 + KERNELBASE) = 0;
 316                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 317         }
 318
 319         identify_ppc_sys_by_id(mfspr(SPRN_SVR));
 320
 321         /* setup the PowerPC module struct */
 322         ppc_md.setup_arch = gp3_setup_arch;
 323         ppc_md.show_cpuinfo = gp3_show_cpuinfo;
 324
 325         ppc_md.init_IRQ = gp3_init_IRQ;
 326         ppc_md.get_irq = openpic_get_irq;
 327
 328         ppc_md.restart = mpc85xx_restart;
 329         ppc_md.power_off = mpc85xx_power_off;
 330         ppc_md.halt = mpc85xx_halt;
 331
 332         ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
 333
 334         ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
 335
 336         if (ppc_md.progress)
 337                 ppc_md.progress("platform_init(): exit", 0);
 338
 339         return;
 340 }