arch/ppc/platforms/85xx/tqm85xx.c

   1 /*
   2  * TQM85xx (40/41/55/60) board specific routines
   3  *
   4  * Copyright (c) 2005 DENX Software Engineering
   5  * Stefan Roese <sr@denx.de>
   6  *
   7  * Based on original work by
   8  *      Kumar Gala <galak@kernel.crashing.org>
   9  *      Copyright 2004 Freescale Semiconductor Inc.
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16
  17 #include <linux/stddef.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/reboot.h>
  22 #include <linux/pci.h>
  23 #include <linux/kdev_t.h>
  24 #include <linux/major.h>
  25 #include <linux/console.h>
  26 #include <linux/delay.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/root_dev.h>
  29 #include <linux/serial.h>
  30 #include <linux/tty.h>  /* for linux/serial_core.h */
  31 #include <linux/serial_core.h>
  32 #include <linux/initrd.h>
  33 #include <linux/module.h>
  34 #include <linux/fsl_devices.h>
  35
  36 #include <asm/system.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/page.h>
  39 #include <asm/atomic.h>
  40 #include <asm/time.h>
  41 #include <asm/io.h>
  42 #include <asm/machdep.h>
  43 #include <asm/open_pic.h>
  44 #include <asm/bootinfo.h>
  45 #include <asm/pci-bridge.h>
  46 #include <asm/mpc85xx.h>
  47 #include <asm/irq.h>
  48 #include <asm/immap_85xx.h>
  49 #include <asm/kgdb.h>
  50 #include <asm/ppc_sys.h>
  51 #include <asm/cpm2.h>
  52 #include <mm/mmu_decl.h>
  53
  54 #include <syslib/ppc85xx_setup.h>
  55 #include <syslib/cpm2_pic.h>
  56 #include <syslib/ppc85xx_common.h>
  57 #include <syslib/ppc85xx_rio.h>
  58
  59 #ifndef CONFIG_PCI
  60 unsigned long isa_io_base = 0;
  61 unsigned long isa_mem_base = 0;
  62 #endif
  63
  64
  65 extern unsigned long total_memory;      /* in mm/init */
  66
  67 unsigned char __res[sizeof (bd_t)];
  68
  69 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
  70 static u_char tqm85xx_openpic_initsenses[] __initdata = {
  71         MPC85XX_INTERNAL_IRQ_SENSES,
  72         0x0,                                            /* External  0: */
  73         0x0,                                            /* External  1: */
  74 #if defined(CONFIG_PCI)
  75         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 2: PCI INTA */
  76         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 3: PCI INTB */
  77 #else
  78         0x0,                            /* External  2: */
  79         0x0,                            /* External  3: */
  80 #endif
  81         0x0,                            /* External  4: */
  82         0x0,                            /* External  5: */
  83         0x0,                            /* External  6: */
  84         0x0,                            /* External  7: */
  85         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 8: PHY */
  86         0x0,                            /* External  9: */
  87         0x0,                            /* External 10: */
  88         0x0,                            /* External 11: */
  89 };
  90
  91 /* ************************************************************************
  92  *
  93  * Setup the architecture
  94  *
  95  */
  96 static void __init
  97 tqm85xx_setup_arch(void)
  98 {
  99         bd_t *binfo = (bd_t *) __res;
 100         unsigned int freq;
 101         struct gianfar_platform_data *pdata;
 102         struct gianfar_mdio_data *mdata;
 103
 104 #ifdef CONFIG_MPC8560
 105         cpm2_reset();
 106 #endif
 107
 108         /* get the core frequency */
 109         freq = binfo->bi_intfreq;
 110
 111         if (ppc_md.progress)
 112                 ppc_md.progress("tqm85xx_setup_arch()", 0);
 113
 114         /* Set loops_per_jiffy to a half-way reasonable value,
 115            for use until calibrate_delay gets called. */
 116         loops_per_jiffy = freq / HZ;
 117
 118 #ifdef CONFIG_PCI
 119         /* setup PCI host bridges */
 120         mpc85xx_setup_hose();
 121 #endif
 122
 123 #ifndef CONFIG_MPC8560
 124 #if defined(CONFIG_SERIAL_8250)
 125         mpc85xx_early_serial_map();
 126 #endif
 127
 128 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 129         /* Invalidate the entry we stole earlier the serial ports
 130          * should be properly mapped */
 131         invalidate_tlbcam_entry(num_tlbcam_entries - 1);
 132 #endif
 133 #endif /* CONFIG_MPC8560 */
 134
 135         /* setup the board related info for the MDIO bus */
 136         mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
 137
 138         mdata->irq[0] = MPC85xx_IRQ_EXT8;
 139         mdata->irq[1] = MPC85xx_IRQ_EXT8;
 140         mdata->irq[2] = PHY_POLL;
 141         mdata->irq[3] = MPC85xx_IRQ_EXT8;
 142         mdata->irq[31] = PHY_POLL;
 143
 144         /* setup the board related information for the enet controllers */
 145         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
 146         if (pdata) {
 147                 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
 148                 pdata->bus_id = 0;
 149                 pdata->phy_id = 2;
 150                 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
 151         }
 152
 153         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
 154         if (pdata) {
 155                 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
 156                 pdata->bus_id = 0;
 157                 pdata->phy_id = 1;
 158                 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
 159         }
 160
 161 #ifdef CONFIG_MPC8540
 162         pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_FEC);
 163         if (pdata) {
 164                 pdata->board_flags = 0;
 165                 pdata->bus_id = 0;
 166                 pdata->phy_id = 3;
 167                 memcpy(pdata->mac_addr, binfo->bi_enet2addr, 6);
 168         }
 169 #endif
 170
 171 #ifdef CONFIG_BLK_DEV_INITRD
 172         if (initrd_start)
 173                 ROOT_DEV = Root_RAM0;
 174         else
 175 #endif
 176 #ifdef  CONFIG_ROOT_NFS
 177                 ROOT_DEV = Root_NFS;
 178 #else
 179         ROOT_DEV = Root_HDA1;
 180 #endif
 181 }
 182
 183 #ifdef CONFIG_MPC8560
 184 static irqreturn_t cpm2_cascade(int irq, void *dev_id)
 185 {
 186         while ((irq = cpm2_get_irq()) >= 0)
 187                 __do_IRQ(irq);
 188         return IRQ_HANDLED;
 189 }
 190
 191 static struct irqaction cpm2_irqaction = {
 192         .handler = cpm2_cascade,
 193         .flags = IRQF_DISABLED,
 194         .mask = CPU_MASK_NONE,
 195         .name = "cpm2_cascade",
 196 };
 197 #endif /* CONFIG_MPC8560 */
 198
 199 void __init
 200 tqm85xx_init_IRQ(void)
 201 {
 202         bd_t *binfo = (bd_t *) __res;
 203
 204         /* Determine the Physical Address of the OpenPIC regs */
 205         phys_addr_t OpenPIC_PAddr =
 206                 binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
 207         OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
 208         OpenPIC_InitSenses = tqm85xx_openpic_initsenses;
 209         OpenPIC_NumInitSenses = sizeof (tqm85xx_openpic_initsenses);
 210
 211         /* Skip reserved space and internal sources */
 212         openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
 213
 214         /* Map PIC IRQs 0-11 */
 215         openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
 216
 217         /* we let openpic interrupts starting from an offset, to
 218          * leave space for cascading interrupts underneath.
 219          */
 220         openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
 221
 222 #ifdef CONFIG_MPC8560
 223         /* Setup CPM2 PIC */
 224         cpm2_init_IRQ();
 225
 226         setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
 227 #endif /* CONFIG_MPC8560 */
 228
 229         return;
 230 }
 231
 232 int tqm85xx_show_cpuinfo(struct seq_file *m)
 233 {
 234         uint pvid, svid, phid1;
 235         uint memsize = total_memory;
 236         bd_t *binfo = (bd_t *) __res;
 237         unsigned int freq;
 238
 239         /* get the core frequency */
 240         freq = binfo->bi_intfreq;
 241
 242         pvid = mfspr(SPRN_PVR);
 243         svid = mfspr(SPRN_SVR);
 244
 245         seq_printf(m, "Vendor\t\t: TQ Components\n");
 246         seq_printf(m, "Machine\t\t: TQM%s\n", cur_ppc_sys_spec->ppc_sys_name);
 247         seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
 248         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 249         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 250
 251         /* Display cpu Pll setting */
 252         phid1 = mfspr(SPRN_HID1);
 253         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 254
 255         /* Display the amount of memory */
 256         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 257
 258         return 0;
 259 }
 260
 261 #ifdef CONFIG_PCI
 262 /*
 263  * interrupt routing
 264  */
 265 int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 266 {
 267         static char pci_irq_table[][4] =
 268                 /*
 269                  *      PCI IDSEL/INTPIN->INTLINE
 270                  *       A      B      C      D
 271                  */
 272                 {
 273                         {PIRQA, PIRQB, 0, 0},
 274                 };
 275
 276         const long min_idsel = 0x1c, max_idsel = 0x1c, irqs_per_slot = 4;
 277         return PCI_IRQ_TABLE_LOOKUP;
 278 }
 279
 280 int mpc85xx_exclude_device(u_char bus, u_char devfn)
 281 {
 282         if (bus == 0 && PCI_SLOT(devfn) == 0)
 283                 return PCIBIOS_DEVICE_NOT_FOUND;
 284         else
 285                 return PCIBIOS_SUCCESSFUL;
 286 }
 287
 288 #endif /* CONFIG_PCI */
 289
 290 #ifdef CONFIG_RAPIDIO
 291 void platform_rio_init(void)
 292 {
 293         /* 512MB RIO LAW at 0xc0000000 */
 294         mpc85xx_rio_setup(0xc0000000, 0x20000000);
 295 }
 296 #endif /* CONFIG_RAPIDIO */
 297
 298 /* ************************************************************************ */
 299 void __init
 300 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 301               unsigned long r6, unsigned long r7)
 302 {
 303         /* parse_bootinfo must always be called first */
 304         parse_bootinfo(find_bootinfo());
 305
 306         /*
 307          * If we were passed in a board information, copy it into the
 308          * residual data area.
 309          */
 310         if (r3) {
 311                 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
 312                        sizeof (bd_t));
 313         }
 314
 315 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && !defined(CONFIG_MPC8560)
 316         {
 317                 bd_t *binfo = (bd_t *) __res;
 318                 struct uart_port p;
 319
 320                 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
 321                 settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
 322                           binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
 323
 324                 memset(&p, 0, sizeof (p));
 325                 p.iotype = UPIO_MEM;
 326                 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
 327                 p.uartclk = binfo->bi_busfreq;
 328
 329                 gen550_init(0, &p);
 330
 331                 memset(&p, 0, sizeof (p));
 332                 p.iotype = UPIO_MEM;
 333                 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
 334                 p.uartclk = binfo->bi_busfreq;
 335
 336                 gen550_init(1, &p);
 337         }
 338 #endif
 339
 340 #if defined(CONFIG_BLK_DEV_INITRD)
 341         /*
 342          * If the init RAM disk has been configured in, and there's a valid
 343          * starting address for it, set it up.
 344          */
 345         if (r4) {
 346                 initrd_start = r4 + KERNELBASE;
 347                 initrd_end = r5 + KERNELBASE;
 348         }
 349 #endif                          /* CONFIG_BLK_DEV_INITRD */
 350
 351         /* Copy the kernel command line arguments to a safe place. */
 352
 353         if (r6) {
 354                 *(char *) (r7 + KERNELBASE) = 0;
 355                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 356         }
 357
 358         identify_ppc_sys_by_id(mfspr(SPRN_SVR));
 359
 360         /* setup the PowerPC module struct */
 361         ppc_md.setup_arch = tqm85xx_setup_arch;
 362         ppc_md.show_cpuinfo = tqm85xx_show_cpuinfo;
 363
 364         ppc_md.init_IRQ = tqm85xx_init_IRQ;
 365         ppc_md.get_irq = openpic_get_irq;
 366
 367         ppc_md.restart = mpc85xx_restart;
 368         ppc_md.power_off = mpc85xx_power_off;
 369         ppc_md.halt = mpc85xx_halt;
 370
 371         ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
 372
 373         ppc_md.time_init = NULL;
 374         ppc_md.set_rtc_time = NULL;
 375         ppc_md.get_rtc_time = NULL;
 376         ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
 377
 378 #ifndef CONFIG_MPC8560
 379 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
 380         ppc_md.progress = gen550_progress;
 381 #endif  /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
 382 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
 383         ppc_md.early_serial_map = mpc85xx_early_serial_map;
 384 #endif  /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
 385 #endif /* CONFIG_MPC8560 */
 386
 387         if (ppc_md.progress)
 388                 ppc_md.progress("tqm85xx_init(): exit", 0);
 389
 390         return;
 391 }