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x86: cpa: move clflush_cache_range()
[wrt350n-kernel.git] / drivers / net / niu.c
blob2fe14b0c5c67956e05f01b69d54ebb7d7a194509
1 /* niu.c: Neptune ethernet driver.
2 *
3 * Copyright (C) 2007 David S. Miller (davem@davemloft.net)
4 */
5
6 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/netdevice.h>
11 #include <linux/ethtool.h>
12 #include <linux/etherdevice.h>
13 #include <linux/platform_device.h>
14 #include <linux/delay.h>
15 #include <linux/bitops.h>
16 #include <linux/mii.h>
17 #include <linux/if_ether.h>
18 #include <linux/if_vlan.h>
19 #include <linux/ip.h>
20 #include <linux/in.h>
21 #include <linux/ipv6.h>
22 #include <linux/log2.h>
23 #include <linux/jiffies.h>
24 #include <linux/crc32.h>
25
26 #include <linux/io.h>
27
28 #ifdef CONFIG_SPARC64
29 #include <linux/of_device.h>
30 #endif
31
32 #include "niu.h"
33
34 #define DRV_MODULE_NAME "niu"
35 #define PFX DRV_MODULE_NAME ": "
36 #define DRV_MODULE_VERSION "0.6"
37 #define DRV_MODULE_RELDATE "January 5, 2008"
38
39 static char version[] __devinitdata =
40 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
41
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION);
46
47 #ifndef DMA_44BIT_MASK
48 #define DMA_44BIT_MASK 0x00000fffffffffffULL
49 #endif
50
51 #ifndef readq
52 static u64 readq(void __iomem *reg)
53 {
54 return (((u64)readl(reg + 0x4UL) << 32) |
55 (u64)readl(reg));
56 }
57
58 static void writeq(u64 val, void __iomem *reg)
59 {
60 writel(val & 0xffffffff, reg);
61 writel(val >> 32, reg + 0x4UL);
62 }
63 #endif
64
65 static struct pci_device_id niu_pci_tbl[] = {
66 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)},
67 {}
68 };
69
70 MODULE_DEVICE_TABLE(pci, niu_pci_tbl);
71
72 #define NIU_TX_TIMEOUT (5 * HZ)
73
74 #define nr64(reg) readq(np->regs + (reg))
75 #define nw64(reg, val) writeq((val), np->regs + (reg))
76
77 #define nr64_mac(reg) readq(np->mac_regs + (reg))
78 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
79
80 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
81 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
82
83 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
84 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
85
86 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
87 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
88
89 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
90
91 static int niu_debug;
92 static int debug = -1;
93 module_param(debug, int, 0);
94 MODULE_PARM_DESC(debug, "NIU debug level");
95
96 #define niudbg(TYPE, f, a...) \
97 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
98 printk(KERN_DEBUG PFX f, ## a); \
99 } while (0)
100
101 #define niuinfo(TYPE, f, a...) \
102 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
103 printk(KERN_INFO PFX f, ## a); \
104 } while (0)
105
106 #define niuwarn(TYPE, f, a...) \
107 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
108 printk(KERN_WARNING PFX f, ## a); \
109 } while (0)
110
111 #define niu_lock_parent(np, flags) \
112 spin_lock_irqsave(&np->parent->lock, flags)
113 #define niu_unlock_parent(np, flags) \
114 spin_unlock_irqrestore(&np->parent->lock, flags)
115
116 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg,
117 u64 bits, int limit, int delay)
118 {
119 while (--limit >= 0) {
120 u64 val = nr64_mac(reg);
121
122 if (!(val & bits))
123 break;
124 udelay(delay);
125 }
126 if (limit < 0)
127 return -ENODEV;
128 return 0;
129 }
130
131 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg,
132 u64 bits, int limit, int delay,
133 const char *reg_name)
134 {
135 int err;
136
137 nw64_mac(reg, bits);
138 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
139 if (err)
140 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
141 "would not clear, val[%llx]\n",
142 np->dev->name, (unsigned long long) bits, reg_name,
143 (unsigned long long) nr64_mac(reg));
144 return err;
145 }
146
147 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
148 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
149 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
150 })
151
152 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg,
153 u64 bits, int limit, int delay)
154 {
155 while (--limit >= 0) {
156 u64 val = nr64_ipp(reg);
157
158 if (!(val & bits))
159 break;
160 udelay(delay);
161 }
162 if (limit < 0)
163 return -ENODEV;
164 return 0;
165 }
166
167 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg,
168 u64 bits, int limit, int delay,
169 const char *reg_name)
170 {
171 int err;
172 u64 val;
173
174 val = nr64_ipp(reg);
175 val |= bits;
176 nw64_ipp(reg, val);
177
178 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
179 if (err)
180 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
181 "would not clear, val[%llx]\n",
182 np->dev->name, (unsigned long long) bits, reg_name,
183 (unsigned long long) nr64_ipp(reg));
184 return err;
185 }
186
187 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
188 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
189 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
190 })
191
192 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg,
193 u64 bits, int limit, int delay)
194 {
195 while (--limit >= 0) {
196 u64 val = nr64(reg);
197
198 if (!(val & bits))
199 break;
200 udelay(delay);
201 }
202 if (limit < 0)
203 return -ENODEV;
204 return 0;
205 }
206
207 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
208 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
209 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
210 })
211
212 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg,
213 u64 bits, int limit, int delay,
214 const char *reg_name)
215 {
216 int err;
217
218 nw64(reg, bits);
219 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
220 if (err)
221 dev_err(np->device, PFX "%s: bits (%llx) of register %s "
222 "would not clear, val[%llx]\n",
223 np->dev->name, (unsigned long long) bits, reg_name,
224 (unsigned long long) nr64(reg));
225 return err;
226 }
227
228 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
229 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
230 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
231 })
232
233 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on)
234 {
235 u64 val = (u64) lp->timer;
236
237 if (on)
238 val |= LDG_IMGMT_ARM;
239
240 nw64(LDG_IMGMT(lp->ldg_num), val);
241 }
242
243 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on)
244 {
245 unsigned long mask_reg, bits;
246 u64 val;
247
248 if (ldn < 0 || ldn > LDN_MAX)
249 return -EINVAL;
250
251 if (ldn < 64) {
252 mask_reg = LD_IM0(ldn);
253 bits = LD_IM0_MASK;
254 } else {
255 mask_reg = LD_IM1(ldn - 64);
256 bits = LD_IM1_MASK;
257 }
258
259 val = nr64(mask_reg);
260 if (on)
261 val &= ~bits;
262 else
263 val |= bits;
264 nw64(mask_reg, val);
265
266 return 0;
267 }
268
269 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on)
270 {
271 struct niu_parent *parent = np->parent;
272 int i;
273
274 for (i = 0; i <= LDN_MAX; i++) {
275 int err;
276
277 if (parent->ldg_map[i] != lp->ldg_num)
278 continue;
279
280 err = niu_ldn_irq_enable(np, i, on);
281 if (err)
282 return err;
283 }
284 return 0;
285 }
286
287 static int niu_enable_interrupts(struct niu *np, int on)
288 {
289 int i;
290
291 for (i = 0; i < np->num_ldg; i++) {
292 struct niu_ldg *lp = &np->ldg[i];
293 int err;
294
295 err = niu_enable_ldn_in_ldg(np, lp, on);
296 if (err)
297 return err;
298 }
299 for (i = 0; i < np->num_ldg; i++)
300 niu_ldg_rearm(np, &np->ldg[i], on);
301
302 return 0;
303 }
304
305 static u32 phy_encode(u32 type, int port)
306 {
307 return (type << (port * 2));
308 }
309
310 static u32 phy_decode(u32 val, int port)
311 {
312 return (val >> (port * 2)) & PORT_TYPE_MASK;
313 }
314
315 static int mdio_wait(struct niu *np)
316 {
317 int limit = 1000;
318 u64 val;
319
320 while (--limit > 0) {
321 val = nr64(MIF_FRAME_OUTPUT);
322 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
323 return val & MIF_FRAME_OUTPUT_DATA;
324
325 udelay(10);
326 }
327
328 return -ENODEV;
329 }
330
331 static int mdio_read(struct niu *np, int port, int dev, int reg)
332 {
333 int err;
334
335 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
336 err = mdio_wait(np);
337 if (err < 0)
338 return err;
339
340 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
341 return mdio_wait(np);
342 }
343
344 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
345 {
346 int err;
347
348 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
349 err = mdio_wait(np);
350 if (err < 0)
351 return err;
352
353 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
354 err = mdio_wait(np);
355 if (err < 0)
356 return err;
357
358 return 0;
359 }
360
361 static int mii_read(struct niu *np, int port, int reg)
362 {
363 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
364 return mdio_wait(np);
365 }
366
367 static int mii_write(struct niu *np, int port, int reg, int data)
368 {
369 int err;
370
371 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
372 err = mdio_wait(np);
373 if (err < 0)
374 return err;
375
376 return 0;
377 }
378
379 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
380 {
381 int err;
382
383 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
384 ESR2_TI_PLL_TX_CFG_L(channel),
385 val & 0xffff);
386 if (!err)
387 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
388 ESR2_TI_PLL_TX_CFG_H(channel),
389 val >> 16);
390 return err;
391 }
392
393 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
394 {
395 int err;
396
397 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
398 ESR2_TI_PLL_RX_CFG_L(channel),
399 val & 0xffff);
400 if (!err)
401 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
402 ESR2_TI_PLL_RX_CFG_H(channel),
403 val >> 16);
404 return err;
405 }
406
407 /* Mode is always 10G fiber. */
408 static int serdes_init_niu(struct niu *np)
409 {
410 struct niu_link_config *lp = &np->link_config;
411 u32 tx_cfg, rx_cfg;
412 unsigned long i;
413
414 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV);
415 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT |
416 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH |
417 PLL_RX_CFG_EQ_LP_ADAPTIVE);
418
419 if (lp->loopback_mode == LOOPBACK_PHY) {
420 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS;
421
422 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
423 ESR2_TI_PLL_TEST_CFG_L, test_cfg);
424
425 tx_cfg |= PLL_TX_CFG_ENTEST;
426 rx_cfg |= PLL_RX_CFG_ENTEST;
427 }
428
429 /* Initialize all 4 lanes of the SERDES. */
430 for (i = 0; i < 4; i++) {
431 int err = esr2_set_tx_cfg(np, i, tx_cfg);
432 if (err)
433 return err;
434 }
435
436 for (i = 0; i < 4; i++) {
437 int err = esr2_set_rx_cfg(np, i, rx_cfg);
438 if (err)
439 return err;
440 }
441
442 return 0;
443 }
444
445 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
446 {
447 int err;
448
449 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
450 if (err >= 0) {
451 *val = (err & 0xffff);
452 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
453 ESR_RXTX_CTRL_H(chan));
454 if (err >= 0)
455 *val |= ((err & 0xffff) << 16);
456 err = 0;
457 }
458 return err;
459 }
460
461 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
462 {
463 int err;
464
465 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
466 ESR_GLUE_CTRL0_L(chan));
467 if (err >= 0) {
468 *val = (err & 0xffff);
469 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
470 ESR_GLUE_CTRL0_H(chan));
471 if (err >= 0) {
472 *val |= ((err & 0xffff) << 16);
473 err = 0;
474 }
475 }
476 return err;
477 }
478
479 static int esr_read_reset(struct niu *np, u32 *val)
480 {
481 int err;
482
483 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
484 ESR_RXTX_RESET_CTRL_L);
485 if (err >= 0) {
486 *val = (err & 0xffff);
487 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
488 ESR_RXTX_RESET_CTRL_H);
489 if (err >= 0) {
490 *val |= ((err & 0xffff) << 16);
491 err = 0;
492 }
493 }
494 return err;
495 }
496
497 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
498 {
499 int err;
500
501 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
502 ESR_RXTX_CTRL_L(chan), val & 0xffff);
503 if (!err)
504 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
505 ESR_RXTX_CTRL_H(chan), (val >> 16));
506 return err;
507 }
508
509 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
510 {
511 int err;
512
513 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
514 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
515 if (!err)
516 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
517 ESR_GLUE_CTRL0_H(chan), (val >> 16));
518 return err;
519 }
520
521 static int esr_reset(struct niu *np)
522 {
523 u32 reset;
524 int err;
525
526 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
527 ESR_RXTX_RESET_CTRL_L, 0x0000);
528 if (err)
529 return err;
530 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
531 ESR_RXTX_RESET_CTRL_H, 0xffff);
532 if (err)
533 return err;
534 udelay(200);
535
536 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
537 ESR_RXTX_RESET_CTRL_L, 0xffff);
538 if (err)
539 return err;
540 udelay(200);
541
542 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
543 ESR_RXTX_RESET_CTRL_H, 0x0000);
544 if (err)
545 return err;
546 udelay(200);
547
548 err = esr_read_reset(np, &reset);
549 if (err)
550 return err;
551 if (reset != 0) {
552 dev_err(np->device, PFX "Port %u ESR_RESET "
553 "did not clear [%08x]\n",
554 np->port, reset);
555 return -ENODEV;
556 }
557
558 return 0;
559 }
560
561 static int serdes_init_10g(struct niu *np)
562 {
563 struct niu_link_config *lp = &np->link_config;
564 unsigned long ctrl_reg, test_cfg_reg, i;
565 u64 ctrl_val, test_cfg_val, sig, mask, val;
566 int err;
567
568 switch (np->port) {
569 case 0:
570 ctrl_reg = ENET_SERDES_0_CTRL_CFG;
571 test_cfg_reg = ENET_SERDES_0_TEST_CFG;
572 break;
573 case 1:
574 ctrl_reg = ENET_SERDES_1_CTRL_CFG;
575 test_cfg_reg = ENET_SERDES_1_TEST_CFG;
576 break;
577
578 default:
579 return -EINVAL;
580 }
581 ctrl_val = (ENET_SERDES_CTRL_SDET_0 |
582 ENET_SERDES_CTRL_SDET_1 |
583 ENET_SERDES_CTRL_SDET_2 |
584 ENET_SERDES_CTRL_SDET_3 |
585 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) |
586 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) |
587 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) |
588 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) |
589 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) |
590 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) |
591 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) |
592 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT));
593 test_cfg_val = 0;
594
595 if (lp->loopback_mode == LOOPBACK_PHY) {
596 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK <<
597 ENET_SERDES_TEST_MD_0_SHIFT) |
598 (ENET_TEST_MD_PAD_LOOPBACK <<
599 ENET_SERDES_TEST_MD_1_SHIFT) |
600 (ENET_TEST_MD_PAD_LOOPBACK <<
601 ENET_SERDES_TEST_MD_2_SHIFT) |
602 (ENET_TEST_MD_PAD_LOOPBACK <<
603 ENET_SERDES_TEST_MD_3_SHIFT));
604 }
605
606 nw64(ctrl_reg, ctrl_val);
607 nw64(test_cfg_reg, test_cfg_val);
608
609 /* Initialize all 4 lanes of the SERDES. */
610 for (i = 0; i < 4; i++) {
611 u32 rxtx_ctrl, glue0;
612
613 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
614 if (err)
615 return err;
616 err = esr_read_glue0(np, i, &glue0);
617 if (err)
618 return err;
619
620 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO);
621 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH |
622 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT));
623
624 glue0 &= ~(ESR_GLUE_CTRL0_SRATE |
625 ESR_GLUE_CTRL0_THCNT |
626 ESR_GLUE_CTRL0_BLTIME);
627 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB |
628 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) |
629 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) |
630 (BLTIME_300_CYCLES <<
631 ESR_GLUE_CTRL0_BLTIME_SHIFT));
632
633 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
634 if (err)
635 return err;
636 err = esr_write_glue0(np, i, glue0);
637 if (err)
638 return err;
639 }
640
641 err = esr_reset(np);
642 if (err)
643 return err;
644
645 sig = nr64(ESR_INT_SIGNALS);
646 switch (np->port) {
647 case 0:
648 mask = ESR_INT_SIGNALS_P0_BITS;
649 val = (ESR_INT_SRDY0_P0 |
650 ESR_INT_DET0_P0 |
651 ESR_INT_XSRDY_P0 |
652 ESR_INT_XDP_P0_CH3 |
653 ESR_INT_XDP_P0_CH2 |
654 ESR_INT_XDP_P0_CH1 |
655 ESR_INT_XDP_P0_CH0);
656 break;
657
658 case 1:
659 mask = ESR_INT_SIGNALS_P1_BITS;
660 val = (ESR_INT_SRDY0_P1 |
661 ESR_INT_DET0_P1 |
662 ESR_INT_XSRDY_P1 |
663 ESR_INT_XDP_P1_CH3 |
664 ESR_INT_XDP_P1_CH2 |
665 ESR_INT_XDP_P1_CH1 |
666 ESR_INT_XDP_P1_CH0);
667 break;
668
669 default:
670 return -EINVAL;
671 }
672
673 if ((sig & mask) != val) {
674 dev_err(np->device, PFX "Port %u signal bits [%08x] are not "
675 "[%08x]\n", np->port, (int) (sig & mask), (int) val);
676 return -ENODEV;
677 }
678
679 return 0;
680 }
681
682 static int serdes_init_1g(struct niu *np)
683 {
684 u64 val;
685
686 val = nr64(ENET_SERDES_1_PLL_CFG);
687 val &= ~ENET_SERDES_PLL_FBDIV2;
688 switch (np->port) {
689 case 0:
690 val |= ENET_SERDES_PLL_HRATE0;
691 break;
692 case 1:
693 val |= ENET_SERDES_PLL_HRATE1;
694 break;
695 case 2:
696 val |= ENET_SERDES_PLL_HRATE2;
697 break;
698 case 3:
699 val |= ENET_SERDES_PLL_HRATE3;
700 break;
701 default:
702 return -EINVAL;
703 }
704 nw64(ENET_SERDES_1_PLL_CFG, val);
705
706 return 0;
707 }
708
709 static int bcm8704_reset(struct niu *np)
710 {
711 int err, limit;
712
713 err = mdio_read(np, np->phy_addr,
714 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
715 if (err < 0)
716 return err;
717 err |= BMCR_RESET;
718 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
719 MII_BMCR, err);
720 if (err)
721 return err;
722
723 limit = 1000;
724 while (--limit >= 0) {
725 err = mdio_read(np, np->phy_addr,
726 BCM8704_PHYXS_DEV_ADDR, MII_BMCR);
727 if (err < 0)
728 return err;
729 if (!(err & BMCR_RESET))
730 break;
731 }
732 if (limit < 0) {
733 dev_err(np->device, PFX "Port %u PHY will not reset "
734 "(bmcr=%04x)\n", np->port, (err & 0xffff));
735 return -ENODEV;
736 }
737 return 0;
738 }
739
740 /* When written, certain PHY registers need to be read back twice
741 * in order for the bits to settle properly.
742 */
743 static int bcm8704_user_dev3_readback(struct niu *np, int reg)
744 {
745 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
746 if (err < 0)
747 return err;
748 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
749 if (err < 0)
750 return err;
751 return 0;
752 }
753
754 static int bcm8704_init_user_dev3(struct niu *np)
755 {
756 int err;
757
758 err = mdio_write(np, np->phy_addr,
759 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL,
760 (USER_CONTROL_OPTXRST_LVL |
761 USER_CONTROL_OPBIASFLT_LVL |
762 USER_CONTROL_OBTMPFLT_LVL |
763 USER_CONTROL_OPPRFLT_LVL |
764 USER_CONTROL_OPTXFLT_LVL |
765 USER_CONTROL_OPRXLOS_LVL |
766 USER_CONTROL_OPRXFLT_LVL |
767 USER_CONTROL_OPTXON_LVL |
768 (0x3f << USER_CONTROL_RES1_SHIFT)));
769 if (err)
770 return err;
771
772 err = mdio_write(np, np->phy_addr,
773 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL,
774 (USER_PMD_TX_CTL_XFP_CLKEN |
775 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) |
776 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) |
777 USER_PMD_TX_CTL_TSCK_LPWREN));
778 if (err)
779 return err;
780
781 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
782 if (err)
783 return err;
784 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
785 if (err)
786 return err;
787
788 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
789 BCM8704_USER_OPT_DIGITAL_CTRL);
790 if (err < 0)
791 return err;
792 err &= ~USER_ODIG_CTRL_GPIOS;
793 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
794 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
795 BCM8704_USER_OPT_DIGITAL_CTRL, err);
796 if (err)
797 return err;
798
799 mdelay(1000);
800
801 return 0;
802 }
803
804 static int mrvl88x2011_act_led(struct niu *np, int val)
805 {
806 int err;
807
808 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
809 MRVL88X2011_LED_8_TO_11_CTL);
810 if (err < 0)
811 return err;
812
813 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
814 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
815
816 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
817 MRVL88X2011_LED_8_TO_11_CTL, err);
818 }
819
820 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate)
821 {
822 int err;
823
824 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
825 MRVL88X2011_LED_BLINK_CTL);
826 if (err >= 0) {
827 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
828 err |= (rate << 4);
829
830 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
831 MRVL88X2011_LED_BLINK_CTL, err);
832 }
833
834 return err;
835 }
836
837 static int xcvr_init_10g_mrvl88x2011(struct niu *np)
838 {
839 int err;
840
841 /* Set LED functions */
842 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
843 if (err)
844 return err;
845
846 /* led activity */
847 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
848 if (err)
849 return err;
850
851 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
852 MRVL88X2011_GENERAL_CTL);
853 if (err < 0)
854 return err;
855
856 err |= MRVL88X2011_ENA_XFPREFCLK;
857
858 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
859 MRVL88X2011_GENERAL_CTL, err);
860 if (err < 0)
861 return err;
862
863 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
864 MRVL88X2011_PMA_PMD_CTL_1);
865 if (err < 0)
866 return err;
867
868 if (np->link_config.loopback_mode == LOOPBACK_MAC)
869 err |= MRVL88X2011_LOOPBACK;
870 else
871 err &= ~MRVL88X2011_LOOPBACK;
872
873 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
874 MRVL88X2011_PMA_PMD_CTL_1, err);
875 if (err < 0)
876 return err;
877
878 /* Enable PMD */
879 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
880 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX);
881 }
882
883 static int xcvr_init_10g_bcm8704(struct niu *np)
884 {
885 struct niu_link_config *lp = &np->link_config;
886 u16 analog_stat0, tx_alarm_status;
887 int err;
888
889 err = bcm8704_reset(np);
890 if (err)
891 return err;
892
893 err = bcm8704_init_user_dev3(np);
894 if (err)
895 return err;
896
897 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
898 MII_BMCR);
899 if (err < 0)
900 return err;
901 err &= ~BMCR_LOOPBACK;
902
903 if (lp->loopback_mode == LOOPBACK_MAC)
904 err |= BMCR_LOOPBACK;
905
906 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
907 MII_BMCR, err);
908 if (err)
909 return err;
910
911 #if 1
912 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
913 MII_STAT1000);
914 if (err < 0)
915 return err;
916 pr_info(PFX "Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
917 np->port, err);
918
919 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
920 if (err < 0)
921 return err;
922 pr_info(PFX "Port %u USER_DEV3(0x20) [%04x]\n",
923 np->port, err);
924
925 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
926 MII_NWAYTEST);
927 if (err < 0)
928 return err;
929 pr_info(PFX "Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
930 np->port, err);
931 #endif
932
933 /* XXX dig this out it might not be so useful XXX */
934 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
935 BCM8704_USER_ANALOG_STATUS0);
936 if (err < 0)
937 return err;
938 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
939 BCM8704_USER_ANALOG_STATUS0);
940 if (err < 0)
941 return err;
942 analog_stat0 = err;
943
944 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
945 BCM8704_USER_TX_ALARM_STATUS);
946 if (err < 0)
947 return err;
948 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
949 BCM8704_USER_TX_ALARM_STATUS);
950 if (err < 0)
951 return err;
952 tx_alarm_status = err;
953
954 if (analog_stat0 != 0x03fc) {
955 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) {
956 pr_info(PFX "Port %u cable not connected "
957 "or bad cable.\n", np->port);
958 } else if (analog_stat0 == 0x639c) {
959 pr_info(PFX "Port %u optical module is bad "
960 "or missing.\n", np->port);
961 }
962 }
963
964 return 0;
965 }
966
967 static int xcvr_init_10g(struct niu *np)
968 {
969 int phy_id, err;
970 u64 val;
971
972 val = nr64_mac(XMAC_CONFIG);
973 val &= ~XMAC_CONFIG_LED_POLARITY;
974 val |= XMAC_CONFIG_FORCE_LED_ON;
975 nw64_mac(XMAC_CONFIG, val);
976
977 /* XXX shared resource, lock parent XXX */
978 val = nr64(MIF_CONFIG);
979 val |= MIF_CONFIG_INDIRECT_MODE;
980 nw64(MIF_CONFIG, val);
981
982 phy_id = phy_decode(np->parent->port_phy, np->port);
983 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
984
985 /* handle different phy types */
986 switch (phy_id & NIU_PHY_ID_MASK) {
987 case NIU_PHY_ID_MRVL88X2011:
988 err = xcvr_init_10g_mrvl88x2011(np);
989 break;
990
991 default: /* bcom 8704 */
992 err = xcvr_init_10g_bcm8704(np);
993 break;
994 }
995
996 return 0;
997 }
998
999 static int mii_reset(struct niu *np)
1000 {
1001 int limit, err;
1002
1003 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1004 if (err)
1005 return err;
1006
1007 limit = 1000;
1008 while (--limit >= 0) {
1009 udelay(500);
1010 err = mii_read(np, np->phy_addr, MII_BMCR);
1011 if (err < 0)
1012 return err;
1013 if (!(err & BMCR_RESET))
1014 break;
1015 }
1016 if (limit < 0) {
1017 dev_err(np->device, PFX "Port %u MII would not reset, "
1018 "bmcr[%04x]\n", np->port, err);
1019 return -ENODEV;
1020 }
1021
1022 return 0;
1023 }
1024
1025 static int mii_init_common(struct niu *np)
1026 {
1027 struct niu_link_config *lp = &np->link_config;
1028 u16 bmcr, bmsr, adv, estat;
1029 int err;
1030
1031 err = mii_reset(np);
1032 if (err)
1033 return err;
1034
1035 err = mii_read(np, np->phy_addr, MII_BMSR);
1036 if (err < 0)
1037 return err;
1038 bmsr = err;
1039
1040 estat = 0;
1041 if (bmsr & BMSR_ESTATEN) {
1042 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1043 if (err < 0)
1044 return err;
1045 estat = err;
1046 }
1047
1048 bmcr = 0;
1049 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1050 if (err)
1051 return err;
1052
1053 if (lp->loopback_mode == LOOPBACK_MAC) {
1054 bmcr |= BMCR_LOOPBACK;
1055 if (lp->active_speed == SPEED_1000)
1056 bmcr |= BMCR_SPEED1000;
1057 if (lp->active_duplex == DUPLEX_FULL)
1058 bmcr |= BMCR_FULLDPLX;
1059 }
1060
1061 if (lp->loopback_mode == LOOPBACK_PHY) {
1062 u16 aux;
1063
1064 aux = (BCM5464R_AUX_CTL_EXT_LB |
1065 BCM5464R_AUX_CTL_WRITE_1);
1066 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1067 if (err)
1068 return err;
1069 }
1070
1071 /* XXX configurable XXX */
1072 /* XXX for now don't advertise half-duplex or asym pause... XXX */
1073 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1074 if (bmsr & BMSR_10FULL)
1075 adv |= ADVERTISE_10FULL;
1076 if (bmsr & BMSR_100FULL)
1077 adv |= ADVERTISE_100FULL;
1078 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1079 if (err)
1080 return err;
1081
1082 if (bmsr & BMSR_ESTATEN) {
1083 u16 ctrl1000 = 0;
1084
1085 if (estat & ESTATUS_1000_TFULL)
1086 ctrl1000 |= ADVERTISE_1000FULL;
1087 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1088 if (err)
1089 return err;
1090 }
1091 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1092
1093 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1094 if (err)
1095 return err;
1096
1097 err = mii_read(np, np->phy_addr, MII_BMCR);
1098 if (err < 0)
1099 return err;
1100 err = mii_read(np, np->phy_addr, MII_BMSR);
1101 if (err < 0)
1102 return err;
1103 #if 0
1104 pr_info(PFX "Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1105 np->port, bmcr, bmsr);
1106 #endif
1107
1108 return 0;
1109 }
1110
1111 static int xcvr_init_1g(struct niu *np)
1112 {
1113 u64 val;
1114
1115 /* XXX shared resource, lock parent XXX */
1116 val = nr64(MIF_CONFIG);
1117 val &= ~MIF_CONFIG_INDIRECT_MODE;
1118 nw64(MIF_CONFIG, val);
1119
1120 return mii_init_common(np);
1121 }
1122
1123 static int niu_xcvr_init(struct niu *np)
1124 {
1125 const struct niu_phy_ops *ops = np->phy_ops;
1126 int err;
1127
1128 err = 0;
1129 if (ops->xcvr_init)
1130 err = ops->xcvr_init(np);
1131
1132 return err;
1133 }
1134
1135 static int niu_serdes_init(struct niu *np)
1136 {
1137 const struct niu_phy_ops *ops = np->phy_ops;
1138 int err;
1139
1140 err = 0;
1141 if (ops->serdes_init)
1142 err = ops->serdes_init(np);
1143
1144 return err;
1145 }
1146
1147 static void niu_init_xif(struct niu *);
1148 static void niu_handle_led(struct niu *, int status);
1149
1150 static int niu_link_status_common(struct niu *np, int link_up)
1151 {
1152 struct niu_link_config *lp = &np->link_config;
1153 struct net_device *dev = np->dev;
1154 unsigned long flags;
1155
1156 if (!netif_carrier_ok(dev) && link_up) {
1157 niuinfo(LINK, "%s: Link is up at %s, %s duplex\n",
1158 dev->name,
1159 (lp->active_speed == SPEED_10000 ?
1160 "10Gb/sec" :
1161 (lp->active_speed == SPEED_1000 ?
1162 "1Gb/sec" :
1163 (lp->active_speed == SPEED_100 ?
1164 "100Mbit/sec" : "10Mbit/sec"))),
1165 (lp->active_duplex == DUPLEX_FULL ?
1166 "full" : "half"));
1167
1168 spin_lock_irqsave(&np->lock, flags);
1169 niu_init_xif(np);
1170 niu_handle_led(np, 1);
1171 spin_unlock_irqrestore(&np->lock, flags);
1172
1173 netif_carrier_on(dev);
1174 } else if (netif_carrier_ok(dev) && !link_up) {
1175 niuwarn(LINK, "%s: Link is down\n", dev->name);
1176 spin_lock_irqsave(&np->lock, flags);
1177 niu_handle_led(np, 0);
1178 spin_unlock_irqrestore(&np->lock, flags);
1179 netif_carrier_off(dev);
1180 }
1181
1182 return 0;
1183 }
1184
1185 static int link_status_10g_mrvl(struct niu *np, int *link_up_p)
1186 {
1187 int err, link_up, pma_status, pcs_status;
1188
1189 link_up = 0;
1190
1191 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1192 MRVL88X2011_10G_PMD_STATUS_2);
1193 if (err < 0)
1194 goto out;
1195
1196 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1197 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1198 MRVL88X2011_PMA_PMD_STATUS_1);
1199 if (err < 0)
1200 goto out;
1201
1202 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1203
1204 /* Check PMC Register : 3.0001.2 == 1: read twice */
1205 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1206 MRVL88X2011_PMA_PMD_STATUS_1);
1207 if (err < 0)
1208 goto out;
1209
1210 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1211 MRVL88X2011_PMA_PMD_STATUS_1);
1212 if (err < 0)
1213 goto out;
1214
1215 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1216
1217 /* Check XGXS Register : 4.0018.[0-3,12] */
1218 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1219 MRVL88X2011_10G_XGXS_LANE_STAT);
1220 if (err < 0)
1221 goto out;
1222
1223 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1224 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 |
1225 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC |
1226 0x800))
1227 link_up = (pma_status && pcs_status) ? 1 : 0;
1228
1229 np->link_config.active_speed = SPEED_10000;
1230 np->link_config.active_duplex = DUPLEX_FULL;
1231 err = 0;
1232 out:
1233 mrvl88x2011_act_led(np, (link_up ?
1234 MRVL88X2011_LED_CTL_PCS_ACT :
1235 MRVL88X2011_LED_CTL_OFF));
1236
1237 *link_up_p = link_up;
1238 return err;
1239 }
1240
1241 static int link_status_10g_bcom(struct niu *np, int *link_up_p)
1242 {
1243 int err, link_up;
1244
1245 link_up = 0;
1246
1247 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1248 BCM8704_PMD_RCV_SIGDET);
1249 if (err < 0)
1250 goto out;
1251 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1252 err = 0;
1253 goto out;
1254 }
1255
1256 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1257 BCM8704_PCS_10G_R_STATUS);
1258 if (err < 0)
1259 goto out;
1260 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1261 err = 0;
1262 goto out;
1263 }
1264
1265 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1266 BCM8704_PHYXS_XGXS_LANE_STAT);
1267 if (err < 0)
1268 goto out;
1269
1270 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
1271 PHYXS_XGXS_LANE_STAT_MAGIC |
1272 PHYXS_XGXS_LANE_STAT_LANE3 |
1273 PHYXS_XGXS_LANE_STAT_LANE2 |
1274 PHYXS_XGXS_LANE_STAT_LANE1 |
1275 PHYXS_XGXS_LANE_STAT_LANE0)) {
1276 err = 0;
1277 goto out;
1278 }
1279
1280 link_up = 1;
1281 np->link_config.active_speed = SPEED_10000;
1282 np->link_config.active_duplex = DUPLEX_FULL;
1283 err = 0;
1284
1285 out:
1286 *link_up_p = link_up;
1287 return err;
1288 }
1289
1290 static int link_status_10g(struct niu *np, int *link_up_p)
1291 {
1292 unsigned long flags;
1293 int err = -EINVAL;
1294
1295 spin_lock_irqsave(&np->lock, flags);
1296
1297 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) {
1298 int phy_id;
1299
1300 phy_id = phy_decode(np->parent->port_phy, np->port);
1301 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1302
1303 /* handle different phy types */
1304 switch (phy_id & NIU_PHY_ID_MASK) {
1305 case NIU_PHY_ID_MRVL88X2011:
1306 err = link_status_10g_mrvl(np, link_up_p);
1307 break;
1308
1309 default: /* bcom 8704 */
1310 err = link_status_10g_bcom(np, link_up_p);
1311 break;
1312 }
1313 }
1314
1315 spin_unlock_irqrestore(&np->lock, flags);
1316
1317 return err;
1318 }
1319
1320 static int link_status_1g(struct niu *np, int *link_up_p)
1321 {
1322 struct niu_link_config *lp = &np->link_config;
1323 u16 current_speed, bmsr;
1324 unsigned long flags;
1325 u8 current_duplex;
1326 int err, link_up;
1327
1328 link_up = 0;
1329 current_speed = SPEED_INVALID;
1330 current_duplex = DUPLEX_INVALID;
1331
1332 spin_lock_irqsave(&np->lock, flags);
1333
1334 err = -EINVAL;
1335 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
1336 goto out;
1337
1338 err = mii_read(np, np->phy_addr, MII_BMSR);
1339 if (err < 0)
1340 goto out;
1341
1342 bmsr = err;
1343 if (bmsr & BMSR_LSTATUS) {
1344 u16 adv, lpa, common, estat;
1345
1346 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1347 if (err < 0)
1348 goto out;
1349 adv = err;
1350
1351 err = mii_read(np, np->phy_addr, MII_LPA);
1352 if (err < 0)
1353 goto out;
1354 lpa = err;
1355
1356 common = adv & lpa;
1357
1358 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1359 if (err < 0)
1360 goto out;
1361 estat = err;
1362
1363 link_up = 1;
1364 if (estat & (ESTATUS_1000_TFULL | ESTATUS_1000_THALF)) {
1365 current_speed = SPEED_1000;
1366 if (estat & ESTATUS_1000_TFULL)
1367 current_duplex = DUPLEX_FULL;
1368 else
1369 current_duplex = DUPLEX_HALF;
1370 } else {
1371 if (common & ADVERTISE_100BASE4) {
1372 current_speed = SPEED_100;
1373 current_duplex = DUPLEX_HALF;
1374 } else if (common & ADVERTISE_100FULL) {
1375 current_speed = SPEED_100;
1376 current_duplex = DUPLEX_FULL;
1377 } else if (common & ADVERTISE_100HALF) {
1378 current_speed = SPEED_100;
1379 current_duplex = DUPLEX_HALF;
1380 } else if (common & ADVERTISE_10FULL) {
1381 current_speed = SPEED_10;
1382 current_duplex = DUPLEX_FULL;
1383 } else if (common & ADVERTISE_10HALF) {
1384 current_speed = SPEED_10;
1385 current_duplex = DUPLEX_HALF;
1386 } else
1387 link_up = 0;
1388 }
1389 }
1390 lp->active_speed = current_speed;
1391 lp->active_duplex = current_duplex;
1392 err = 0;
1393
1394 out:
1395 spin_unlock_irqrestore(&np->lock, flags);
1396
1397 *link_up_p = link_up;
1398 return err;
1399 }
1400
1401 static int niu_link_status(struct niu *np, int *link_up_p)
1402 {
1403 const struct niu_phy_ops *ops = np->phy_ops;
1404 int err;
1405
1406 err = 0;
1407 if (ops->link_status)
1408 err = ops->link_status(np, link_up_p);
1409
1410 return err;
1411 }
1412
1413 static void niu_timer(unsigned long __opaque)
1414 {
1415 struct niu *np = (struct niu *) __opaque;
1416 unsigned long off;
1417 int err, link_up;
1418
1419 err = niu_link_status(np, &link_up);
1420 if (!err)
1421 niu_link_status_common(np, link_up);
1422
1423 if (netif_carrier_ok(np->dev))
1424 off = 5 * HZ;
1425 else
1426 off = 1 * HZ;
1427 np->timer.expires = jiffies + off;
1428
1429 add_timer(&np->timer);
1430 }
1431
1432 static const struct niu_phy_ops phy_ops_10g_fiber_niu = {
1433 .serdes_init = serdes_init_niu,
1434 .xcvr_init = xcvr_init_10g,
1435 .link_status = link_status_10g,
1436 };
1437
1438 static const struct niu_phy_ops phy_ops_10g_fiber = {
1439 .serdes_init = serdes_init_10g,
1440 .xcvr_init = xcvr_init_10g,
1441 .link_status = link_status_10g,
1442 };
1443
1444 static const struct niu_phy_ops phy_ops_10g_copper = {
1445 .serdes_init = serdes_init_10g,
1446 .link_status = link_status_10g, /* XXX */
1447 };
1448
1449 static const struct niu_phy_ops phy_ops_1g_fiber = {
1450 .serdes_init = serdes_init_1g,
1451 .xcvr_init = xcvr_init_1g,
1452 .link_status = link_status_1g,
1453 };
1454
1455 static const struct niu_phy_ops phy_ops_1g_copper = {
1456 .xcvr_init = xcvr_init_1g,
1457 .link_status = link_status_1g,
1458 };
1459
1460 struct niu_phy_template {
1461 const struct niu_phy_ops *ops;
1462 u32 phy_addr_base;
1463 };
1464
1465 static const struct niu_phy_template phy_template_niu = {
1466 .ops = &phy_ops_10g_fiber_niu,
1467 .phy_addr_base = 16,
1468 };
1469
1470 static const struct niu_phy_template phy_template_10g_fiber = {
1471 .ops = &phy_ops_10g_fiber,
1472 .phy_addr_base = 8,
1473 };
1474
1475 static const struct niu_phy_template phy_template_10g_copper = {
1476 .ops = &phy_ops_10g_copper,
1477 .phy_addr_base = 10,
1478 };
1479
1480 static const struct niu_phy_template phy_template_1g_fiber = {
1481 .ops = &phy_ops_1g_fiber,
1482 .phy_addr_base = 0,
1483 };
1484
1485 static const struct niu_phy_template phy_template_1g_copper = {
1486 .ops = &phy_ops_1g_copper,
1487 .phy_addr_base = 0,
1488 };
1489
1490 static int niu_determine_phy_disposition(struct niu *np)
1491 {
1492 struct niu_parent *parent = np->parent;
1493 u8 plat_type = parent->plat_type;
1494 const struct niu_phy_template *tp;
1495 u32 phy_addr_off = 0;
1496
1497 if (plat_type == PLAT_TYPE_NIU) {
1498 tp = &phy_template_niu;
1499 phy_addr_off += np->port;
1500 } else {
1501 switch (np->flags & (NIU_FLAGS_10G | NIU_FLAGS_FIBER)) {
1502 case 0:
1503 /* 1G copper */
1504 tp = &phy_template_1g_copper;
1505 if (plat_type == PLAT_TYPE_VF_P0)
1506 phy_addr_off = 10;
1507 else if (plat_type == PLAT_TYPE_VF_P1)
1508 phy_addr_off = 26;
1509
1510 phy_addr_off += (np->port ^ 0x3);
1511 break;
1512
1513 case NIU_FLAGS_10G:
1514 /* 10G copper */
1515 tp = &phy_template_1g_copper;
1516 break;
1517
1518 case NIU_FLAGS_FIBER:
1519 /* 1G fiber */
1520 tp = &phy_template_1g_fiber;
1521 break;
1522
1523 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
1524 /* 10G fiber */
1525 tp = &phy_template_10g_fiber;
1526 if (plat_type == PLAT_TYPE_VF_P0 ||
1527 plat_type == PLAT_TYPE_VF_P1)
1528 phy_addr_off = 8;
1529 phy_addr_off += np->port;
1530 break;
1531
1532 default:
1533 return -EINVAL;
1534 }
1535 }
1536
1537 np->phy_ops = tp->ops;
1538 np->phy_addr = tp->phy_addr_base + phy_addr_off;
1539
1540 return 0;
1541 }
1542
1543 static int niu_init_link(struct niu *np)
1544 {
1545 struct niu_parent *parent = np->parent;
1546 int err, ignore;
1547
1548 if (parent->plat_type == PLAT_TYPE_NIU) {
1549 err = niu_xcvr_init(np);
1550 if (err)
1551 return err;
1552 msleep(200);
1553 }
1554 err = niu_serdes_init(np);
1555 if (err)
1556 return err;
1557 msleep(200);
1558 err = niu_xcvr_init(np);
1559 if (!err)
1560 niu_link_status(np, &ignore);
1561 return 0;
1562 }
1563
1564 static void niu_set_primary_mac(struct niu *np, unsigned char *addr)
1565 {
1566 u16 reg0 = addr[4] << 8 | addr[5];
1567 u16 reg1 = addr[2] << 8 | addr[3];
1568 u16 reg2 = addr[0] << 8 | addr[1];
1569
1570 if (np->flags & NIU_FLAGS_XMAC) {
1571 nw64_mac(XMAC_ADDR0, reg0);
1572 nw64_mac(XMAC_ADDR1, reg1);
1573 nw64_mac(XMAC_ADDR2, reg2);
1574 } else {
1575 nw64_mac(BMAC_ADDR0, reg0);
1576 nw64_mac(BMAC_ADDR1, reg1);
1577 nw64_mac(BMAC_ADDR2, reg2);
1578 }
1579 }
1580
1581 static int niu_num_alt_addr(struct niu *np)
1582 {
1583 if (np->flags & NIU_FLAGS_XMAC)
1584 return XMAC_NUM_ALT_ADDR;
1585 else
1586 return BMAC_NUM_ALT_ADDR;
1587 }
1588
1589 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr)
1590 {
1591 u16 reg0 = addr[4] << 8 | addr[5];
1592 u16 reg1 = addr[2] << 8 | addr[3];
1593 u16 reg2 = addr[0] << 8 | addr[1];
1594
1595 if (index >= niu_num_alt_addr(np))
1596 return -EINVAL;
1597
1598 if (np->flags & NIU_FLAGS_XMAC) {
1599 nw64_mac(XMAC_ALT_ADDR0(index), reg0);
1600 nw64_mac(XMAC_ALT_ADDR1(index), reg1);
1601 nw64_mac(XMAC_ALT_ADDR2(index), reg2);
1602 } else {
1603 nw64_mac(BMAC_ALT_ADDR0(index), reg0);
1604 nw64_mac(BMAC_ALT_ADDR1(index), reg1);
1605 nw64_mac(BMAC_ALT_ADDR2(index), reg2);
1606 }
1607
1608 return 0;
1609 }
1610
1611 static int niu_enable_alt_mac(struct niu *np, int index, int on)
1612 {
1613 unsigned long reg;
1614 u64 val, mask;
1615
1616 if (index >= niu_num_alt_addr(np))
1617 return -EINVAL;
1618
1619 if (np->flags & NIU_FLAGS_XMAC)
1620 reg = XMAC_ADDR_CMPEN;
1621 else
1622 reg = BMAC_ADDR_CMPEN;
1623
1624 mask = 1 << index;
1625
1626 val = nr64_mac(reg);
1627 if (on)
1628 val |= mask;
1629 else
1630 val &= ~mask;
1631 nw64_mac(reg, val);
1632
1633 return 0;
1634 }
1635
1636 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg,
1637 int num, int mac_pref)
1638 {
1639 u64 val = nr64_mac(reg);
1640 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
1641 val |= num;
1642 if (mac_pref)
1643 val |= HOST_INFO_MPR;
1644 nw64_mac(reg, val);
1645 }
1646
1647 static int __set_rdc_table_num(struct niu *np,
1648 int xmac_index, int bmac_index,
1649 int rdc_table_num, int mac_pref)
1650 {
1651 unsigned long reg;
1652
1653 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN)
1654 return -EINVAL;
1655 if (np->flags & NIU_FLAGS_XMAC)
1656 reg = XMAC_HOST_INFO(xmac_index);
1657 else
1658 reg = BMAC_HOST_INFO(bmac_index);
1659 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref);
1660 return 0;
1661 }
1662
1663 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num,
1664 int mac_pref)
1665 {
1666 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref);
1667 }
1668
1669 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num,
1670 int mac_pref)
1671 {
1672 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref);
1673 }
1674
1675 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx,
1676 int table_num, int mac_pref)
1677 {
1678 if (idx >= niu_num_alt_addr(np))
1679 return -EINVAL;
1680 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref);
1681 }
1682
1683 static u64 vlan_entry_set_parity(u64 reg_val)
1684 {
1685 u64 port01_mask;
1686 u64 port23_mask;
1687
1688 port01_mask = 0x00ff;
1689 port23_mask = 0xff00;
1690
1691 if (hweight64(reg_val & port01_mask) & 1)
1692 reg_val |= ENET_VLAN_TBL_PARITY0;
1693 else
1694 reg_val &= ~ENET_VLAN_TBL_PARITY0;
1695
1696 if (hweight64(reg_val & port23_mask) & 1)
1697 reg_val |= ENET_VLAN_TBL_PARITY1;
1698 else
1699 reg_val &= ~ENET_VLAN_TBL_PARITY1;
1700
1701 return reg_val;
1702 }
1703
1704 static void vlan_tbl_write(struct niu *np, unsigned long index,
1705 int port, int vpr, int rdc_table)
1706 {
1707 u64 reg_val = nr64(ENET_VLAN_TBL(index));
1708
1709 reg_val &= ~((ENET_VLAN_TBL_VPR |
1710 ENET_VLAN_TBL_VLANRDCTBLN) <<
1711 ENET_VLAN_TBL_SHIFT(port));
1712 if (vpr)
1713 reg_val |= (ENET_VLAN_TBL_VPR <<
1714 ENET_VLAN_TBL_SHIFT(port));
1715 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
1716
1717 reg_val = vlan_entry_set_parity(reg_val);
1718
1719 nw64(ENET_VLAN_TBL(index), reg_val);
1720 }
1721
1722 static void vlan_tbl_clear(struct niu *np)
1723 {
1724 int i;
1725
1726 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++)
1727 nw64(ENET_VLAN_TBL(i), 0);
1728 }
1729
1730 static int tcam_wait_bit(struct niu *np, u64 bit)
1731 {
1732 int limit = 1000;
1733
1734 while (--limit > 0) {
1735 if (nr64(TCAM_CTL) & bit)
1736 break;
1737 udelay(1);
1738 }
1739 if (limit < 0)
1740 return -ENODEV;
1741
1742 return 0;
1743 }
1744
1745 static int tcam_flush(struct niu *np, int index)
1746 {
1747 nw64(TCAM_KEY_0, 0x00);
1748 nw64(TCAM_KEY_MASK_0, 0xff);
1749 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
1750
1751 return tcam_wait_bit(np, TCAM_CTL_STAT);
1752 }
1753
1754 #if 0
1755 static int tcam_read(struct niu *np, int index,
1756 u64 *key, u64 *mask)
1757 {
1758 int err;
1759
1760 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
1761 err = tcam_wait_bit(np, TCAM_CTL_STAT);
1762 if (!err) {
1763 key[0] = nr64(TCAM_KEY_0);
1764 key[1] = nr64(TCAM_KEY_1);
1765 key[2] = nr64(TCAM_KEY_2);
1766 key[3] = nr64(TCAM_KEY_3);
1767 mask[0] = nr64(TCAM_KEY_MASK_0);
1768 mask[1] = nr64(TCAM_KEY_MASK_1);
1769 mask[2] = nr64(TCAM_KEY_MASK_2);
1770 mask[3] = nr64(TCAM_KEY_MASK_3);
1771 }
1772 return err;
1773 }
1774 #endif
1775
1776 static int tcam_write(struct niu *np, int index,
1777 u64 *key, u64 *mask)
1778 {
1779 nw64(TCAM_KEY_0, key[0]);
1780 nw64(TCAM_KEY_1, key[1]);
1781 nw64(TCAM_KEY_2, key[2]);
1782 nw64(TCAM_KEY_3, key[3]);
1783 nw64(TCAM_KEY_MASK_0, mask[0]);
1784 nw64(TCAM_KEY_MASK_1, mask[1]);
1785 nw64(TCAM_KEY_MASK_2, mask[2]);
1786 nw64(TCAM_KEY_MASK_3, mask[3]);
1787 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
1788
1789 return tcam_wait_bit(np, TCAM_CTL_STAT);
1790 }
1791
1792 #if 0
1793 static int tcam_assoc_read(struct niu *np, int index, u64 *data)
1794 {
1795 int err;
1796
1797 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
1798 err = tcam_wait_bit(np, TCAM_CTL_STAT);
1799 if (!err)
1800 *data = nr64(TCAM_KEY_1);
1801
1802 return err;
1803 }
1804 #endif
1805
1806 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data)
1807 {
1808 nw64(TCAM_KEY_1, assoc_data);
1809 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
1810
1811 return tcam_wait_bit(np, TCAM_CTL_STAT);
1812 }
1813
1814 static void tcam_enable(struct niu *np, int on)
1815 {
1816 u64 val = nr64(FFLP_CFG_1);
1817
1818 if (on)
1819 val &= ~FFLP_CFG_1_TCAM_DIS;
1820 else
1821 val |= FFLP_CFG_1_TCAM_DIS;
1822 nw64(FFLP_CFG_1, val);
1823 }
1824
1825 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio)
1826 {
1827 u64 val = nr64(FFLP_CFG_1);
1828
1829 val &= ~(FFLP_CFG_1_FFLPINITDONE |
1830 FFLP_CFG_1_CAMLAT |
1831 FFLP_CFG_1_CAMRATIO);
1832 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
1833 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
1834 nw64(FFLP_CFG_1, val);
1835
1836 val = nr64(FFLP_CFG_1);
1837 val |= FFLP_CFG_1_FFLPINITDONE;
1838 nw64(FFLP_CFG_1, val);
1839 }
1840
1841 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class,
1842 int on)
1843 {
1844 unsigned long reg;
1845 u64 val;
1846
1847 if (class < CLASS_CODE_ETHERTYPE1 ||
1848 class > CLASS_CODE_ETHERTYPE2)
1849 return -EINVAL;
1850
1851 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
1852 val = nr64(reg);
1853 if (on)
1854 val |= L2_CLS_VLD;
1855 else
1856 val &= ~L2_CLS_VLD;
1857 nw64(reg, val);
1858
1859 return 0;
1860 }
1861
1862 #if 0
1863 static int tcam_user_eth_class_set(struct niu *np, unsigned long class,
1864 u64 ether_type)
1865 {
1866 unsigned long reg;
1867 u64 val;
1868
1869 if (class < CLASS_CODE_ETHERTYPE1 ||
1870 class > CLASS_CODE_ETHERTYPE2 ||
1871 (ether_type & ~(u64)0xffff) != 0)
1872 return -EINVAL;
1873
1874 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1);
1875 val = nr64(reg);
1876 val &= ~L2_CLS_ETYPE;
1877 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
1878 nw64(reg, val);
1879
1880 return 0;
1881 }
1882 #endif
1883
1884 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class,
1885 int on)
1886 {
1887 unsigned long reg;
1888 u64 val;
1889
1890 if (class < CLASS_CODE_USER_PROG1 ||
1891 class > CLASS_CODE_USER_PROG4)
1892 return -EINVAL;
1893
1894 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
1895 val = nr64(reg);
1896 if (on)
1897 val |= L3_CLS_VALID;
1898 else
1899 val &= ~L3_CLS_VALID;
1900 nw64(reg, val);
1901
1902 return 0;
1903 }
1904
1905 #if 0
1906 static int tcam_user_ip_class_set(struct niu *np, unsigned long class,
1907 int ipv6, u64 protocol_id,
1908 u64 tos_mask, u64 tos_val)
1909 {
1910 unsigned long reg;
1911 u64 val;
1912
1913 if (class < CLASS_CODE_USER_PROG1 ||
1914 class > CLASS_CODE_USER_PROG4 ||
1915 (protocol_id & ~(u64)0xff) != 0 ||
1916 (tos_mask & ~(u64)0xff) != 0 ||
1917 (tos_val & ~(u64)0xff) != 0)
1918 return -EINVAL;
1919
1920 reg = L3_CLS(class - CLASS_CODE_USER_PROG1);
1921 val = nr64(reg);
1922 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
1923 L3_CLS_TOSMASK | L3_CLS_TOS);
1924 if (ipv6)
1925 val |= L3_CLS_IPVER;
1926 val |= (protocol_id << L3_CLS_PID_SHIFT);
1927 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
1928 val |= (tos_val << L3_CLS_TOS_SHIFT);
1929 nw64(reg, val);
1930
1931 return 0;
1932 }
1933 #endif
1934
1935 static int tcam_early_init(struct niu *np)
1936 {
1937 unsigned long i;
1938 int err;
1939
1940 tcam_enable(np, 0);
1941 tcam_set_lat_and_ratio(np,
1942 DEFAULT_TCAM_LATENCY,
1943 DEFAULT_TCAM_ACCESS_RATIO);
1944 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) {
1945 err = tcam_user_eth_class_enable(np, i, 0);
1946 if (err)
1947 return err;
1948 }
1949 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) {
1950 err = tcam_user_ip_class_enable(np, i, 0);
1951 if (err)
1952 return err;
1953 }
1954
1955 return 0;
1956 }
1957
1958 static int tcam_flush_all(struct niu *np)
1959 {
1960 unsigned long i;
1961
1962 for (i = 0; i < np->parent->tcam_num_entries; i++) {
1963 int err = tcam_flush(np, i);
1964 if (err)
1965 return err;
1966 }
1967 return 0;
1968 }
1969
1970 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries)
1971 {
1972 return ((u64)index | (num_entries == 1 ?
1973 HASH_TBL_ADDR_AUTOINC : 0));
1974 }
1975
1976 #if 0
1977 static int hash_read(struct niu *np, unsigned long partition,
1978 unsigned long index, unsigned long num_entries,
1979 u64 *data)
1980 {
1981 u64 val = hash_addr_regval(index, num_entries);
1982 unsigned long i;
1983
1984 if (partition >= FCRAM_NUM_PARTITIONS ||
1985 index + num_entries > FCRAM_SIZE)
1986 return -EINVAL;
1987
1988 nw64(HASH_TBL_ADDR(partition), val);
1989 for (i = 0; i < num_entries; i++)
1990 data[i] = nr64(HASH_TBL_DATA(partition));
1991
1992 return 0;
1993 }
1994 #endif
1995
1996 static int hash_write(struct niu *np, unsigned long partition,
1997 unsigned long index, unsigned long num_entries,
1998 u64 *data)
1999 {
2000 u64 val = hash_addr_regval(index, num_entries);
2001 unsigned long i;
2002
2003 if (partition >= FCRAM_NUM_PARTITIONS ||
2004 index + (num_entries * 8) > FCRAM_SIZE)
2005 return -EINVAL;
2006
2007 nw64(HASH_TBL_ADDR(partition), val);
2008 for (i = 0; i < num_entries; i++)
2009 nw64(HASH_TBL_DATA(partition), data[i]);
2010
2011 return 0;
2012 }
2013
2014 static void fflp_reset(struct niu *np)
2015 {
2016 u64 val;
2017
2018 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
2019 udelay(10);
2020 nw64(FFLP_CFG_1, 0);
2021
2022 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
2023 nw64(FFLP_CFG_1, val);
2024 }
2025
2026 static void fflp_set_timings(struct niu *np)
2027 {
2028 u64 val = nr64(FFLP_CFG_1);
2029
2030 val &= ~FFLP_CFG_1_FFLPINITDONE;
2031 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
2032 nw64(FFLP_CFG_1, val);
2033
2034 val = nr64(FFLP_CFG_1);
2035 val |= FFLP_CFG_1_FFLPINITDONE;
2036 nw64(FFLP_CFG_1, val);
2037
2038 val = nr64(FCRAM_REF_TMR);
2039 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
2040 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
2041 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
2042 nw64(FCRAM_REF_TMR, val);
2043 }
2044
2045 static int fflp_set_partition(struct niu *np, u64 partition,
2046 u64 mask, u64 base, int enable)
2047 {
2048 unsigned long reg;
2049 u64 val;
2050
2051 if (partition >= FCRAM_NUM_PARTITIONS ||
2052 (mask & ~(u64)0x1f) != 0 ||
2053 (base & ~(u64)0x1f) != 0)
2054 return -EINVAL;
2055
2056 reg = FLW_PRT_SEL(partition);
2057
2058 val = nr64(reg);
2059 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
2060 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
2061 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
2062 if (enable)
2063 val |= FLW_PRT_SEL_EXT;
2064 nw64(reg, val);
2065
2066 return 0;
2067 }
2068
2069 static int fflp_disable_all_partitions(struct niu *np)
2070 {
2071 unsigned long i;
2072
2073 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) {
2074 int err = fflp_set_partition(np, 0, 0, 0, 0);
2075 if (err)
2076 return err;
2077 }
2078 return 0;
2079 }
2080
2081 static void fflp_llcsnap_enable(struct niu *np, int on)
2082 {
2083 u64 val = nr64(FFLP_CFG_1);
2084
2085 if (on)
2086 val |= FFLP_CFG_1_LLCSNAP;
2087 else
2088 val &= ~FFLP_CFG_1_LLCSNAP;
2089 nw64(FFLP_CFG_1, val);
2090 }
2091
2092 static void fflp_errors_enable(struct niu *np, int on)
2093 {
2094 u64 val = nr64(FFLP_CFG_1);
2095
2096 if (on)
2097 val &= ~FFLP_CFG_1_ERRORDIS;
2098 else
2099 val |= FFLP_CFG_1_ERRORDIS;
2100 nw64(FFLP_CFG_1, val);
2101 }
2102
2103 static int fflp_hash_clear(struct niu *np)
2104 {
2105 struct fcram_hash_ipv4 ent;
2106 unsigned long i;
2107
2108 /* IPV4 hash entry with valid bit clear, rest is don't care. */
2109 memset(&ent, 0, sizeof(ent));
2110 ent.header = HASH_HEADER_EXT;
2111
2112 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) {
2113 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
2114 if (err)
2115 return err;
2116 }
2117 return 0;
2118 }
2119
2120 static int fflp_early_init(struct niu *np)
2121 {
2122 struct niu_parent *parent;
2123 unsigned long flags;
2124 int err;
2125
2126 niu_lock_parent(np, flags);
2127
2128 parent = np->parent;
2129 err = 0;
2130 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) {
2131 niudbg(PROBE, "fflp_early_init: Initting hw on port %u\n",
2132 np->port);
2133 if (np->parent->plat_type != PLAT_TYPE_NIU) {
2134 fflp_reset(np);
2135 fflp_set_timings(np);
2136 err = fflp_disable_all_partitions(np);
2137 if (err) {
2138 niudbg(PROBE, "fflp_disable_all_partitions "
2139 "failed, err=%d\n", err);
2140 goto out;
2141 }
2142 }
2143
2144 err = tcam_early_init(np);
2145 if (err) {
2146 niudbg(PROBE, "tcam_early_init failed, err=%d\n",
2147 err);
2148 goto out;
2149 }
2150 fflp_llcsnap_enable(np, 1);
2151 fflp_errors_enable(np, 0);
2152 nw64(H1POLY, 0);
2153 nw64(H2POLY, 0);
2154
2155 err = tcam_flush_all(np);
2156 if (err) {
2157 niudbg(PROBE, "tcam_flush_all failed, err=%d\n",
2158 err);
2159 goto out;
2160 }
2161 if (np->parent->plat_type != PLAT_TYPE_NIU) {
2162 err = fflp_hash_clear(np);
2163 if (err) {
2164 niudbg(PROBE, "fflp_hash_clear failed, "
2165 "err=%d\n", err);
2166 goto out;
2167 }
2168 }
2169
2170 vlan_tbl_clear(np);
2171
2172 niudbg(PROBE, "fflp_early_init: Success\n");
2173 parent->flags |= PARENT_FLGS_CLS_HWINIT;
2174 }
2175 out:
2176 niu_unlock_parent(np, flags);
2177 return err;
2178 }
2179
2180 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key)
2181 {
2182 if (class_code < CLASS_CODE_USER_PROG1 ||
2183 class_code > CLASS_CODE_SCTP_IPV6)
2184 return -EINVAL;
2185
2186 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2187 return 0;
2188 }
2189
2190 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key)
2191 {
2192 if (class_code < CLASS_CODE_USER_PROG1 ||
2193 class_code > CLASS_CODE_SCTP_IPV6)
2194 return -EINVAL;
2195
2196 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
2197 return 0;
2198 }
2199
2200 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page,
2201 u32 offset, u32 size)
2202 {
2203 int i = skb_shinfo(skb)->nr_frags;
2204 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2205
2206 frag->page = page;
2207 frag->page_offset = offset;
2208 frag->size = size;
2209
2210 skb->len += size;
2211 skb->data_len += size;
2212 skb->truesize += size;
2213
2214 skb_shinfo(skb)->nr_frags = i + 1;
2215 }
2216
2217 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a)
2218 {
2219 a >>= PAGE_SHIFT;
2220 a ^= (a >> ilog2(MAX_RBR_RING_SIZE));
2221
2222 return (a & (MAX_RBR_RING_SIZE - 1));
2223 }
2224
2225 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr,
2226 struct page ***link)
2227 {
2228 unsigned int h = niu_hash_rxaddr(rp, addr);
2229 struct page *p, **pp;
2230
2231 addr &= PAGE_MASK;
2232 pp = &rp->rxhash[h];
2233 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) {
2234 if (p->index == addr) {
2235 *link = pp;
2236 break;
2237 }
2238 }
2239
2240 return p;
2241 }
2242
2243 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base)
2244 {
2245 unsigned int h = niu_hash_rxaddr(rp, base);
2246
2247 page->index = base;
2248 page->mapping = (struct address_space *) rp->rxhash[h];
2249 rp->rxhash[h] = page;
2250 }
2251
2252 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp,
2253 gfp_t mask, int start_index)
2254 {
2255 struct page *page;
2256 u64 addr;
2257 int i;
2258
2259 page = alloc_page(mask);
2260 if (!page)
2261 return -ENOMEM;
2262
2263 addr = np->ops->map_page(np->device, page, 0,
2264 PAGE_SIZE, DMA_FROM_DEVICE);
2265
2266 niu_hash_page(rp, page, addr);
2267 if (rp->rbr_blocks_per_page > 1)
2268 atomic_add(rp->rbr_blocks_per_page - 1,
2269 &compound_head(page)->_count);
2270
2271 for (i = 0; i < rp->rbr_blocks_per_page; i++) {
2272 __le32 *rbr = &rp->rbr[start_index + i];
2273
2274 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT);
2275 addr += rp->rbr_block_size;
2276 }
2277
2278 return 0;
2279 }
2280
2281 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2282 {
2283 int index = rp->rbr_index;
2284
2285 rp->rbr_pending++;
2286 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) {
2287 int err = niu_rbr_add_page(np, rp, mask, index);
2288
2289 if (unlikely(err)) {
2290 rp->rbr_pending--;
2291 return;
2292 }
2293
2294 rp->rbr_index += rp->rbr_blocks_per_page;
2295 BUG_ON(rp->rbr_index > rp->rbr_table_size);
2296 if (rp->rbr_index == rp->rbr_table_size)
2297 rp->rbr_index = 0;
2298
2299 if (rp->rbr_pending >= rp->rbr_kick_thresh) {
2300 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
2301 rp->rbr_pending = 0;
2302 }
2303 }
2304 }
2305
2306 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp)
2307 {
2308 unsigned int index = rp->rcr_index;
2309 int num_rcr = 0;
2310
2311 rp->rx_dropped++;
2312 while (1) {
2313 struct page *page, **link;
2314 u64 addr, val;
2315 u32 rcr_size;
2316
2317 num_rcr++;
2318
2319 val = le64_to_cpup(&rp->rcr[index]);
2320 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2321 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2322 page = niu_find_rxpage(rp, addr, &link);
2323
2324 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2325 RCR_ENTRY_PKTBUFSZ_SHIFT];
2326 if ((page->index + PAGE_SIZE) - rcr_size == addr) {
2327 *link = (struct page *) page->mapping;
2328 np->ops->unmap_page(np->device, page->index,
2329 PAGE_SIZE, DMA_FROM_DEVICE);
2330 page->index = 0;
2331 page->mapping = NULL;
2332 __free_page(page);
2333 rp->rbr_refill_pending++;
2334 }
2335
2336 index = NEXT_RCR(rp, index);
2337 if (!(val & RCR_ENTRY_MULTI))
2338 break;
2339
2340 }
2341 rp->rcr_index = index;
2342
2343 return num_rcr;
2344 }
2345
2346 static int niu_process_rx_pkt(struct niu *np, struct rx_ring_info *rp)
2347 {
2348 unsigned int index = rp->rcr_index;
2349 struct sk_buff *skb;
2350 int len, num_rcr;
2351
2352 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE);
2353 if (unlikely(!skb))
2354 return niu_rx_pkt_ignore(np, rp);
2355
2356 num_rcr = 0;
2357 while (1) {
2358 struct page *page, **link;
2359 u32 rcr_size, append_size;
2360 u64 addr, val, off;
2361
2362 num_rcr++;
2363
2364 val = le64_to_cpup(&rp->rcr[index]);
2365
2366 len = (val & RCR_ENTRY_L2_LEN) >>
2367 RCR_ENTRY_L2_LEN_SHIFT;
2368 len -= ETH_FCS_LEN;
2369
2370 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
2371 RCR_ENTRY_PKT_BUF_ADDR_SHIFT;
2372 page = niu_find_rxpage(rp, addr, &link);
2373
2374 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
2375 RCR_ENTRY_PKTBUFSZ_SHIFT];
2376
2377 off = addr & ~PAGE_MASK;
2378 append_size = rcr_size;
2379 if (num_rcr == 1) {
2380 int ptype;
2381
2382 off += 2;
2383 append_size -= 2;
2384
2385 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
2386 if ((ptype == RCR_PKT_TYPE_TCP ||
2387 ptype == RCR_PKT_TYPE_UDP) &&
2388 !(val & (RCR_ENTRY_NOPORT |
2389 RCR_ENTRY_ERROR)))
2390 skb->ip_summed = CHECKSUM_UNNECESSARY;
2391 else
2392 skb->ip_summed = CHECKSUM_NONE;
2393 }
2394 if (!(val & RCR_ENTRY_MULTI))
2395 append_size = len - skb->len;
2396
2397 niu_rx_skb_append(skb, page, off, append_size);
2398 if ((page->index + rp->rbr_block_size) - rcr_size == addr) {
2399 *link = (struct page *) page->mapping;
2400 np->ops->unmap_page(np->device, page->index,
2401 PAGE_SIZE, DMA_FROM_DEVICE);
2402 page->index = 0;
2403 page->mapping = NULL;
2404 rp->rbr_refill_pending++;
2405 } else
2406 get_page(page);
2407
2408 index = NEXT_RCR(rp, index);
2409 if (!(val & RCR_ENTRY_MULTI))
2410 break;
2411
2412 }
2413 rp->rcr_index = index;
2414
2415 skb_reserve(skb, NET_IP_ALIGN);
2416 __pskb_pull_tail(skb, min(len, NIU_RXPULL_MAX));
2417
2418 rp->rx_packets++;
2419 rp->rx_bytes += skb->len;
2420
2421 skb->protocol = eth_type_trans(skb, np->dev);
2422 netif_receive_skb(skb);
2423
2424 np->dev->last_rx = jiffies;
2425
2426 return num_rcr;
2427 }
2428
2429 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask)
2430 {
2431 int blocks_per_page = rp->rbr_blocks_per_page;
2432 int err, index = rp->rbr_index;
2433
2434 err = 0;
2435 while (index < (rp->rbr_table_size - blocks_per_page)) {
2436 err = niu_rbr_add_page(np, rp, mask, index);
2437 if (err)
2438 break;
2439
2440 index += blocks_per_page;
2441 }
2442
2443 rp->rbr_index = index;
2444 return err;
2445 }
2446
2447 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp)
2448 {
2449 int i;
2450
2451 for (i = 0; i < MAX_RBR_RING_SIZE; i++) {
2452 struct page *page;
2453
2454 page = rp->rxhash[i];
2455 while (page) {
2456 struct page *next = (struct page *) page->mapping;
2457 u64 base = page->index;
2458
2459 np->ops->unmap_page(np->device, base, PAGE_SIZE,
2460 DMA_FROM_DEVICE);
2461 page->index = 0;
2462 page->mapping = NULL;
2463
2464 __free_page(page);
2465
2466 page = next;
2467 }
2468 }
2469
2470 for (i = 0; i < rp->rbr_table_size; i++)
2471 rp->rbr[i] = cpu_to_le32(0);
2472 rp->rbr_index = 0;
2473 }
2474
2475 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx)
2476 {
2477 struct tx_buff_info *tb = &rp->tx_buffs[idx];
2478 struct sk_buff *skb = tb->skb;
2479 struct tx_pkt_hdr *tp;
2480 u64 tx_flags;
2481 int i, len;
2482
2483 tp = (struct tx_pkt_hdr *) skb->data;
2484 tx_flags = le64_to_cpup(&tp->flags);
2485
2486 rp->tx_packets++;
2487 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) -
2488 ((tx_flags & TXHDR_PAD) / 2));
2489
2490 len = skb_headlen(skb);
2491 np->ops->unmap_single(np->device, tb->mapping,
2492 len, DMA_TO_DEVICE);
2493
2494 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK)
2495 rp->mark_pending--;
2496
2497 tb->skb = NULL;
2498 do {
2499 idx = NEXT_TX(rp, idx);
2500 len -= MAX_TX_DESC_LEN;
2501 } while (len > 0);
2502
2503 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2504 tb = &rp->tx_buffs[idx];
2505 BUG_ON(tb->skb != NULL);
2506 np->ops->unmap_page(np->device, tb->mapping,
2507 skb_shinfo(skb)->frags[i].size,
2508 DMA_TO_DEVICE);
2509 idx = NEXT_TX(rp, idx);
2510 }
2511
2512 dev_kfree_skb(skb);
2513
2514 return idx;
2515 }
2516
2517 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
2518
2519 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp)
2520 {
2521 u16 pkt_cnt, tmp;
2522 int cons;
2523 u64 cs;
2524
2525 cs = rp->tx_cs;
2526 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK))))
2527 goto out;
2528
2529 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT;
2530 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) &
2531 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT);
2532
2533 rp->last_pkt_cnt = tmp;
2534
2535 cons = rp->cons;
2536
2537 niudbg(TX_DONE, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
2538 np->dev->name, pkt_cnt, cons);
2539
2540 while (pkt_cnt--)
2541 cons = release_tx_packet(np, rp, cons);
2542
2543 rp->cons = cons;
2544 smp_mb();
2545
2546 out:
2547 if (unlikely(netif_queue_stopped(np->dev) &&
2548 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) {
2549 netif_tx_lock(np->dev);
2550 if (netif_queue_stopped(np->dev) &&
2551 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))
2552 netif_wake_queue(np->dev);
2553 netif_tx_unlock(np->dev);
2554 }
2555 }
2556
2557 static int niu_rx_work(struct niu *np, struct rx_ring_info *rp, int budget)
2558 {
2559 int qlen, rcr_done = 0, work_done = 0;
2560 struct rxdma_mailbox *mbox = rp->mbox;
2561 u64 stat;
2562
2563 #if 1
2564 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
2565 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
2566 #else
2567 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
2568 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN);
2569 #endif
2570 mbox->rx_dma_ctl_stat = 0;
2571 mbox->rcrstat_a = 0;
2572
2573 niudbg(RX_STATUS, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
2574 np->dev->name, rp->rx_channel, (unsigned long long) stat, qlen);
2575
2576 rcr_done = work_done = 0;
2577 qlen = min(qlen, budget);
2578 while (work_done < qlen) {
2579 rcr_done += niu_process_rx_pkt(np, rp);
2580 work_done++;
2581 }
2582
2583 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) {
2584 unsigned int i;
2585
2586 for (i = 0; i < rp->rbr_refill_pending; i++)
2587 niu_rbr_refill(np, rp, GFP_ATOMIC);
2588 rp->rbr_refill_pending = 0;
2589 }
2590
2591 stat = (RX_DMA_CTL_STAT_MEX |
2592 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) |
2593 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT));
2594
2595 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
2596
2597 return work_done;
2598 }
2599
2600 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget)
2601 {
2602 u64 v0 = lp->v0;
2603 u32 tx_vec = (v0 >> 32);
2604 u32 rx_vec = (v0 & 0xffffffff);
2605 int i, work_done = 0;
2606
2607 niudbg(INTR, "%s: niu_poll_core() v0[%016llx]\n",
2608 np->dev->name, (unsigned long long) v0);
2609
2610 for (i = 0; i < np->num_tx_rings; i++) {
2611 struct tx_ring_info *rp = &np->tx_rings[i];
2612 if (tx_vec & (1 << rp->tx_channel))
2613 niu_tx_work(np, rp);
2614 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
2615 }
2616
2617 for (i = 0; i < np->num_rx_rings; i++) {
2618 struct rx_ring_info *rp = &np->rx_rings[i];
2619
2620 if (rx_vec & (1 << rp->rx_channel)) {
2621 int this_work_done;
2622
2623 this_work_done = niu_rx_work(np, rp,
2624 budget);
2625
2626 budget -= this_work_done;
2627 work_done += this_work_done;
2628 }
2629 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
2630 }
2631
2632 return work_done;
2633 }
2634
2635 static int niu_poll(struct napi_struct *napi, int budget)
2636 {
2637 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi);
2638 struct niu *np = lp->np;
2639 int work_done;
2640
2641 work_done = niu_poll_core(np, lp, budget);
2642
2643 if (work_done < budget) {
2644 netif_rx_complete(np->dev, napi);
2645 niu_ldg_rearm(np, lp, 1);
2646 }
2647 return work_done;
2648 }
2649
2650 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp,
2651 u64 stat)
2652 {
2653 dev_err(np->device, PFX "%s: RX channel %u errors ( ",
2654 np->dev->name, rp->rx_channel);
2655
2656 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT)
2657 printk("RBR_TMOUT ");
2658 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR)
2659 printk("RSP_CNT ");
2660 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS)
2661 printk("BYTE_EN_BUS ");
2662 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR)
2663 printk("RSP_DAT ");
2664 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR)
2665 printk("RCR_ACK ");
2666 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR)
2667 printk("RCR_SHA_PAR ");
2668 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR)
2669 printk("RBR_PRE_PAR ");
2670 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR)
2671 printk("CONFIG ");
2672 if (stat & RX_DMA_CTL_STAT_RCRINCON)
2673 printk("RCRINCON ");
2674 if (stat & RX_DMA_CTL_STAT_RCRFULL)
2675 printk("RCRFULL ");
2676 if (stat & RX_DMA_CTL_STAT_RBRFULL)
2677 printk("RBRFULL ");
2678 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE)
2679 printk("RBRLOGPAGE ");
2680 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE)
2681 printk("CFIGLOGPAGE ");
2682 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR)
2683 printk("DC_FIDO ");
2684
2685 printk(")\n");
2686 }
2687
2688 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp)
2689 {
2690 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
2691 int err = 0;
2692
2693
2694 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL |
2695 RX_DMA_CTL_STAT_PORT_FATAL))
2696 err = -EINVAL;
2697
2698 if (err) {
2699 dev_err(np->device, PFX "%s: RX channel %u error, stat[%llx]\n",
2700 np->dev->name, rp->rx_channel,
2701 (unsigned long long) stat);
2702
2703 niu_log_rxchan_errors(np, rp, stat);
2704 }
2705
2706 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
2707 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS);
2708
2709 return err;
2710 }
2711
2712 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp,
2713 u64 cs)
2714 {
2715 dev_err(np->device, PFX "%s: TX channel %u errors ( ",
2716 np->dev->name, rp->tx_channel);
2717
2718 if (cs & TX_CS_MBOX_ERR)
2719 printk("MBOX ");
2720 if (cs & TX_CS_PKT_SIZE_ERR)
2721 printk("PKT_SIZE ");
2722 if (cs & TX_CS_TX_RING_OFLOW)
2723 printk("TX_RING_OFLOW ");
2724 if (cs & TX_CS_PREF_BUF_PAR_ERR)
2725 printk("PREF_BUF_PAR ");
2726 if (cs & TX_CS_NACK_PREF)
2727 printk("NACK_PREF ");
2728 if (cs & TX_CS_NACK_PKT_RD)
2729 printk("NACK_PKT_RD ");
2730 if (cs & TX_CS_CONF_PART_ERR)
2731 printk("CONF_PART ");
2732 if (cs & TX_CS_PKT_PRT_ERR)
2733 printk("PKT_PTR ");
2734
2735 printk(")\n");
2736 }
2737
2738 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp)
2739 {
2740 u64 cs, logh, logl;
2741
2742 cs = nr64(TX_CS(rp->tx_channel));
2743 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
2744 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
2745
2746 dev_err(np->device, PFX "%s: TX channel %u error, "
2747 "cs[%llx] logh[%llx] logl[%llx]\n",
2748 np->dev->name, rp->tx_channel,
2749 (unsigned long long) cs,
2750 (unsigned long long) logh,
2751 (unsigned long long) logl);
2752
2753 niu_log_txchan_errors(np, rp, cs);
2754
2755 return -ENODEV;
2756 }
2757
2758 static int niu_mif_interrupt(struct niu *np)
2759 {
2760 u64 mif_status = nr64(MIF_STATUS);
2761 int phy_mdint = 0;
2762
2763 if (np->flags & NIU_FLAGS_XMAC) {
2764 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS);
2765
2766 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT)
2767 phy_mdint = 1;
2768 }
2769
2770 dev_err(np->device, PFX "%s: MIF interrupt, "
2771 "stat[%llx] phy_mdint(%d)\n",
2772 np->dev->name, (unsigned long long) mif_status, phy_mdint);
2773
2774 return -ENODEV;
2775 }
2776
2777 static void niu_xmac_interrupt(struct niu *np)
2778 {
2779 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
2780 u64 val;
2781
2782 val = nr64_mac(XTXMAC_STATUS);
2783 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
2784 mp->tx_frames += TXMAC_FRM_CNT_COUNT;
2785 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
2786 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT;
2787 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
2788 mp->tx_fifo_errors++;
2789 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
2790 mp->tx_overflow_errors++;
2791 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
2792 mp->tx_max_pkt_size_errors++;
2793 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
2794 mp->tx_underflow_errors++;
2795
2796 val = nr64_mac(XRXMAC_STATUS);
2797 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
2798 mp->rx_local_faults++;
2799 if (val & XRXMAC_STATUS_RFLT_DET)
2800 mp->rx_remote_faults++;
2801 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
2802 mp->rx_link_faults += LINK_FAULT_CNT_COUNT;
2803 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
2804 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT;
2805 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
2806 mp->rx_frags += RXMAC_FRAG_CNT_COUNT;
2807 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
2808 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT;
2809 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
2810 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
2811 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
2812 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT;
2813 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
2814 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT;
2815 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
2816 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT;
2817 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
2818 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT;
2819 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
2820 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT;
2821 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
2822 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT;
2823 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
2824 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT;
2825 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
2826 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT;
2827 if (val & XRXMAC_STAT_MSK_RXOCTET_CNT_EXP)
2828 mp->rx_octets += RXMAC_BT_CNT_COUNT;
2829 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
2830 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT;
2831 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
2832 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT;
2833 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
2834 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT;
2835 if (val & XRXMAC_STATUS_RXUFLOW)
2836 mp->rx_underflows++;
2837 if (val & XRXMAC_STATUS_RXOFLOW)
2838 mp->rx_overflows++;
2839
2840 val = nr64_mac(XMAC_FC_STAT);
2841 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
2842 mp->pause_off_state++;
2843 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
2844 mp->pause_on_state++;
2845 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
2846 mp->pause_received++;
2847 }
2848
2849 static void niu_bmac_interrupt(struct niu *np)
2850 {
2851 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
2852 u64 val;
2853
2854 val = nr64_mac(BTXMAC_STATUS);
2855 if (val & BTXMAC_STATUS_UNDERRUN)
2856 mp->tx_underflow_errors++;
2857 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
2858 mp->tx_max_pkt_size_errors++;
2859 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
2860 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT;
2861 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
2862 mp->tx_frames += BTXMAC_FRM_CNT_COUNT;
2863
2864 val = nr64_mac(BRXMAC_STATUS);
2865 if (val & BRXMAC_STATUS_OVERFLOW)
2866 mp->rx_overflows++;
2867 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
2868 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT;
2869 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
2870 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
2871 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
2872 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT;
2873 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
2874 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT;
2875
2876 val = nr64_mac(BMAC_CTRL_STATUS);
2877 if (val & BMAC_CTRL_STATUS_NOPAUSE)
2878 mp->pause_off_state++;
2879 if (val & BMAC_CTRL_STATUS_PAUSE)
2880 mp->pause_on_state++;
2881 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
2882 mp->pause_received++;
2883 }
2884
2885 static int niu_mac_interrupt(struct niu *np)
2886 {
2887 if (np->flags & NIU_FLAGS_XMAC)
2888 niu_xmac_interrupt(np);
2889 else
2890 niu_bmac_interrupt(np);
2891
2892 return 0;
2893 }
2894
2895 static void niu_log_device_error(struct niu *np, u64 stat)
2896 {
2897 dev_err(np->device, PFX "%s: Core device errors ( ",
2898 np->dev->name);
2899
2900 if (stat & SYS_ERR_MASK_META2)
2901 printk("META2 ");
2902 if (stat & SYS_ERR_MASK_META1)
2903 printk("META1 ");
2904 if (stat & SYS_ERR_MASK_PEU)
2905 printk("PEU ");
2906 if (stat & SYS_ERR_MASK_TXC)
2907 printk("TXC ");
2908 if (stat & SYS_ERR_MASK_RDMC)
2909 printk("RDMC ");
2910 if (stat & SYS_ERR_MASK_TDMC)
2911 printk("TDMC ");
2912 if (stat & SYS_ERR_MASK_ZCP)
2913 printk("ZCP ");
2914 if (stat & SYS_ERR_MASK_FFLP)
2915 printk("FFLP ");
2916 if (stat & SYS_ERR_MASK_IPP)
2917 printk("IPP ");
2918 if (stat & SYS_ERR_MASK_MAC)
2919 printk("MAC ");
2920 if (stat & SYS_ERR_MASK_SMX)
2921 printk("SMX ");
2922
2923 printk(")\n");
2924 }
2925
2926 static int niu_device_error(struct niu *np)
2927 {
2928 u64 stat = nr64(SYS_ERR_STAT);
2929
2930 dev_err(np->device, PFX "%s: Core device error, stat[%llx]\n",
2931 np->dev->name, (unsigned long long) stat);
2932
2933 niu_log_device_error(np, stat);
2934
2935 return -ENODEV;
2936 }
2937
2938 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp,
2939 u64 v0, u64 v1, u64 v2)
2940 {
2941
2942 int i, err = 0;
2943
2944 lp->v0 = v0;
2945 lp->v1 = v1;
2946 lp->v2 = v2;
2947
2948 if (v1 & 0x00000000ffffffffULL) {
2949 u32 rx_vec = (v1 & 0xffffffff);
2950
2951 for (i = 0; i < np->num_rx_rings; i++) {
2952 struct rx_ring_info *rp = &np->rx_rings[i];
2953
2954 if (rx_vec & (1 << rp->rx_channel)) {
2955 int r = niu_rx_error(np, rp);
2956 if (r) {
2957 err = r;
2958 } else {
2959 if (!v0)
2960 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
2961 RX_DMA_CTL_STAT_MEX);
2962 }
2963 }
2964 }
2965 }
2966 if (v1 & 0x7fffffff00000000ULL) {
2967 u32 tx_vec = (v1 >> 32) & 0x7fffffff;
2968
2969 for (i = 0; i < np->num_tx_rings; i++) {
2970 struct tx_ring_info *rp = &np->tx_rings[i];
2971
2972 if (tx_vec & (1 << rp->tx_channel)) {
2973 int r = niu_tx_error(np, rp);
2974 if (r)
2975 err = r;
2976 }
2977 }
2978 }
2979 if ((v0 | v1) & 0x8000000000000000ULL) {
2980 int r = niu_mif_interrupt(np);
2981 if (r)
2982 err = r;
2983 }
2984 if (v2) {
2985 if (v2 & 0x01ef) {
2986 int r = niu_mac_interrupt(np);
2987 if (r)
2988 err = r;
2989 }
2990 if (v2 & 0x0210) {
2991 int r = niu_device_error(np);
2992 if (r)
2993 err = r;
2994 }
2995 }
2996
2997 if (err)
2998 niu_enable_interrupts(np, 0);
2999
3000 return err;
3001 }
3002
3003 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp,
3004 int ldn)
3005 {
3006 struct rxdma_mailbox *mbox = rp->mbox;
3007 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat);
3008
3009 stat_write = (RX_DMA_CTL_STAT_RCRTHRES |
3010 RX_DMA_CTL_STAT_RCRTO);
3011 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
3012
3013 niudbg(INTR, "%s: rxchan_intr stat[%llx]\n",
3014 np->dev->name, (unsigned long long) stat);
3015 }
3016
3017 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp,
3018 int ldn)
3019 {
3020 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
3021
3022 niudbg(INTR, "%s: txchan_intr cs[%llx]\n",
3023 np->dev->name, (unsigned long long) rp->tx_cs);
3024 }
3025
3026 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0)
3027 {
3028 struct niu_parent *parent = np->parent;
3029 u32 rx_vec, tx_vec;
3030 int i;
3031
3032 tx_vec = (v0 >> 32);
3033 rx_vec = (v0 & 0xffffffff);
3034
3035 for (i = 0; i < np->num_rx_rings; i++) {
3036 struct rx_ring_info *rp = &np->rx_rings[i];
3037 int ldn = LDN_RXDMA(rp->rx_channel);
3038
3039 if (parent->ldg_map[ldn] != ldg)
3040 continue;
3041
3042 nw64(LD_IM0(ldn), LD_IM0_MASK);
3043 if (rx_vec & (1 << rp->rx_channel))
3044 niu_rxchan_intr(np, rp, ldn);
3045 }
3046
3047 for (i = 0; i < np->num_tx_rings; i++) {
3048 struct tx_ring_info *rp = &np->tx_rings[i];
3049 int ldn = LDN_TXDMA(rp->tx_channel);
3050
3051 if (parent->ldg_map[ldn] != ldg)
3052 continue;
3053
3054 nw64(LD_IM0(ldn), LD_IM0_MASK);
3055 if (tx_vec & (1 << rp->tx_channel))
3056 niu_txchan_intr(np, rp, ldn);
3057 }
3058 }
3059
3060 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp,
3061 u64 v0, u64 v1, u64 v2)
3062 {
3063 if (likely(netif_rx_schedule_prep(np->dev, &lp->napi))) {
3064 lp->v0 = v0;
3065 lp->v1 = v1;
3066 lp->v2 = v2;
3067 __niu_fastpath_interrupt(np, lp->ldg_num, v0);
3068 __netif_rx_schedule(np->dev, &lp->napi);
3069 }
3070 }
3071
3072 static irqreturn_t niu_interrupt(int irq, void *dev_id)
3073 {
3074 struct niu_ldg *lp = dev_id;
3075 struct niu *np = lp->np;
3076 int ldg = lp->ldg_num;
3077 unsigned long flags;
3078 u64 v0, v1, v2;
3079
3080 if (netif_msg_intr(np))
3081 printk(KERN_DEBUG PFX "niu_interrupt() ldg[%p](%d) ",
3082 lp, ldg);
3083
3084 spin_lock_irqsave(&np->lock, flags);
3085
3086 v0 = nr64(LDSV0(ldg));
3087 v1 = nr64(LDSV1(ldg));
3088 v2 = nr64(LDSV2(ldg));
3089
3090 if (netif_msg_intr(np))
3091 printk("v0[%llx] v1[%llx] v2[%llx]\n",
3092 (unsigned long long) v0,
3093 (unsigned long long) v1,
3094 (unsigned long long) v2);
3095
3096 if (unlikely(!v0 && !v1 && !v2)) {
3097 spin_unlock_irqrestore(&np->lock, flags);
3098 return IRQ_NONE;
3099 }
3100
3101 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) {
3102 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
3103 if (err)
3104 goto out;
3105 }
3106 if (likely(v0 & ~((u64)1 << LDN_MIF)))
3107 niu_schedule_napi(np, lp, v0, v1, v2);
3108 else
3109 niu_ldg_rearm(np, lp, 1);
3110 out:
3111 spin_unlock_irqrestore(&np->lock, flags);
3112
3113 return IRQ_HANDLED;
3114 }
3115
3116 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp)
3117 {
3118 if (rp->mbox) {
3119 np->ops->free_coherent(np->device,
3120 sizeof(struct rxdma_mailbox),
3121 rp->mbox, rp->mbox_dma);
3122 rp->mbox = NULL;
3123 }
3124 if (rp->rcr) {
3125 np->ops->free_coherent(np->device,
3126 MAX_RCR_RING_SIZE * sizeof(__le64),
3127 rp->rcr, rp->rcr_dma);
3128 rp->rcr = NULL;
3129 rp->rcr_table_size = 0;
3130 rp->rcr_index = 0;
3131 }
3132 if (rp->rbr) {
3133 niu_rbr_free(np, rp);
3134
3135 np->ops->free_coherent(np->device,
3136 MAX_RBR_RING_SIZE * sizeof(__le32),
3137 rp->rbr, rp->rbr_dma);
3138 rp->rbr = NULL;
3139 rp->rbr_table_size = 0;
3140 rp->rbr_index = 0;
3141 }
3142 kfree(rp->rxhash);
3143 rp->rxhash = NULL;
3144 }
3145
3146 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp)
3147 {
3148 if (rp->mbox) {
3149 np->ops->free_coherent(np->device,
3150 sizeof(struct txdma_mailbox),
3151 rp->mbox, rp->mbox_dma);
3152 rp->mbox = NULL;
3153 }
3154 if (rp->descr) {
3155 int i;
3156
3157 for (i = 0; i < MAX_TX_RING_SIZE; i++) {
3158 if (rp->tx_buffs[i].skb)
3159 (void) release_tx_packet(np, rp, i);
3160 }
3161
3162 np->ops->free_coherent(np->device,
3163 MAX_TX_RING_SIZE * sizeof(__le64),
3164 rp->descr, rp->descr_dma);
3165 rp->descr = NULL;
3166 rp->pending = 0;
3167 rp->prod = 0;
3168 rp->cons = 0;
3169 rp->wrap_bit = 0;
3170 }
3171 }
3172
3173 static void niu_free_channels(struct niu *np)
3174 {
3175 int i;
3176
3177 if (np->rx_rings) {
3178 for (i = 0; i < np->num_rx_rings; i++) {
3179 struct rx_ring_info *rp = &np->rx_rings[i];
3180
3181 niu_free_rx_ring_info(np, rp);
3182 }
3183 kfree(np->rx_rings);
3184 np->rx_rings = NULL;
3185 np->num_rx_rings = 0;
3186 }
3187
3188 if (np->tx_rings) {
3189 for (i = 0; i < np->num_tx_rings; i++) {
3190 struct tx_ring_info *rp = &np->tx_rings[i];
3191
3192 niu_free_tx_ring_info(np, rp);
3193 }
3194 kfree(np->tx_rings);
3195 np->tx_rings = NULL;
3196 np->num_tx_rings = 0;
3197 }
3198 }
3199
3200 static int niu_alloc_rx_ring_info(struct niu *np,
3201 struct rx_ring_info *rp)
3202 {
3203 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64);
3204
3205 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *),
3206 GFP_KERNEL);
3207 if (!rp->rxhash)
3208 return -ENOMEM;
3209
3210 rp->mbox = np->ops->alloc_coherent(np->device,
3211 sizeof(struct rxdma_mailbox),
3212 &rp->mbox_dma, GFP_KERNEL);
3213 if (!rp->mbox)
3214 return -ENOMEM;
3215 if ((unsigned long)rp->mbox & (64UL - 1)) {
3216 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3217 "RXDMA mailbox %p\n", np->dev->name, rp->mbox);
3218 return -EINVAL;
3219 }
3220
3221 rp->rcr = np->ops->alloc_coherent(np->device,
3222 MAX_RCR_RING_SIZE * sizeof(__le64),
3223 &rp->rcr_dma, GFP_KERNEL);
3224 if (!rp->rcr)
3225 return -ENOMEM;
3226 if ((unsigned long)rp->rcr & (64UL - 1)) {
3227 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3228 "RXDMA RCR table %p\n", np->dev->name, rp->rcr);
3229 return -EINVAL;
3230 }
3231 rp->rcr_table_size = MAX_RCR_RING_SIZE;
3232 rp->rcr_index = 0;
3233
3234 rp->rbr = np->ops->alloc_coherent(np->device,
3235 MAX_RBR_RING_SIZE * sizeof(__le32),
3236 &rp->rbr_dma, GFP_KERNEL);
3237 if (!rp->rbr)
3238 return -ENOMEM;
3239 if ((unsigned long)rp->rbr & (64UL - 1)) {
3240 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3241 "RXDMA RBR table %p\n", np->dev->name, rp->rbr);
3242 return -EINVAL;
3243 }
3244 rp->rbr_table_size = MAX_RBR_RING_SIZE;
3245 rp->rbr_index = 0;
3246 rp->rbr_pending = 0;
3247
3248 return 0;
3249 }
3250
3251 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp)
3252 {
3253 int mtu = np->dev->mtu;
3254
3255 /* These values are recommended by the HW designers for fair
3256 * utilization of DRR amongst the rings.
3257 */
3258 rp->max_burst = mtu + 32;
3259 if (rp->max_burst > 4096)
3260 rp->max_burst = 4096;
3261 }
3262
3263 static int niu_alloc_tx_ring_info(struct niu *np,
3264 struct tx_ring_info *rp)
3265 {
3266 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64);
3267
3268 rp->mbox = np->ops->alloc_coherent(np->device,
3269 sizeof(struct txdma_mailbox),
3270 &rp->mbox_dma, GFP_KERNEL);
3271 if (!rp->mbox)
3272 return -ENOMEM;
3273 if ((unsigned long)rp->mbox & (64UL - 1)) {
3274 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3275 "TXDMA mailbox %p\n", np->dev->name, rp->mbox);
3276 return -EINVAL;
3277 }
3278
3279 rp->descr = np->ops->alloc_coherent(np->device,
3280 MAX_TX_RING_SIZE * sizeof(__le64),
3281 &rp->descr_dma, GFP_KERNEL);
3282 if (!rp->descr)
3283 return -ENOMEM;
3284 if ((unsigned long)rp->descr & (64UL - 1)) {
3285 dev_err(np->device, PFX "%s: Coherent alloc gives misaligned "
3286 "TXDMA descr table %p\n", np->dev->name, rp->descr);
3287 return -EINVAL;
3288 }
3289
3290 rp->pending = MAX_TX_RING_SIZE;
3291 rp->prod = 0;
3292 rp->cons = 0;
3293 rp->wrap_bit = 0;
3294
3295 /* XXX make these configurable... XXX */
3296 rp->mark_freq = rp->pending / 4;
3297
3298 niu_set_max_burst(np, rp);
3299
3300 return 0;
3301 }
3302
3303 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp)
3304 {
3305 u16 bss;
3306
3307 bss = min(PAGE_SHIFT, 15);
3308
3309 rp->rbr_block_size = 1 << bss;
3310 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss);
3311
3312 rp->rbr_sizes[0] = 256;
3313 rp->rbr_sizes[1] = 1024;
3314 if (np->dev->mtu > ETH_DATA_LEN) {
3315 switch (PAGE_SIZE) {
3316 case 4 * 1024:
3317 rp->rbr_sizes[2] = 4096;
3318 break;
3319
3320 default:
3321 rp->rbr_sizes[2] = 8192;
3322 break;
3323 }
3324 } else {
3325 rp->rbr_sizes[2] = 2048;
3326 }
3327 rp->rbr_sizes[3] = rp->rbr_block_size;
3328 }
3329
3330 static int niu_alloc_channels(struct niu *np)
3331 {
3332 struct niu_parent *parent = np->parent;
3333 int first_rx_channel, first_tx_channel;
3334 int i, port, err;
3335
3336 port = np->port;
3337 first_rx_channel = first_tx_channel = 0;
3338 for (i = 0; i < port; i++) {
3339 first_rx_channel += parent->rxchan_per_port[i];
3340 first_tx_channel += parent->txchan_per_port[i];
3341 }
3342
3343 np->num_rx_rings = parent->rxchan_per_port[port];
3344 np->num_tx_rings = parent->txchan_per_port[port];
3345
3346 np->rx_rings = kzalloc(np->num_rx_rings * sizeof(struct rx_ring_info),
3347 GFP_KERNEL);
3348 err = -ENOMEM;
3349 if (!np->rx_rings)
3350 goto out_err;
3351
3352 for (i = 0; i < np->num_rx_rings; i++) {
3353 struct rx_ring_info *rp = &np->rx_rings[i];
3354
3355 rp->np = np;
3356 rp->rx_channel = first_rx_channel + i;
3357
3358 err = niu_alloc_rx_ring_info(np, rp);
3359 if (err)
3360 goto out_err;
3361
3362 niu_size_rbr(np, rp);
3363
3364 /* XXX better defaults, configurable, etc... XXX */
3365 rp->nonsyn_window = 64;
3366 rp->nonsyn_threshold = rp->rcr_table_size - 64;
3367 rp->syn_window = 64;
3368 rp->syn_threshold = rp->rcr_table_size - 64;
3369 rp->rcr_pkt_threshold = 16;
3370 rp->rcr_timeout = 8;
3371 rp->rbr_kick_thresh = RBR_REFILL_MIN;
3372 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page)
3373 rp->rbr_kick_thresh = rp->rbr_blocks_per_page;
3374
3375 err = niu_rbr_fill(np, rp, GFP_KERNEL);
3376 if (err)
3377 return err;
3378 }
3379
3380 np->tx_rings = kzalloc(np->num_tx_rings * sizeof(struct tx_ring_info),
3381 GFP_KERNEL);
3382 err = -ENOMEM;
3383 if (!np->tx_rings)
3384 goto out_err;
3385
3386 for (i = 0; i < np->num_tx_rings; i++) {
3387 struct tx_ring_info *rp = &np->tx_rings[i];
3388
3389 rp->np = np;
3390 rp->tx_channel = first_tx_channel + i;
3391
3392 err = niu_alloc_tx_ring_info(np, rp);
3393 if (err)
3394 goto out_err;
3395 }
3396
3397 return 0;
3398
3399 out_err:
3400 niu_free_channels(np);
3401 return err;
3402 }
3403
3404 static int niu_tx_cs_sng_poll(struct niu *np, int channel)
3405 {
3406 int limit = 1000;
3407
3408 while (--limit > 0) {
3409 u64 val = nr64(TX_CS(channel));
3410 if (val & TX_CS_SNG_STATE)
3411 return 0;
3412 }
3413 return -ENODEV;
3414 }
3415
3416 static int niu_tx_channel_stop(struct niu *np, int channel)
3417 {
3418 u64 val = nr64(TX_CS(channel));
3419
3420 val |= TX_CS_STOP_N_GO;
3421 nw64(TX_CS(channel), val);
3422
3423 return niu_tx_cs_sng_poll(np, channel);
3424 }
3425
3426 static int niu_tx_cs_reset_poll(struct niu *np, int channel)
3427 {
3428 int limit = 1000;
3429
3430 while (--limit > 0) {
3431 u64 val = nr64(TX_CS(channel));
3432 if (!(val & TX_CS_RST))
3433 return 0;
3434 }
3435 return -ENODEV;
3436 }
3437
3438 static int niu_tx_channel_reset(struct niu *np, int channel)
3439 {
3440 u64 val = nr64(TX_CS(channel));
3441 int err;
3442
3443 val |= TX_CS_RST;
3444 nw64(TX_CS(channel), val);
3445
3446 err = niu_tx_cs_reset_poll(np, channel);
3447 if (!err)
3448 nw64(TX_RING_KICK(channel), 0);
3449
3450 return err;
3451 }
3452
3453 static int niu_tx_channel_lpage_init(struct niu *np, int channel)
3454 {
3455 u64 val;
3456
3457 nw64(TX_LOG_MASK1(channel), 0);
3458 nw64(TX_LOG_VAL1(channel), 0);
3459 nw64(TX_LOG_MASK2(channel), 0);
3460 nw64(TX_LOG_VAL2(channel), 0);
3461 nw64(TX_LOG_PAGE_RELO1(channel), 0);
3462 nw64(TX_LOG_PAGE_RELO2(channel), 0);
3463 nw64(TX_LOG_PAGE_HDL(channel), 0);
3464
3465 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
3466 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
3467 nw64(TX_LOG_PAGE_VLD(channel), val);
3468
3469 /* XXX TXDMA 32bit mode? XXX */
3470
3471 return 0;
3472 }
3473
3474 static void niu_txc_enable_port(struct niu *np, int on)
3475 {
3476 unsigned long flags;
3477 u64 val, mask;
3478
3479 niu_lock_parent(np, flags);
3480 val = nr64(TXC_CONTROL);
3481 mask = (u64)1 << np->port;
3482 if (on) {
3483 val |= TXC_CONTROL_ENABLE | mask;
3484 } else {
3485 val &= ~mask;
3486 if ((val & ~TXC_CONTROL_ENABLE) == 0)
3487 val &= ~TXC_CONTROL_ENABLE;
3488 }
3489 nw64(TXC_CONTROL, val);
3490 niu_unlock_parent(np, flags);
3491 }
3492
3493 static void niu_txc_set_imask(struct niu *np, u64 imask)
3494 {
3495 unsigned long flags;
3496 u64 val;
3497
3498 niu_lock_parent(np, flags);
3499 val = nr64(TXC_INT_MASK);
3500 val &= ~TXC_INT_MASK_VAL(np->port);
3501 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
3502 niu_unlock_parent(np, flags);
3503 }
3504
3505 static void niu_txc_port_dma_enable(struct niu *np, int on)
3506 {
3507 u64 val = 0;
3508
3509 if (on) {
3510 int i;
3511
3512 for (i = 0; i < np->num_tx_rings; i++)
3513 val |= (1 << np->tx_rings[i].tx_channel);
3514 }
3515 nw64(TXC_PORT_DMA(np->port), val);
3516 }
3517
3518 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
3519 {
3520 int err, channel = rp->tx_channel;
3521 u64 val, ring_len;
3522
3523 err = niu_tx_channel_stop(np, channel);
3524 if (err)
3525 return err;
3526
3527 err = niu_tx_channel_reset(np, channel);
3528 if (err)
3529 return err;
3530
3531 err = niu_tx_channel_lpage_init(np, channel);
3532 if (err)
3533 return err;
3534
3535 nw64(TXC_DMA_MAX(channel), rp->max_burst);
3536 nw64(TX_ENT_MSK(channel), 0);
3537
3538 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE |
3539 TX_RNG_CFIG_STADDR)) {
3540 dev_err(np->device, PFX "%s: TX ring channel %d "
3541 "DMA addr (%llx) is not aligned.\n",
3542 np->dev->name, channel,
3543 (unsigned long long) rp->descr_dma);
3544 return -EINVAL;
3545 }
3546
3547 /* The length field in TX_RNG_CFIG is measured in 64-byte
3548 * blocks. rp->pending is the number of TX descriptors in
3549 * our ring, 8 bytes each, thus we divide by 8 bytes more
3550 * to get the proper value the chip wants.
3551 */
3552 ring_len = (rp->pending / 8);
3553
3554 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
3555 rp->descr_dma);
3556 nw64(TX_RNG_CFIG(channel), val);
3557
3558 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) ||
3559 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) {
3560 dev_err(np->device, PFX "%s: TX ring channel %d "
3561 "MBOX addr (%llx) is has illegal bits.\n",
3562 np->dev->name, channel,
3563 (unsigned long long) rp->mbox_dma);
3564 return -EINVAL;
3565 }
3566 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
3567 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
3568
3569 nw64(TX_CS(channel), 0);
3570
3571 rp->last_pkt_cnt = 0;
3572
3573 return 0;
3574 }
3575
3576 static void niu_init_rdc_groups(struct niu *np)
3577 {
3578 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
3579 int i, first_table_num = tp->first_table_num;
3580
3581 for (i = 0; i < tp->num_tables; i++) {
3582 struct rdc_table *tbl = &tp->tables[i];
3583 int this_table = first_table_num + i;
3584 int slot;
3585
3586 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++)
3587 nw64(RDC_TBL(this_table, slot),
3588 tbl->rxdma_channel[slot]);
3589 }
3590
3591 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
3592 }
3593
3594 static void niu_init_drr_weight(struct niu *np)
3595 {
3596 int type = phy_decode(np->parent->port_phy, np->port);
3597 u64 val;
3598
3599 switch (type) {
3600 case PORT_TYPE_10G:
3601 val = PT_DRR_WEIGHT_DEFAULT_10G;
3602 break;
3603
3604 case PORT_TYPE_1G:
3605 default:
3606 val = PT_DRR_WEIGHT_DEFAULT_1G;
3607 break;
3608 }
3609 nw64(PT_DRR_WT(np->port), val);
3610 }
3611
3612 static int niu_init_hostinfo(struct niu *np)
3613 {
3614 struct niu_parent *parent = np->parent;
3615 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
3616 int i, err, num_alt = niu_num_alt_addr(np);
3617 int first_rdc_table = tp->first_table_num;
3618
3619 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
3620 if (err)
3621 return err;
3622
3623 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
3624 if (err)
3625 return err;
3626
3627 for (i = 0; i < num_alt; i++) {
3628 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
3629 if (err)
3630 return err;
3631 }
3632
3633 return 0;
3634 }
3635
3636 static int niu_rx_channel_reset(struct niu *np, int channel)
3637 {
3638 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel),
3639 RXDMA_CFIG1_RST, 1000, 10,
3640 "RXDMA_CFIG1");
3641 }
3642
3643 static int niu_rx_channel_lpage_init(struct niu *np, int channel)
3644 {
3645 u64 val;
3646
3647 nw64(RX_LOG_MASK1(channel), 0);
3648 nw64(RX_LOG_VAL1(channel), 0);
3649 nw64(RX_LOG_MASK2(channel), 0);
3650 nw64(RX_LOG_VAL2(channel), 0);
3651 nw64(RX_LOG_PAGE_RELO1(channel), 0);
3652 nw64(RX_LOG_PAGE_RELO2(channel), 0);
3653 nw64(RX_LOG_PAGE_HDL(channel), 0);
3654
3655 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
3656 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
3657 nw64(RX_LOG_PAGE_VLD(channel), val);
3658
3659 return 0;
3660 }
3661
3662 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp)
3663 {
3664 u64 val;
3665
3666 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
3667 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) |
3668 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) |
3669 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT));
3670 nw64(RDC_RED_PARA(rp->rx_channel), val);
3671 }
3672
3673 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret)
3674 {
3675 u64 val = 0;
3676
3677 switch (rp->rbr_block_size) {
3678 case 4 * 1024:
3679 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
3680 break;
3681 case 8 * 1024:
3682 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
3683 break;
3684 case 16 * 1024:
3685 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
3686 break;
3687 case 32 * 1024:
3688 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
3689 break;
3690 default:
3691 return -EINVAL;
3692 }
3693 val |= RBR_CFIG_B_VLD2;
3694 switch (rp->rbr_sizes[2]) {
3695 case 2 * 1024:
3696 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
3697 break;
3698 case 4 * 1024:
3699 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
3700 break;
3701 case 8 * 1024:
3702 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
3703 break;
3704 case 16 * 1024:
3705 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
3706 break;
3707
3708 default:
3709 return -EINVAL;
3710 }
3711 val |= RBR_CFIG_B_VLD1;
3712 switch (rp->rbr_sizes[1]) {
3713 case 1 * 1024:
3714 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
3715 break;
3716 case 2 * 1024:
3717 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
3718 break;
3719 case 4 * 1024:
3720 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
3721 break;
3722 case 8 * 1024:
3723 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
3724 break;
3725
3726 default:
3727 return -EINVAL;
3728 }
3729 val |= RBR_CFIG_B_VLD0;
3730 switch (rp->rbr_sizes[0]) {
3731 case 256:
3732 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
3733 break;
3734 case 512:
3735 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
3736 break;
3737 case 1 * 1024:
3738 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
3739 break;
3740 case 2 * 1024:
3741 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
3742 break;
3743
3744 default:
3745 return -EINVAL;
3746 }
3747
3748 *ret = val;
3749 return 0;
3750 }
3751
3752 static int niu_enable_rx_channel(struct niu *np, int channel, int on)
3753 {
3754 u64 val = nr64(RXDMA_CFIG1(channel));
3755 int limit;
3756
3757 if (on)
3758 val |= RXDMA_CFIG1_EN;
3759 else
3760 val &= ~RXDMA_CFIG1_EN;
3761 nw64(RXDMA_CFIG1(channel), val);
3762
3763 limit = 1000;
3764 while (--limit > 0) {
3765 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
3766 break;
3767 udelay(10);
3768 }
3769 if (limit <= 0)
3770 return -ENODEV;
3771 return 0;
3772 }
3773
3774 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
3775 {
3776 int err, channel = rp->rx_channel;
3777 u64 val;
3778
3779 err = niu_rx_channel_reset(np, channel);
3780 if (err)
3781 return err;
3782
3783 err = niu_rx_channel_lpage_init(np, channel);
3784 if (err)
3785 return err;
3786
3787 niu_rx_channel_wred_init(np, rp);
3788
3789 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
3790 nw64(RX_DMA_CTL_STAT(channel),
3791 (RX_DMA_CTL_STAT_MEX |
3792 RX_DMA_CTL_STAT_RCRTHRES |
3793 RX_DMA_CTL_STAT_RCRTO |
3794 RX_DMA_CTL_STAT_RBR_EMPTY));
3795 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
3796 nw64(RXDMA_CFIG2(channel), (rp->mbox_dma & 0x00000000ffffffc0));
3797 nw64(RBR_CFIG_A(channel),
3798 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) |
3799 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR)));
3800 err = niu_compute_rbr_cfig_b(rp, &val);
3801 if (err)
3802 return err;
3803 nw64(RBR_CFIG_B(channel), val);
3804 nw64(RCRCFIG_A(channel),
3805 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) |
3806 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR)));
3807 nw64(RCRCFIG_B(channel),
3808 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) |
3809 RCRCFIG_B_ENTOUT |
3810 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT));
3811
3812 err = niu_enable_rx_channel(np, channel, 1);
3813 if (err)
3814 return err;
3815
3816 nw64(RBR_KICK(channel), rp->rbr_index);
3817
3818 val = nr64(RX_DMA_CTL_STAT(channel));
3819 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
3820 nw64(RX_DMA_CTL_STAT(channel), val);
3821
3822 return 0;
3823 }
3824
3825 static int niu_init_rx_channels(struct niu *np)
3826 {
3827 unsigned long flags;
3828 u64 seed = jiffies_64;
3829 int err, i;
3830
3831 niu_lock_parent(np, flags);
3832 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
3833 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
3834 niu_unlock_parent(np, flags);
3835
3836 /* XXX RXDMA 32bit mode? XXX */
3837
3838 niu_init_rdc_groups(np);
3839 niu_init_drr_weight(np);
3840
3841 err = niu_init_hostinfo(np);
3842 if (err)
3843 return err;
3844
3845 for (i = 0; i < np->num_rx_rings; i++) {
3846 struct rx_ring_info *rp = &np->rx_rings[i];
3847
3848 err = niu_init_one_rx_channel(np, rp);
3849 if (err)
3850 return err;
3851 }
3852
3853 return 0;
3854 }
3855
3856 static int niu_set_ip_frag_rule(struct niu *np)
3857 {
3858 struct niu_parent *parent = np->parent;
3859 struct niu_classifier *cp = &np->clas;
3860 struct niu_tcam_entry *tp;
3861 int index, err;
3862
3863 /* XXX fix this allocation scheme XXX */
3864 index = cp->tcam_index;
3865 tp = &parent->tcam[index];
3866
3867 /* Note that the noport bit is the same in both ipv4 and
3868 * ipv6 format TCAM entries.
3869 */
3870 memset(tp, 0, sizeof(*tp));
3871 tp->key[1] = TCAM_V4KEY1_NOPORT;
3872 tp->key_mask[1] = TCAM_V4KEY1_NOPORT;
3873 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET |
3874 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT));
3875 err = tcam_write(np, index, tp->key, tp->key_mask);
3876 if (err)
3877 return err;
3878 err = tcam_assoc_write(np, index, tp->assoc_data);
3879 if (err)
3880 return err;
3881
3882 return 0;
3883 }
3884
3885 static int niu_init_classifier_hw(struct niu *np)
3886 {
3887 struct niu_parent *parent = np->parent;
3888 struct niu_classifier *cp = &np->clas;
3889 int i, err;
3890
3891 nw64(H1POLY, cp->h1_init);
3892 nw64(H2POLY, cp->h2_init);
3893
3894 err = niu_init_hostinfo(np);
3895 if (err)
3896 return err;
3897
3898 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) {
3899 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i];
3900
3901 vlan_tbl_write(np, i, np->port,
3902 vp->vlan_pref, vp->rdc_num);
3903 }
3904
3905 for (i = 0; i < cp->num_alt_mac_mappings; i++) {
3906 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i];
3907
3908 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
3909 ap->rdc_num, ap->mac_pref);
3910 if (err)
3911 return err;
3912 }
3913
3914 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
3915 int index = i - CLASS_CODE_USER_PROG1;
3916
3917 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
3918 if (err)
3919 return err;
3920 err = niu_set_flow_key(np, i, parent->flow_key[index]);
3921 if (err)
3922 return err;
3923 }
3924
3925 err = niu_set_ip_frag_rule(np);
3926 if (err)
3927 return err;
3928
3929 tcam_enable(np, 1);
3930
3931 return 0;
3932 }
3933
3934 static int niu_zcp_write(struct niu *np, int index, u64 *data)
3935 {
3936 nw64(ZCP_RAM_DATA0, data[0]);
3937 nw64(ZCP_RAM_DATA1, data[1]);
3938 nw64(ZCP_RAM_DATA2, data[2]);
3939 nw64(ZCP_RAM_DATA3, data[3]);
3940 nw64(ZCP_RAM_DATA4, data[4]);
3941 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
3942 nw64(ZCP_RAM_ACC,
3943 (ZCP_RAM_ACC_WRITE |
3944 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
3945 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
3946
3947 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3948 1000, 100);
3949 }
3950
3951 static int niu_zcp_read(struct niu *np, int index, u64 *data)
3952 {
3953 int err;
3954
3955 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3956 1000, 100);
3957 if (err) {
3958 dev_err(np->device, PFX "%s: ZCP read busy won't clear, "
3959 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
3960 (unsigned long long) nr64(ZCP_RAM_ACC));
3961 return err;
3962 }
3963
3964 nw64(ZCP_RAM_ACC,
3965 (ZCP_RAM_ACC_READ |
3966 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) |
3967 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
3968
3969 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
3970 1000, 100);
3971 if (err) {
3972 dev_err(np->device, PFX "%s: ZCP read busy2 won't clear, "
3973 "ZCP_RAM_ACC[%llx]\n", np->dev->name,
3974 (unsigned long long) nr64(ZCP_RAM_ACC));
3975 return err;
3976 }
3977
3978 data[0] = nr64(ZCP_RAM_DATA0);
3979 data[1] = nr64(ZCP_RAM_DATA1);
3980 data[2] = nr64(ZCP_RAM_DATA2);
3981 data[3] = nr64(ZCP_RAM_DATA3);
3982 data[4] = nr64(ZCP_RAM_DATA4);
3983
3984 return 0;
3985 }
3986
3987 static void niu_zcp_cfifo_reset(struct niu *np)
3988 {
3989 u64 val = nr64(RESET_CFIFO);
3990
3991 val |= RESET_CFIFO_RST(np->port);
3992 nw64(RESET_CFIFO, val);
3993 udelay(10);
3994
3995 val &= ~RESET_CFIFO_RST(np->port);
3996 nw64(RESET_CFIFO, val);
3997 }
3998
3999 static int niu_init_zcp(struct niu *np)
4000 {
4001 u64 data[5], rbuf[5];
4002 int i, max, err;
4003
4004 if (np->parent->plat_type != PLAT_TYPE_NIU) {
4005 if (np->port == 0 || np->port == 1)
4006 max = ATLAS_P0_P1_CFIFO_ENTRIES;
4007 else
4008 max = ATLAS_P2_P3_CFIFO_ENTRIES;
4009 } else
4010 max = NIU_CFIFO_ENTRIES;
4011
4012 data[0] = 0;
4013 data[1] = 0;
4014 data[2] = 0;
4015 data[3] = 0;
4016 data[4] = 0;
4017
4018 for (i = 0; i < max; i++) {
4019 err = niu_zcp_write(np, i, data);
4020 if (err)
4021 return err;
4022 err = niu_zcp_read(np, i, rbuf);
4023 if (err)
4024 return err;
4025 }
4026
4027 niu_zcp_cfifo_reset(np);
4028 nw64(CFIFO_ECC(np->port), 0);
4029 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
4030 (void) nr64(ZCP_INT_STAT);
4031 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
4032
4033 return 0;
4034 }
4035
4036 static void niu_ipp_write(struct niu *np, int index, u64 *data)
4037 {
4038 u64 val = nr64_ipp(IPP_CFIG);
4039
4040 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
4041 nw64_ipp(IPP_DFIFO_WR_PTR, index);
4042 nw64_ipp(IPP_DFIFO_WR0, data[0]);
4043 nw64_ipp(IPP_DFIFO_WR1, data[1]);
4044 nw64_ipp(IPP_DFIFO_WR2, data[2]);
4045 nw64_ipp(IPP_DFIFO_WR3, data[3]);
4046 nw64_ipp(IPP_DFIFO_WR4, data[4]);
4047 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
4048 }
4049
4050 static void niu_ipp_read(struct niu *np, int index, u64 *data)
4051 {
4052 nw64_ipp(IPP_DFIFO_RD_PTR, index);
4053 data[0] = nr64_ipp(IPP_DFIFO_RD0);
4054 data[1] = nr64_ipp(IPP_DFIFO_RD1);
4055 data[2] = nr64_ipp(IPP_DFIFO_RD2);
4056 data[3] = nr64_ipp(IPP_DFIFO_RD3);
4057 data[4] = nr64_ipp(IPP_DFIFO_RD4);
4058 }
4059
4060 static int niu_ipp_reset(struct niu *np)
4061 {
4062 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST,
4063 1000, 100, "IPP_CFIG");
4064 }
4065
4066 static int niu_init_ipp(struct niu *np)
4067 {
4068 u64 data[5], rbuf[5], val;
4069 int i, max, err;
4070
4071 if (np->parent->plat_type != PLAT_TYPE_NIU) {
4072 if (np->port == 0 || np->port == 1)
4073 max = ATLAS_P0_P1_DFIFO_ENTRIES;
4074 else
4075 max = ATLAS_P2_P3_DFIFO_ENTRIES;
4076 } else
4077 max = NIU_DFIFO_ENTRIES;
4078
4079 data[0] = 0;
4080 data[1] = 0;
4081 data[2] = 0;
4082 data[3] = 0;
4083 data[4] = 0;
4084
4085 for (i = 0; i < max; i++) {
4086 niu_ipp_write(np, i, data);
4087 niu_ipp_read(np, i, rbuf);
4088 }
4089
4090 (void) nr64_ipp(IPP_INT_STAT);
4091 (void) nr64_ipp(IPP_INT_STAT);
4092
4093 err = niu_ipp_reset(np);
4094 if (err)
4095 return err;
4096
4097 (void) nr64_ipp(IPP_PKT_DIS);
4098 (void) nr64_ipp(IPP_BAD_CS_CNT);
4099 (void) nr64_ipp(IPP_ECC);
4100
4101 (void) nr64_ipp(IPP_INT_STAT);
4102
4103 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL);
4104
4105 val = nr64_ipp(IPP_CFIG);
4106 val &= ~IPP_CFIG_IP_MAX_PKT;
4107 val |= (IPP_CFIG_IPP_ENABLE |
4108 IPP_CFIG_DFIFO_ECC_EN |
4109 IPP_CFIG_DROP_BAD_CRC |
4110 IPP_CFIG_CKSUM_EN |
4111 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT));
4112 nw64_ipp(IPP_CFIG, val);
4113
4114 return 0;
4115 }
4116
4117 static void niu_handle_led(struct niu *np, int status)
4118 {
4119 u64 val;
4120 val = nr64_mac(XMAC_CONFIG);
4121
4122 if ((np->flags & NIU_FLAGS_10G) != 0 &&
4123 (np->flags & NIU_FLAGS_FIBER) != 0) {
4124 if (status) {
4125 val |= XMAC_CONFIG_LED_POLARITY;
4126 val &= ~XMAC_CONFIG_FORCE_LED_ON;
4127 } else {
4128 val |= XMAC_CONFIG_FORCE_LED_ON;
4129 val &= ~XMAC_CONFIG_LED_POLARITY;
4130 }
4131 }
4132
4133 nw64_mac(XMAC_CONFIG, val);
4134 }
4135
4136 static void niu_init_xif_xmac(struct niu *np)
4137 {
4138 struct niu_link_config *lp = &np->link_config;
4139 u64 val;
4140
4141 val = nr64_mac(XMAC_CONFIG);
4142 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
4143
4144 val |= XMAC_CONFIG_TX_OUTPUT_EN;
4145
4146 if (lp->loopback_mode == LOOPBACK_MAC) {
4147 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
4148 val |= XMAC_CONFIG_LOOPBACK;
4149 } else {
4150 val &= ~XMAC_CONFIG_LOOPBACK;
4151 }
4152
4153 if (np->flags & NIU_FLAGS_10G) {
4154 val &= ~XMAC_CONFIG_LFS_DISABLE;
4155 } else {
4156 val |= XMAC_CONFIG_LFS_DISABLE;
4157 if (!(np->flags & NIU_FLAGS_FIBER))
4158 val |= XMAC_CONFIG_1G_PCS_BYPASS;
4159 else
4160 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
4161 }
4162
4163 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
4164
4165 if (lp->active_speed == SPEED_100)
4166 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
4167 else
4168 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
4169
4170 nw64_mac(XMAC_CONFIG, val);
4171
4172 val = nr64_mac(XMAC_CONFIG);
4173 val &= ~XMAC_CONFIG_MODE_MASK;
4174 if (np->flags & NIU_FLAGS_10G) {
4175 val |= XMAC_CONFIG_MODE_XGMII;
4176 } else {
4177 if (lp->active_speed == SPEED_100)
4178 val |= XMAC_CONFIG_MODE_MII;
4179 else
4180 val |= XMAC_CONFIG_MODE_GMII;
4181 }
4182
4183 nw64_mac(XMAC_CONFIG, val);
4184 }
4185
4186 static void niu_init_xif_bmac(struct niu *np)
4187 {
4188 struct niu_link_config *lp = &np->link_config;
4189 u64 val;
4190
4191 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
4192
4193 if (lp->loopback_mode == LOOPBACK_MAC)
4194 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
4195 else
4196 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
4197
4198 if (lp->active_speed == SPEED_1000)
4199 val |= BMAC_XIF_CONFIG_GMII_MODE;
4200 else
4201 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
4202
4203 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
4204 BMAC_XIF_CONFIG_LED_POLARITY);
4205
4206 if (!(np->flags & NIU_FLAGS_10G) &&
4207 !(np->flags & NIU_FLAGS_FIBER) &&
4208 lp->active_speed == SPEED_100)
4209 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
4210 else
4211 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
4212
4213 nw64_mac(BMAC_XIF_CONFIG, val);
4214 }
4215
4216 static void niu_init_xif(struct niu *np)
4217 {
4218 if (np->flags & NIU_FLAGS_XMAC)
4219 niu_init_xif_xmac(np);
4220 else
4221 niu_init_xif_bmac(np);
4222 }
4223
4224 static void niu_pcs_mii_reset(struct niu *np)
4225 {
4226 u64 val = nr64_pcs(PCS_MII_CTL);
4227 val |= PCS_MII_CTL_RST;
4228 nw64_pcs(PCS_MII_CTL, val);
4229 }
4230
4231 static void niu_xpcs_reset(struct niu *np)
4232 {
4233 u64 val = nr64_xpcs(XPCS_CONTROL1);
4234 val |= XPCS_CONTROL1_RESET;
4235 nw64_xpcs(XPCS_CONTROL1, val);
4236 }
4237
4238 static int niu_init_pcs(struct niu *np)
4239 {
4240 struct niu_link_config *lp = &np->link_config;
4241 u64 val;
4242
4243 switch (np->flags & (NIU_FLAGS_10G | NIU_FLAGS_FIBER)) {
4244 case NIU_FLAGS_FIBER:
4245 /* 1G fiber */
4246 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE);
4247 nw64_pcs(PCS_DPATH_MODE, 0);
4248 niu_pcs_mii_reset(np);
4249 break;
4250
4251 case NIU_FLAGS_10G:
4252 case NIU_FLAGS_10G | NIU_FLAGS_FIBER:
4253 if (!(np->flags & NIU_FLAGS_XMAC))
4254 return -EINVAL;
4255
4256 /* 10G copper or fiber */
4257 val = nr64_mac(XMAC_CONFIG);
4258 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
4259 nw64_mac(XMAC_CONFIG, val);
4260
4261 niu_xpcs_reset(np);
4262
4263 val = nr64_xpcs(XPCS_CONTROL1);
4264 if (lp->loopback_mode == LOOPBACK_PHY)
4265 val |= XPCS_CONTROL1_LOOPBACK;
4266 else
4267 val &= ~XPCS_CONTROL1_LOOPBACK;
4268 nw64_xpcs(XPCS_CONTROL1, val);
4269
4270 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0);
4271 (void) nr64_xpcs(XPCS_SYMERR_CNT01);
4272 (void) nr64_xpcs(XPCS_SYMERR_CNT23);
4273 break;
4274
4275 case 0:
4276 /* 1G copper */
4277 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII);
4278 niu_pcs_mii_reset(np);
4279 break;
4280
4281 default:
4282 return -EINVAL;
4283 }
4284
4285 return 0;
4286 }
4287
4288 static int niu_reset_tx_xmac(struct niu *np)
4289 {
4290 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST,
4291 (XTXMAC_SW_RST_REG_RS |
4292 XTXMAC_SW_RST_SOFT_RST),
4293 1000, 100, "XTXMAC_SW_RST");
4294 }
4295
4296 static int niu_reset_tx_bmac(struct niu *np)
4297 {
4298 int limit;
4299
4300 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET);
4301 limit = 1000;
4302 while (--limit >= 0) {
4303 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET))
4304 break;
4305 udelay(100);
4306 }
4307 if (limit < 0) {
4308 dev_err(np->device, PFX "Port %u TX BMAC would not reset, "
4309 "BTXMAC_SW_RST[%llx]\n",
4310 np->port,
4311 (unsigned long long) nr64_mac(BTXMAC_SW_RST));
4312 return -ENODEV;
4313 }
4314
4315 return 0;
4316 }
4317
4318 static int niu_reset_tx_mac(struct niu *np)
4319 {
4320 if (np->flags & NIU_FLAGS_XMAC)
4321 return niu_reset_tx_xmac(np);
4322 else
4323 return niu_reset_tx_bmac(np);
4324 }
4325
4326 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max)
4327 {
4328 u64 val;
4329
4330 val = nr64_mac(XMAC_MIN);
4331 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
4332 XMAC_MIN_RX_MIN_PKT_SIZE);
4333 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
4334 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
4335 nw64_mac(XMAC_MIN, val);
4336
4337 nw64_mac(XMAC_MAX, max);
4338
4339 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0);
4340
4341 val = nr64_mac(XMAC_IPG);
4342 if (np->flags & NIU_FLAGS_10G) {
4343 val &= ~XMAC_IPG_IPG_XGMII;
4344 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
4345 } else {
4346 val &= ~XMAC_IPG_IPG_MII_GMII;
4347 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
4348 }
4349 nw64_mac(XMAC_IPG, val);
4350
4351 val = nr64_mac(XMAC_CONFIG);
4352 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
4353 XMAC_CONFIG_STRETCH_MODE |
4354 XMAC_CONFIG_VAR_MIN_IPG_EN |
4355 XMAC_CONFIG_TX_ENABLE);
4356 nw64_mac(XMAC_CONFIG, val);
4357
4358 nw64_mac(TXMAC_FRM_CNT, 0);
4359 nw64_mac(TXMAC_BYTE_CNT, 0);
4360 }
4361
4362 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max)
4363 {
4364 u64 val;
4365
4366 nw64_mac(BMAC_MIN_FRAME, min);
4367 nw64_mac(BMAC_MAX_FRAME, max);
4368
4369 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0);
4370 nw64_mac(BMAC_CTRL_TYPE, 0x8808);
4371 nw64_mac(BMAC_PREAMBLE_SIZE, 7);
4372
4373 val = nr64_mac(BTXMAC_CONFIG);
4374 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
4375 BTXMAC_CONFIG_ENABLE);
4376 nw64_mac(BTXMAC_CONFIG, val);
4377 }
4378
4379 static void niu_init_tx_mac(struct niu *np)
4380 {
4381 u64 min, max;
4382
4383 min = 64;
4384 if (np->dev->mtu > ETH_DATA_LEN)
4385 max = 9216;
4386 else
4387 max = 1522;
4388
4389 /* The XMAC_MIN register only accepts values for TX min which
4390 * have the low 3 bits cleared.
4391 */
4392 BUILD_BUG_ON(min & 0x7);
4393
4394 if (np->flags & NIU_FLAGS_XMAC)
4395 niu_init_tx_xmac(np, min, max);
4396 else
4397 niu_init_tx_bmac(np, min, max);
4398 }
4399
4400 static int niu_reset_rx_xmac(struct niu *np)
4401 {
4402 int limit;
4403
4404 nw64_mac(XRXMAC_SW_RST,
4405 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST);
4406 limit = 1000;
4407 while (--limit >= 0) {
4408 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS |
4409 XRXMAC_SW_RST_SOFT_RST)))
4410 break;
4411 udelay(100);
4412 }
4413 if (limit < 0) {
4414 dev_err(np->device, PFX "Port %u RX XMAC would not reset, "
4415 "XRXMAC_SW_RST[%llx]\n",
4416 np->port,
4417 (unsigned long long) nr64_mac(XRXMAC_SW_RST));
4418 return -ENODEV;
4419 }
4420
4421 return 0;
4422 }
4423
4424 static int niu_reset_rx_bmac(struct niu *np)
4425 {
4426 int limit;
4427
4428 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET);
4429 limit = 1000;
4430 while (--limit >= 0) {
4431 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET))
4432 break;
4433 udelay(100);
4434 }
4435 if (limit < 0) {
4436 dev_err(np->device, PFX "Port %u RX BMAC would not reset, "
4437 "BRXMAC_SW_RST[%llx]\n",
4438 np->port,
4439 (unsigned long long) nr64_mac(BRXMAC_SW_RST));
4440 return -ENODEV;
4441 }
4442
4443 return 0;
4444 }
4445
4446 static int niu_reset_rx_mac(struct niu *np)
4447 {
4448 if (np->flags & NIU_FLAGS_XMAC)
4449 return niu_reset_rx_xmac(np);
4450 else
4451 return niu_reset_rx_bmac(np);
4452 }
4453
4454 static void niu_init_rx_xmac(struct niu *np)
4455 {
4456 struct niu_parent *parent = np->parent;
4457 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4458 int first_rdc_table = tp->first_table_num;
4459 unsigned long i;
4460 u64 val;
4461
4462 nw64_mac(XMAC_ADD_FILT0, 0);
4463 nw64_mac(XMAC_ADD_FILT1, 0);
4464 nw64_mac(XMAC_ADD_FILT2, 0);
4465 nw64_mac(XMAC_ADD_FILT12_MASK, 0);
4466 nw64_mac(XMAC_ADD_FILT00_MASK, 0);
4467 for (i = 0; i < MAC_NUM_HASH; i++)
4468 nw64_mac(XMAC_HASH_TBL(i), 0);
4469 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0);
4470 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4471 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4472
4473 val = nr64_mac(XMAC_CONFIG);
4474 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
4475 XMAC_CONFIG_PROMISCUOUS |
4476 XMAC_CONFIG_PROMISC_GROUP |
4477 XMAC_CONFIG_ERR_CHK_DIS |
4478 XMAC_CONFIG_RX_CRC_CHK_DIS |
4479 XMAC_CONFIG_RESERVED_MULTICAST |
4480 XMAC_CONFIG_RX_CODEV_CHK_DIS |
4481 XMAC_CONFIG_ADDR_FILTER_EN |
4482 XMAC_CONFIG_RCV_PAUSE_ENABLE |
4483 XMAC_CONFIG_STRIP_CRC |
4484 XMAC_CONFIG_PASS_FLOW_CTRL |
4485 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN);
4486 val |= (XMAC_CONFIG_HASH_FILTER_EN);
4487 nw64_mac(XMAC_CONFIG, val);
4488
4489 nw64_mac(RXMAC_BT_CNT, 0);
4490 nw64_mac(RXMAC_BC_FRM_CNT, 0);
4491 nw64_mac(RXMAC_MC_FRM_CNT, 0);
4492 nw64_mac(RXMAC_FRAG_CNT, 0);
4493 nw64_mac(RXMAC_HIST_CNT1, 0);
4494 nw64_mac(RXMAC_HIST_CNT2, 0);
4495 nw64_mac(RXMAC_HIST_CNT3, 0);
4496 nw64_mac(RXMAC_HIST_CNT4, 0);
4497 nw64_mac(RXMAC_HIST_CNT5, 0);
4498 nw64_mac(RXMAC_HIST_CNT6, 0);
4499 nw64_mac(RXMAC_HIST_CNT7, 0);
4500 nw64_mac(RXMAC_MPSZER_CNT, 0);
4501 nw64_mac(RXMAC_CRC_ER_CNT, 0);
4502 nw64_mac(RXMAC_CD_VIO_CNT, 0);
4503 nw64_mac(LINK_FAULT_CNT, 0);
4504 }
4505
4506 static void niu_init_rx_bmac(struct niu *np)
4507 {
4508 struct niu_parent *parent = np->parent;
4509 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4510 int first_rdc_table = tp->first_table_num;
4511 unsigned long i;
4512 u64 val;
4513
4514 nw64_mac(BMAC_ADD_FILT0, 0);
4515 nw64_mac(BMAC_ADD_FILT1, 0);
4516 nw64_mac(BMAC_ADD_FILT2, 0);
4517 nw64_mac(BMAC_ADD_FILT12_MASK, 0);
4518 nw64_mac(BMAC_ADD_FILT00_MASK, 0);
4519 for (i = 0; i < MAC_NUM_HASH; i++)
4520 nw64_mac(BMAC_HASH_TBL(i), 0);
4521 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4522 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4523 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0);
4524
4525 val = nr64_mac(BRXMAC_CONFIG);
4526 val &= ~(BRXMAC_CONFIG_ENABLE |
4527 BRXMAC_CONFIG_STRIP_PAD |
4528 BRXMAC_CONFIG_STRIP_FCS |
4529 BRXMAC_CONFIG_PROMISC |
4530 BRXMAC_CONFIG_PROMISC_GRP |
4531 BRXMAC_CONFIG_ADDR_FILT_EN |
4532 BRXMAC_CONFIG_DISCARD_DIS);
4533 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
4534 nw64_mac(BRXMAC_CONFIG, val);
4535
4536 val = nr64_mac(BMAC_ADDR_CMPEN);
4537 val |= BMAC_ADDR_CMPEN_EN0;
4538 nw64_mac(BMAC_ADDR_CMPEN, val);
4539 }
4540
4541 static void niu_init_rx_mac(struct niu *np)
4542 {
4543 niu_set_primary_mac(np, np->dev->dev_addr);
4544
4545 if (np->flags & NIU_FLAGS_XMAC)
4546 niu_init_rx_xmac(np);
4547 else
4548 niu_init_rx_bmac(np);
4549 }
4550
4551 static void niu_enable_tx_xmac(struct niu *np, int on)
4552 {
4553 u64 val = nr64_mac(XMAC_CONFIG);
4554
4555 if (on)
4556 val |= XMAC_CONFIG_TX_ENABLE;
4557 else
4558 val &= ~XMAC_CONFIG_TX_ENABLE;
4559 nw64_mac(XMAC_CONFIG, val);
4560 }
4561
4562 static void niu_enable_tx_bmac(struct niu *np, int on)
4563 {
4564 u64 val = nr64_mac(BTXMAC_CONFIG);
4565
4566 if (on)
4567 val |= BTXMAC_CONFIG_ENABLE;
4568 else
4569 val &= ~BTXMAC_CONFIG_ENABLE;
4570 nw64_mac(BTXMAC_CONFIG, val);
4571 }
4572
4573 static void niu_enable_tx_mac(struct niu *np, int on)
4574 {
4575 if (np->flags & NIU_FLAGS_XMAC)
4576 niu_enable_tx_xmac(np, on);
4577 else
4578 niu_enable_tx_bmac(np, on);
4579 }
4580
4581 static void niu_enable_rx_xmac(struct niu *np, int on)
4582 {
4583 u64 val = nr64_mac(XMAC_CONFIG);
4584
4585 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
4586 XMAC_CONFIG_PROMISCUOUS);
4587
4588 if (np->flags & NIU_FLAGS_MCAST)
4589 val |= XMAC_CONFIG_HASH_FILTER_EN;
4590 if (np->flags & NIU_FLAGS_PROMISC)
4591 val |= XMAC_CONFIG_PROMISCUOUS;
4592
4593 if (on)
4594 val |= XMAC_CONFIG_RX_MAC_ENABLE;
4595 else
4596 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
4597 nw64_mac(XMAC_CONFIG, val);
4598 }
4599
4600 static void niu_enable_rx_bmac(struct niu *np, int on)
4601 {
4602 u64 val = nr64_mac(BRXMAC_CONFIG);
4603
4604 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
4605 BRXMAC_CONFIG_PROMISC);
4606
4607 if (np->flags & NIU_FLAGS_MCAST)
4608 val |= BRXMAC_CONFIG_HASH_FILT_EN;
4609 if (np->flags & NIU_FLAGS_PROMISC)
4610 val |= BRXMAC_CONFIG_PROMISC;
4611
4612 if (on)
4613 val |= BRXMAC_CONFIG_ENABLE;
4614 else
4615 val &= ~BRXMAC_CONFIG_ENABLE;
4616 nw64_mac(BRXMAC_CONFIG, val);
4617 }
4618
4619 static void niu_enable_rx_mac(struct niu *np, int on)
4620 {
4621 if (np->flags & NIU_FLAGS_XMAC)
4622 niu_enable_rx_xmac(np, on);
4623 else
4624 niu_enable_rx_bmac(np, on);
4625 }
4626
4627 static int niu_init_mac(struct niu *np)
4628 {
4629 int err;
4630
4631 niu_init_xif(np);
4632 err = niu_init_pcs(np);
4633 if (err)
4634 return err;
4635
4636 err = niu_reset_tx_mac(np);
4637 if (err)
4638 return err;
4639 niu_init_tx_mac(np);
4640 err = niu_reset_rx_mac(np);
4641 if (err)
4642 return err;
4643 niu_init_rx_mac(np);
4644
4645 /* This looks hookey but the RX MAC reset we just did will
4646 * undo some of the state we setup in niu_init_tx_mac() so we
4647 * have to call it again. In particular, the RX MAC reset will
4648 * set the XMAC_MAX register back to it's default value.
4649 */
4650 niu_init_tx_mac(np);
4651 niu_enable_tx_mac(np, 1);
4652
4653 niu_enable_rx_mac(np, 1);
4654
4655 return 0;
4656 }
4657
4658 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4659 {
4660 (void) niu_tx_channel_stop(np, rp->tx_channel);
4661 }
4662
4663 static void niu_stop_tx_channels(struct niu *np)
4664 {
4665 int i;
4666
4667 for (i = 0; i < np->num_tx_rings; i++) {
4668 struct tx_ring_info *rp = &np->tx_rings[i];
4669
4670 niu_stop_one_tx_channel(np, rp);
4671 }
4672 }
4673
4674 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp)
4675 {
4676 (void) niu_tx_channel_reset(np, rp->tx_channel);
4677 }
4678
4679 static void niu_reset_tx_channels(struct niu *np)
4680 {
4681 int i;
4682
4683 for (i = 0; i < np->num_tx_rings; i++) {
4684 struct tx_ring_info *rp = &np->tx_rings[i];
4685
4686 niu_reset_one_tx_channel(np, rp);
4687 }
4688 }
4689
4690 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4691 {
4692 (void) niu_enable_rx_channel(np, rp->rx_channel, 0);
4693 }
4694
4695 static void niu_stop_rx_channels(struct niu *np)
4696 {
4697 int i;
4698
4699 for (i = 0; i < np->num_rx_rings; i++) {
4700 struct rx_ring_info *rp = &np->rx_rings[i];
4701
4702 niu_stop_one_rx_channel(np, rp);
4703 }
4704 }
4705
4706 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp)
4707 {
4708 int channel = rp->rx_channel;
4709
4710 (void) niu_rx_channel_reset(np, channel);
4711 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
4712 nw64(RX_DMA_CTL_STAT(channel), 0);
4713 (void) niu_enable_rx_channel(np, channel, 0);
4714 }
4715
4716 static void niu_reset_rx_channels(struct niu *np)
4717 {
4718 int i;
4719
4720 for (i = 0; i < np->num_rx_rings; i++) {
4721 struct rx_ring_info *rp = &np->rx_rings[i];
4722
4723 niu_reset_one_rx_channel(np, rp);
4724 }
4725 }
4726
4727 static void niu_disable_ipp(struct niu *np)
4728 {
4729 u64 rd, wr, val;
4730 int limit;
4731
4732 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
4733 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
4734 limit = 100;
4735 while (--limit >= 0 && (rd != wr)) {
4736 rd = nr64_ipp(IPP_DFIFO_RD_PTR);
4737 wr = nr64_ipp(IPP_DFIFO_WR_PTR);
4738 }
4739 if (limit < 0 &&
4740 (rd != 0 && wr != 1)) {
4741 dev_err(np->device, PFX "%s: IPP would not quiesce, "
4742 "rd_ptr[%llx] wr_ptr[%llx]\n",
4743 np->dev->name,
4744 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR),
4745 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR));
4746 }
4747
4748 val = nr64_ipp(IPP_CFIG);
4749 val &= ~(IPP_CFIG_IPP_ENABLE |
4750 IPP_CFIG_DFIFO_ECC_EN |
4751 IPP_CFIG_DROP_BAD_CRC |
4752 IPP_CFIG_CKSUM_EN);
4753 nw64_ipp(IPP_CFIG, val);
4754
4755 (void) niu_ipp_reset(np);
4756 }
4757
4758 static int niu_init_hw(struct niu *np)
4759 {
4760 int i, err;
4761
4762 niudbg(IFUP, "%s: Initialize TXC\n", np->dev->name);
4763 niu_txc_enable_port(np, 1);
4764 niu_txc_port_dma_enable(np, 1);
4765 niu_txc_set_imask(np, 0);
4766
4767 niudbg(IFUP, "%s: Initialize TX channels\n", np->dev->name);
4768 for (i = 0; i < np->num_tx_rings; i++) {
4769 struct tx_ring_info *rp = &np->tx_rings[i];
4770
4771 err = niu_init_one_tx_channel(np, rp);
4772 if (err)
4773 return err;
4774 }
4775
4776 niudbg(IFUP, "%s: Initialize RX channels\n", np->dev->name);
4777 err = niu_init_rx_channels(np);
4778 if (err)
4779 goto out_uninit_tx_channels;
4780
4781 niudbg(IFUP, "%s: Initialize classifier\n", np->dev->name);
4782 err = niu_init_classifier_hw(np);
4783 if (err)
4784 goto out_uninit_rx_channels;
4785
4786 niudbg(IFUP, "%s: Initialize ZCP\n", np->dev->name);
4787 err = niu_init_zcp(np);
4788 if (err)
4789 goto out_uninit_rx_channels;
4790
4791 niudbg(IFUP, "%s: Initialize IPP\n", np->dev->name);
4792 err = niu_init_ipp(np);
4793 if (err)
4794 goto out_uninit_rx_channels;
4795
4796 niudbg(IFUP, "%s: Initialize MAC\n", np->dev->name);
4797 err = niu_init_mac(np);
4798 if (err)
4799 goto out_uninit_ipp;
4800
4801 return 0;
4802
4803 out_uninit_ipp:
4804 niudbg(IFUP, "%s: Uninit IPP\n", np->dev->name);
4805 niu_disable_ipp(np);
4806
4807 out_uninit_rx_channels:
4808 niudbg(IFUP, "%s: Uninit RX channels\n", np->dev->name);
4809 niu_stop_rx_channels(np);
4810 niu_reset_rx_channels(np);
4811
4812 out_uninit_tx_channels:
4813 niudbg(IFUP, "%s: Uninit TX channels\n", np->dev->name);
4814 niu_stop_tx_channels(np);
4815 niu_reset_tx_channels(np);
4816
4817 return err;
4818 }
4819
4820 static void niu_stop_hw(struct niu *np)
4821 {
4822 niudbg(IFDOWN, "%s: Disable interrupts\n", np->dev->name);
4823 niu_enable_interrupts(np, 0);
4824
4825 niudbg(IFDOWN, "%s: Disable RX MAC\n", np->dev->name);
4826 niu_enable_rx_mac(np, 0);
4827
4828 niudbg(IFDOWN, "%s: Disable IPP\n", np->dev->name);
4829 niu_disable_ipp(np);
4830
4831 niudbg(IFDOWN, "%s: Stop TX channels\n", np->dev->name);
4832 niu_stop_tx_channels(np);
4833
4834 niudbg(IFDOWN, "%s: Stop RX channels\n", np->dev->name);
4835 niu_stop_rx_channels(np);
4836
4837 niudbg(IFDOWN, "%s: Reset TX channels\n", np->dev->name);
4838 niu_reset_tx_channels(np);
4839
4840 niudbg(IFDOWN, "%s: Reset RX channels\n", np->dev->name);
4841 niu_reset_rx_channels(np);
4842 }
4843
4844 static int niu_request_irq(struct niu *np)
4845 {
4846 int i, j, err;
4847
4848 err = 0;
4849 for (i = 0; i < np->num_ldg; i++) {
4850 struct niu_ldg *lp = &np->ldg[i];
4851
4852 err = request_irq(lp->irq, niu_interrupt,
4853 IRQF_SHARED | IRQF_SAMPLE_RANDOM,
4854 np->dev->name, lp);
4855 if (err)
4856 goto out_free_irqs;
4857
4858 }
4859
4860 return 0;
4861
4862 out_free_irqs:
4863 for (j = 0; j < i; j++) {
4864 struct niu_ldg *lp = &np->ldg[j];
4865
4866 free_irq(lp->irq, lp);
4867 }
4868 return err;
4869 }
4870
4871 static void niu_free_irq(struct niu *np)
4872 {
4873 int i;
4874
4875 for (i = 0; i < np->num_ldg; i++) {
4876 struct niu_ldg *lp = &np->ldg[i];
4877
4878 free_irq(lp->irq, lp);
4879 }
4880 }
4881
4882 static void niu_enable_napi(struct niu *np)
4883 {
4884 int i;
4885
4886 for (i = 0; i < np->num_ldg; i++)
4887 napi_enable(&np->ldg[i].napi);
4888 }
4889
4890 static void niu_disable_napi(struct niu *np)
4891 {
4892 int i;
4893
4894 for (i = 0; i < np->num_ldg; i++)
4895 napi_disable(&np->ldg[i].napi);
4896 }
4897
4898 static int niu_open(struct net_device *dev)
4899 {
4900 struct niu *np = netdev_priv(dev);
4901 int err;
4902
4903 netif_carrier_off(dev);
4904
4905 err = niu_alloc_channels(np);
4906 if (err)
4907 goto out_err;
4908
4909 err = niu_enable_interrupts(np, 0);
4910 if (err)
4911 goto out_free_channels;
4912
4913 err = niu_request_irq(np);
4914 if (err)
4915 goto out_free_channels;
4916
4917 niu_enable_napi(np);
4918
4919 spin_lock_irq(&np->lock);
4920
4921 err = niu_init_hw(np);
4922 if (!err) {
4923 init_timer(&np->timer);
4924 np->timer.expires = jiffies + HZ;
4925 np->timer.data = (unsigned long) np;
4926 np->timer.function = niu_timer;
4927
4928 err = niu_enable_interrupts(np, 1);
4929 if (err)
4930 niu_stop_hw(np);
4931 }
4932
4933 spin_unlock_irq(&np->lock);
4934
4935 if (err) {
4936 niu_disable_napi(np);
4937 goto out_free_irq;
4938 }
4939
4940 netif_start_queue(dev);
4941
4942 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
4943 netif_carrier_on(dev);
4944
4945 add_timer(&np->timer);
4946
4947 return 0;
4948
4949 out_free_irq:
4950 niu_free_irq(np);
4951
4952 out_free_channels:
4953 niu_free_channels(np);
4954
4955 out_err:
4956 return err;
4957 }
4958
4959 static void niu_full_shutdown(struct niu *np, struct net_device *dev)
4960 {
4961 cancel_work_sync(&np->reset_task);
4962
4963 niu_disable_napi(np);
4964 netif_stop_queue(dev);
4965
4966 del_timer_sync(&np->timer);
4967
4968 spin_lock_irq(&np->lock);
4969
4970 niu_stop_hw(np);
4971
4972 spin_unlock_irq(&np->lock);
4973 }
4974
4975 static int niu_close(struct net_device *dev)
4976 {
4977 struct niu *np = netdev_priv(dev);
4978
4979 niu_full_shutdown(np, dev);
4980
4981 niu_free_irq(np);
4982
4983 niu_free_channels(np);
4984
4985 niu_handle_led(np, 0);
4986
4987 return 0;
4988 }
4989
4990 static void niu_sync_xmac_stats(struct niu *np)
4991 {
4992 struct niu_xmac_stats *mp = &np->mac_stats.xmac;
4993
4994 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT);
4995 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT);
4996
4997 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT);
4998 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT);
4999 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT);
5000 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT);
5001 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT);
5002 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1);
5003 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2);
5004 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3);
5005 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4);
5006 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5);
5007 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6);
5008 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7);
5009 mp->rx_octets += nr64_mac(RXMAC_BT_CNT);
5010 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT);
5011 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT);
5012 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT);
5013 }
5014
5015 static void niu_sync_bmac_stats(struct niu *np)
5016 {
5017 struct niu_bmac_stats *mp = &np->mac_stats.bmac;
5018
5019 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT);
5020 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT);
5021
5022 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT);
5023 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
5024 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT);
5025 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT);
5026 }
5027
5028 static void niu_sync_mac_stats(struct niu *np)
5029 {
5030 if (np->flags & NIU_FLAGS_XMAC)
5031 niu_sync_xmac_stats(np);
5032 else
5033 niu_sync_bmac_stats(np);
5034 }
5035
5036 static void niu_get_rx_stats(struct niu *np)
5037 {
5038 unsigned long pkts, dropped, errors, bytes;
5039 int i;
5040
5041 pkts = dropped = errors = bytes = 0;
5042 for (i = 0; i < np->num_rx_rings; i++) {
5043 struct rx_ring_info *rp = &np->rx_rings[i];
5044
5045 pkts += rp->rx_packets;
5046 bytes += rp->rx_bytes;
5047 dropped += rp->rx_dropped;
5048 errors += rp->rx_errors;
5049 }
5050 np->net_stats.rx_packets = pkts;
5051 np->net_stats.rx_bytes = bytes;
5052 np->net_stats.rx_dropped = dropped;
5053 np->net_stats.rx_errors = errors;
5054 }
5055
5056 static void niu_get_tx_stats(struct niu *np)
5057 {
5058 unsigned long pkts, errors, bytes;
5059 int i;
5060
5061 pkts = errors = bytes = 0;
5062 for (i = 0; i < np->num_tx_rings; i++) {
5063 struct tx_ring_info *rp = &np->tx_rings[i];
5064
5065 pkts += rp->tx_packets;
5066 bytes += rp->tx_bytes;
5067 errors += rp->tx_errors;
5068 }
5069 np->net_stats.tx_packets = pkts;
5070 np->net_stats.tx_bytes = bytes;
5071 np->net_stats.tx_errors = errors;
5072 }
5073
5074 static struct net_device_stats *niu_get_stats(struct net_device *dev)
5075 {
5076 struct niu *np = netdev_priv(dev);
5077
5078 niu_get_rx_stats(np);
5079 niu_get_tx_stats(np);
5080
5081 return &np->net_stats;
5082 }
5083
5084 static void niu_load_hash_xmac(struct niu *np, u16 *hash)
5085 {
5086 int i;
5087
5088 for (i = 0; i < 16; i++)
5089 nw64_mac(XMAC_HASH_TBL(i), hash[i]);
5090 }
5091
5092 static void niu_load_hash_bmac(struct niu *np, u16 *hash)
5093 {
5094 int i;
5095
5096 for (i = 0; i < 16; i++)
5097 nw64_mac(BMAC_HASH_TBL(i), hash[i]);
5098 }
5099
5100 static void niu_load_hash(struct niu *np, u16 *hash)
5101 {
5102 if (np->flags & NIU_FLAGS_XMAC)
5103 niu_load_hash_xmac(np, hash);
5104 else
5105 niu_load_hash_bmac(np, hash);
5106 }
5107
5108 static void niu_set_rx_mode(struct net_device *dev)
5109 {
5110 struct niu *np = netdev_priv(dev);
5111 int i, alt_cnt, err;
5112 struct dev_addr_list *addr;
5113 unsigned long flags;
5114 u16 hash[16] = { 0, };
5115
5116 spin_lock_irqsave(&np->lock, flags);
5117 niu_enable_rx_mac(np, 0);
5118
5119 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC);
5120 if (dev->flags & IFF_PROMISC)
5121 np->flags |= NIU_FLAGS_PROMISC;
5122 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 0))
5123 np->flags |= NIU_FLAGS_MCAST;
5124
5125 alt_cnt = dev->uc_count;
5126 if (alt_cnt > niu_num_alt_addr(np)) {
5127 alt_cnt = 0;
5128 np->flags |= NIU_FLAGS_PROMISC;
5129 }
5130
5131 if (alt_cnt) {
5132 int index = 0;
5133
5134 for (addr = dev->uc_list; addr; addr = addr->next) {
5135 err = niu_set_alt_mac(np, index,
5136 addr->da_addr);
5137 if (err)
5138 printk(KERN_WARNING PFX "%s: Error %d "
5139 "adding alt mac %d\n",
5140 dev->name, err, index);
5141 err = niu_enable_alt_mac(np, index, 1);
5142 if (err)
5143 printk(KERN_WARNING PFX "%s: Error %d "
5144 "enabling alt mac %d\n",
5145 dev->name, err, index);
5146
5147 index++;
5148 }
5149 } else {
5150 for (i = 0; i < niu_num_alt_addr(np); i++) {
5151 err = niu_enable_alt_mac(np, i, 0);
5152 if (err)
5153 printk(KERN_WARNING PFX "%s: Error %d "
5154 "disabling alt mac %d\n",
5155 dev->name, err, i);
5156 }
5157 }
5158 if (dev->flags & IFF_ALLMULTI) {
5159 for (i = 0; i < 16; i++)
5160 hash[i] = 0xffff;
5161 } else if (dev->mc_count > 0) {
5162 for (addr = dev->mc_list; addr; addr = addr->next) {
5163 u32 crc = ether_crc_le(ETH_ALEN, addr->da_addr);
5164
5165 crc >>= 24;
5166 hash[crc >> 4] |= (1 << (15 - (crc & 0xf)));
5167 }
5168 }
5169
5170 if (np->flags & NIU_FLAGS_MCAST)
5171 niu_load_hash(np, hash);
5172
5173 niu_enable_rx_mac(np, 1);
5174 spin_unlock_irqrestore(&np->lock, flags);
5175 }
5176
5177 static int niu_set_mac_addr(struct net_device *dev, void *p)
5178 {
5179 struct niu *np = netdev_priv(dev);
5180 struct sockaddr *addr = p;
5181 unsigned long flags;
5182
5183 if (!is_valid_ether_addr(addr->sa_data))
5184 return -EINVAL;
5185
5186 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
5187
5188 if (!netif_running(dev))
5189 return 0;
5190
5191 spin_lock_irqsave(&np->lock, flags);
5192 niu_enable_rx_mac(np, 0);
5193 niu_set_primary_mac(np, dev->dev_addr);
5194 niu_enable_rx_mac(np, 1);
5195 spin_unlock_irqrestore(&np->lock, flags);
5196
5197 return 0;
5198 }
5199
5200 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5201 {
5202 return -EOPNOTSUPP;
5203 }
5204
5205 static void niu_netif_stop(struct niu *np)
5206 {
5207 np->dev->trans_start = jiffies; /* prevent tx timeout */
5208
5209 niu_disable_napi(np);
5210
5211 netif_tx_disable(np->dev);
5212 }
5213
5214 static void niu_netif_start(struct niu *np)
5215 {
5216 /* NOTE: unconditional netif_wake_queue is only appropriate
5217 * so long as all callers are assured to have free tx slots
5218 * (such as after niu_init_hw).
5219 */
5220 netif_wake_queue(np->dev);
5221
5222 niu_enable_napi(np);
5223
5224 niu_enable_interrupts(np, 1);
5225 }
5226
5227 static void niu_reset_task(struct work_struct *work)
5228 {
5229 struct niu *np = container_of(work, struct niu, reset_task);
5230 unsigned long flags;
5231 int err;
5232
5233 spin_lock_irqsave(&np->lock, flags);
5234 if (!netif_running(np->dev)) {
5235 spin_unlock_irqrestore(&np->lock, flags);
5236 return;
5237 }
5238
5239 spin_unlock_irqrestore(&np->lock, flags);
5240
5241 del_timer_sync(&np->timer);
5242
5243 niu_netif_stop(np);
5244
5245 spin_lock_irqsave(&np->lock, flags);
5246
5247 niu_stop_hw(np);
5248
5249 err = niu_init_hw(np);
5250 if (!err) {
5251 np->timer.expires = jiffies + HZ;
5252 add_timer(&np->timer);
5253 niu_netif_start(np);
5254 }
5255
5256 spin_unlock_irqrestore(&np->lock, flags);
5257 }
5258
5259 static void niu_tx_timeout(struct net_device *dev)
5260 {
5261 struct niu *np = netdev_priv(dev);
5262
5263 dev_err(np->device, PFX "%s: Transmit timed out, resetting\n",
5264 dev->name);
5265
5266 schedule_work(&np->reset_task);
5267 }
5268
5269 static void niu_set_txd(struct tx_ring_info *rp, int index,
5270 u64 mapping, u64 len, u64 mark,
5271 u64 n_frags)
5272 {
5273 __le64 *desc = &rp->descr[index];
5274
5275 *desc = cpu_to_le64(mark |
5276 (n_frags << TX_DESC_NUM_PTR_SHIFT) |
5277 (len << TX_DESC_TR_LEN_SHIFT) |
5278 (mapping & TX_DESC_SAD));
5279 }
5280
5281 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr,
5282 u64 pad_bytes, u64 len)
5283 {
5284 u16 eth_proto, eth_proto_inner;
5285 u64 csum_bits, l3off, ihl, ret;
5286 u8 ip_proto;
5287 int ipv6;
5288
5289 eth_proto = be16_to_cpu(ehdr->h_proto);
5290 eth_proto_inner = eth_proto;
5291 if (eth_proto == ETH_P_8021Q) {
5292 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr;
5293 __be16 val = vp->h_vlan_encapsulated_proto;
5294
5295 eth_proto_inner = be16_to_cpu(val);
5296 }
5297
5298 ipv6 = ihl = 0;
5299 switch (skb->protocol) {
5300 case __constant_htons(ETH_P_IP):
5301 ip_proto = ip_hdr(skb)->protocol;
5302 ihl = ip_hdr(skb)->ihl;
5303 break;
5304 case __constant_htons(ETH_P_IPV6):
5305 ip_proto = ipv6_hdr(skb)->nexthdr;
5306 ihl = (40 >> 2);
5307 ipv6 = 1;
5308 break;
5309 default:
5310 ip_proto = ihl = 0;
5311 break;
5312 }
5313
5314 csum_bits = TXHDR_CSUM_NONE;
5315 if (skb->ip_summed == CHECKSUM_PARTIAL) {
5316 u64 start, stuff;
5317
5318 csum_bits = (ip_proto == IPPROTO_TCP ?
5319 TXHDR_CSUM_TCP :
5320 (ip_proto == IPPROTO_UDP ?
5321 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP));
5322
5323 start = skb_transport_offset(skb) -
5324 (pad_bytes + sizeof(struct tx_pkt_hdr));
5325 stuff = start + skb->csum_offset;
5326
5327 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT;
5328 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT;
5329 }
5330
5331 l3off = skb_network_offset(skb) -
5332 (pad_bytes + sizeof(struct tx_pkt_hdr));
5333
5334 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) |
5335 (len << TXHDR_LEN_SHIFT) |
5336 ((l3off / 2) << TXHDR_L3START_SHIFT) |
5337 (ihl << TXHDR_IHL_SHIFT) |
5338 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) |
5339 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) |
5340 (ipv6 ? TXHDR_IP_VER : 0) |
5341 csum_bits);
5342
5343 return ret;
5344 }
5345
5346 static struct tx_ring_info *tx_ring_select(struct niu *np, struct sk_buff *skb)
5347 {
5348 return &np->tx_rings[0];
5349 }
5350
5351 static int niu_start_xmit(struct sk_buff *skb, struct net_device *dev)
5352 {
5353 struct niu *np = netdev_priv(dev);
5354 unsigned long align, headroom;
5355 struct tx_ring_info *rp;
5356 struct tx_pkt_hdr *tp;
5357 unsigned int len, nfg;
5358 struct ethhdr *ehdr;
5359 int prod, i, tlen;
5360 u64 mapping, mrk;
5361
5362 rp = tx_ring_select(np, skb);
5363
5364 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) {
5365 netif_stop_queue(dev);
5366 dev_err(np->device, PFX "%s: BUG! Tx ring full when "
5367 "queue awake!\n", dev->name);
5368 rp->tx_errors++;
5369 return NETDEV_TX_BUSY;
5370 }
5371
5372 if (skb->len < ETH_ZLEN) {
5373 unsigned int pad_bytes = ETH_ZLEN - skb->len;
5374
5375 if (skb_pad(skb, pad_bytes))
5376 goto out;
5377 skb_put(skb, pad_bytes);
5378 }
5379
5380 len = sizeof(struct tx_pkt_hdr) + 15;
5381 if (skb_headroom(skb) < len) {
5382 struct sk_buff *skb_new;
5383
5384 skb_new = skb_realloc_headroom(skb, len);
5385 if (!skb_new) {
5386 rp->tx_errors++;
5387 goto out_drop;
5388 }
5389 kfree_skb(skb);
5390 skb = skb_new;
5391 } else
5392 skb_orphan(skb);
5393
5394 align = ((unsigned long) skb->data & (16 - 1));
5395 headroom = align + sizeof(struct tx_pkt_hdr);
5396
5397 ehdr = (struct ethhdr *) skb->data;
5398 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom);
5399
5400 len = skb->len - sizeof(struct tx_pkt_hdr);
5401 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len));
5402 tp->resv = 0;
5403
5404 len = skb_headlen(skb);
5405 mapping = np->ops->map_single(np->device, skb->data,
5406 len, DMA_TO_DEVICE);
5407
5408 prod = rp->prod;
5409
5410 rp->tx_buffs[prod].skb = skb;
5411 rp->tx_buffs[prod].mapping = mapping;
5412
5413 mrk = TX_DESC_SOP;
5414 if (++rp->mark_counter == rp->mark_freq) {
5415 rp->mark_counter = 0;
5416 mrk |= TX_DESC_MARK;
5417 rp->mark_pending++;
5418 }
5419
5420 tlen = len;
5421 nfg = skb_shinfo(skb)->nr_frags;
5422 while (tlen > 0) {
5423 tlen -= MAX_TX_DESC_LEN;
5424 nfg++;
5425 }
5426
5427 while (len > 0) {
5428 unsigned int this_len = len;
5429
5430 if (this_len > MAX_TX_DESC_LEN)
5431 this_len = MAX_TX_DESC_LEN;
5432
5433 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg);
5434 mrk = nfg = 0;
5435
5436 prod = NEXT_TX(rp, prod);
5437 mapping += this_len;
5438 len -= this_len;
5439 }
5440
5441 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
5442 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5443
5444 len = frag->size;
5445 mapping = np->ops->map_page(np->device, frag->page,
5446 frag->page_offset, len,
5447 DMA_TO_DEVICE);
5448
5449 rp->tx_buffs[prod].skb = NULL;
5450 rp->tx_buffs[prod].mapping = mapping;
5451
5452 niu_set_txd(rp, prod, mapping, len, 0, 0);
5453
5454 prod = NEXT_TX(rp, prod);
5455 }
5456
5457 if (prod < rp->prod)
5458 rp->wrap_bit ^= TX_RING_KICK_WRAP;
5459 rp->prod = prod;
5460
5461 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
5462
5463 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) {
5464 netif_stop_queue(dev);
5465 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))
5466 netif_wake_queue(dev);
5467 }
5468
5469 dev->trans_start = jiffies;
5470
5471 out:
5472 return NETDEV_TX_OK;
5473
5474 out_drop:
5475 rp->tx_errors++;
5476 kfree_skb(skb);
5477 goto out;
5478 }
5479
5480 static int niu_change_mtu(struct net_device *dev, int new_mtu)
5481 {
5482 struct niu *np = netdev_priv(dev);
5483 int err, orig_jumbo, new_jumbo;
5484
5485 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU)
5486 return -EINVAL;
5487
5488 orig_jumbo = (dev->mtu > ETH_DATA_LEN);
5489 new_jumbo = (new_mtu > ETH_DATA_LEN);
5490
5491 dev->mtu = new_mtu;
5492
5493 if (!netif_running(dev) ||
5494 (orig_jumbo == new_jumbo))
5495 return 0;
5496
5497 niu_full_shutdown(np, dev);
5498
5499 niu_free_channels(np);
5500
5501 niu_enable_napi(np);
5502
5503 err = niu_alloc_channels(np);
5504 if (err)
5505 return err;
5506
5507 spin_lock_irq(&np->lock);
5508
5509 err = niu_init_hw(np);
5510 if (!err) {
5511 init_timer(&np->timer);
5512 np->timer.expires = jiffies + HZ;
5513 np->timer.data = (unsigned long) np;
5514 np->timer.function = niu_timer;
5515
5516 err = niu_enable_interrupts(np, 1);
5517 if (err)
5518 niu_stop_hw(np);
5519 }
5520
5521 spin_unlock_irq(&np->lock);
5522
5523 if (!err) {
5524 netif_start_queue(dev);
5525 if (np->link_config.loopback_mode != LOOPBACK_DISABLED)
5526 netif_carrier_on(dev);
5527
5528 add_timer(&np->timer);
5529 }
5530
5531 return err;
5532 }
5533
5534 static void niu_get_drvinfo(struct net_device *dev,
5535 struct ethtool_drvinfo *info)
5536 {
5537 struct niu *np = netdev_priv(dev);
5538 struct niu_vpd *vpd = &np->vpd;
5539
5540 strcpy(info->driver, DRV_MODULE_NAME);
5541 strcpy(info->version, DRV_MODULE_VERSION);
5542 sprintf(info->fw_version, "%d.%d",
5543 vpd->fcode_major, vpd->fcode_minor);
5544 if (np->parent->plat_type != PLAT_TYPE_NIU)
5545 strcpy(info->bus_info, pci_name(np->pdev));
5546 }
5547
5548 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5549 {
5550 struct niu *np = netdev_priv(dev);
5551 struct niu_link_config *lp;
5552
5553 lp = &np->link_config;
5554
5555 memset(cmd, 0, sizeof(*cmd));
5556 cmd->phy_address = np->phy_addr;
5557 cmd->supported = lp->supported;
5558 cmd->advertising = lp->advertising;
5559 cmd->autoneg = lp->autoneg;
5560 cmd->speed = lp->active_speed;
5561 cmd->duplex = lp->active_duplex;
5562
5563 return 0;
5564 }
5565
5566 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5567 {
5568 return -EINVAL;
5569 }
5570
5571 static u32 niu_get_msglevel(struct net_device *dev)
5572 {
5573 struct niu *np = netdev_priv(dev);
5574 return np->msg_enable;
5575 }
5576
5577 static void niu_set_msglevel(struct net_device *dev, u32 value)
5578 {
5579 struct niu *np = netdev_priv(dev);
5580 np->msg_enable = value;
5581 }
5582
5583 static int niu_get_eeprom_len(struct net_device *dev)
5584 {
5585 struct niu *np = netdev_priv(dev);
5586
5587 return np->eeprom_len;
5588 }
5589
5590 static int niu_get_eeprom(struct net_device *dev,
5591 struct ethtool_eeprom *eeprom, u8 *data)
5592 {
5593 struct niu *np = netdev_priv(dev);
5594 u32 offset, len, val;
5595
5596 offset = eeprom->offset;
5597 len = eeprom->len;
5598
5599 if (offset + len < offset)
5600 return -EINVAL;
5601 if (offset >= np->eeprom_len)
5602 return -EINVAL;
5603 if (offset + len > np->eeprom_len)
5604 len = eeprom->len = np->eeprom_len - offset;
5605
5606 if (offset & 3) {
5607 u32 b_offset, b_count;
5608
5609 b_offset = offset & 3;
5610 b_count = 4 - b_offset;
5611 if (b_count > len)
5612 b_count = len;
5613
5614 val = nr64(ESPC_NCR((offset - b_offset) / 4));
5615 memcpy(data, ((char *)&val) + b_offset, b_count);
5616 data += b_count;
5617 len -= b_count;
5618 offset += b_count;
5619 }
5620 while (len >= 4) {
5621 val = nr64(ESPC_NCR(offset / 4));
5622 memcpy(data, &val, 4);
5623 data += 4;
5624 len -= 4;
5625 offset += 4;
5626 }
5627 if (len) {
5628 val = nr64(ESPC_NCR(offset / 4));
5629 memcpy(data, &val, len);
5630 }
5631 return 0;
5632 }
5633
5634 static const struct {
5635 const char string[ETH_GSTRING_LEN];
5636 } niu_xmac_stat_keys[] = {
5637 { "tx_frames" },
5638 { "tx_bytes" },
5639 { "tx_fifo_errors" },
5640 { "tx_overflow_errors" },
5641 { "tx_max_pkt_size_errors" },
5642 { "tx_underflow_errors" },
5643 { "rx_local_faults" },
5644 { "rx_remote_faults" },
5645 { "rx_link_faults" },
5646 { "rx_align_errors" },
5647 { "rx_frags" },
5648 { "rx_mcasts" },
5649 { "rx_bcasts" },
5650 { "rx_hist_cnt1" },
5651 { "rx_hist_cnt2" },
5652 { "rx_hist_cnt3" },
5653 { "rx_hist_cnt4" },
5654 { "rx_hist_cnt5" },
5655 { "rx_hist_cnt6" },
5656 { "rx_hist_cnt7" },
5657 { "rx_octets" },
5658 { "rx_code_violations" },
5659 { "rx_len_errors" },
5660 { "rx_crc_errors" },
5661 { "rx_underflows" },
5662 { "rx_overflows" },
5663 { "pause_off_state" },
5664 { "pause_on_state" },
5665 { "pause_received" },
5666 };
5667
5668 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
5669
5670 static const struct {
5671 const char string[ETH_GSTRING_LEN];
5672 } niu_bmac_stat_keys[] = {
5673 { "tx_underflow_errors" },
5674 { "tx_max_pkt_size_errors" },
5675 { "tx_bytes" },
5676 { "tx_frames" },
5677 { "rx_overflows" },
5678 { "rx_frames" },
5679 { "rx_align_errors" },
5680 { "rx_crc_errors" },
5681 { "rx_len_errors" },
5682 { "pause_off_state" },
5683 { "pause_on_state" },
5684 { "pause_received" },
5685 };
5686
5687 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
5688
5689 static const struct {
5690 const char string[ETH_GSTRING_LEN];
5691 } niu_rxchan_stat_keys[] = {
5692 { "rx_channel" },
5693 { "rx_packets" },
5694 { "rx_bytes" },
5695 { "rx_dropped" },
5696 { "rx_errors" },
5697 };
5698
5699 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
5700
5701 static const struct {
5702 const char string[ETH_GSTRING_LEN];
5703 } niu_txchan_stat_keys[] = {
5704 { "tx_channel" },
5705 { "tx_packets" },
5706 { "tx_bytes" },
5707 { "tx_errors" },
5708 };
5709
5710 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
5711
5712 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data)
5713 {
5714 struct niu *np = netdev_priv(dev);
5715 int i;
5716
5717 if (stringset != ETH_SS_STATS)
5718 return;
5719
5720 if (np->flags & NIU_FLAGS_XMAC) {
5721 memcpy(data, niu_xmac_stat_keys,
5722 sizeof(niu_xmac_stat_keys));
5723 data += sizeof(niu_xmac_stat_keys);
5724 } else {
5725 memcpy(data, niu_bmac_stat_keys,
5726 sizeof(niu_bmac_stat_keys));
5727 data += sizeof(niu_bmac_stat_keys);
5728 }
5729 for (i = 0; i < np->num_rx_rings; i++) {
5730 memcpy(data, niu_rxchan_stat_keys,
5731 sizeof(niu_rxchan_stat_keys));
5732 data += sizeof(niu_rxchan_stat_keys);
5733 }
5734 for (i = 0; i < np->num_tx_rings; i++) {
5735 memcpy(data, niu_txchan_stat_keys,
5736 sizeof(niu_txchan_stat_keys));
5737 data += sizeof(niu_txchan_stat_keys);
5738 }
5739 }
5740
5741 static int niu_get_stats_count(struct net_device *dev)
5742 {
5743 struct niu *np = netdev_priv(dev);
5744
5745 return ((np->flags & NIU_FLAGS_XMAC ?
5746 NUM_XMAC_STAT_KEYS :
5747 NUM_BMAC_STAT_KEYS) +
5748 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) +
5749 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS));
5750 }
5751
5752 static void niu_get_ethtool_stats(struct net_device *dev,
5753 struct ethtool_stats *stats, u64 *data)
5754 {
5755 struct niu *np = netdev_priv(dev);
5756 int i;
5757
5758 niu_sync_mac_stats(np);
5759 if (np->flags & NIU_FLAGS_XMAC) {
5760 memcpy(data, &np->mac_stats.xmac,
5761 sizeof(struct niu_xmac_stats));
5762 data += (sizeof(struct niu_xmac_stats) / sizeof(u64));
5763 } else {
5764 memcpy(data, &np->mac_stats.bmac,
5765 sizeof(struct niu_bmac_stats));
5766 data += (sizeof(struct niu_bmac_stats) / sizeof(u64));
5767 }
5768 for (i = 0; i < np->num_rx_rings; i++) {
5769 struct rx_ring_info *rp = &np->rx_rings[i];
5770
5771 data[0] = rp->rx_channel;
5772 data[1] = rp->rx_packets;
5773 data[2] = rp->rx_bytes;
5774 data[3] = rp->rx_dropped;
5775 data[4] = rp->rx_errors;
5776 data += 5;
5777 }
5778 for (i = 0; i < np->num_tx_rings; i++) {
5779 struct tx_ring_info *rp = &np->tx_rings[i];
5780
5781 data[0] = rp->tx_channel;
5782 data[1] = rp->tx_packets;
5783 data[2] = rp->tx_bytes;
5784 data[3] = rp->tx_errors;
5785 data += 4;
5786 }
5787 }
5788
5789 static u64 niu_led_state_save(struct niu *np)
5790 {
5791 if (np->flags & NIU_FLAGS_XMAC)
5792 return nr64_mac(XMAC_CONFIG);
5793 else
5794 return nr64_mac(BMAC_XIF_CONFIG);
5795 }
5796
5797 static void niu_led_state_restore(struct niu *np, u64 val)
5798 {
5799 if (np->flags & NIU_FLAGS_XMAC)
5800 nw64_mac(XMAC_CONFIG, val);
5801 else
5802 nw64_mac(BMAC_XIF_CONFIG, val);
5803 }
5804
5805 static void niu_force_led(struct niu *np, int on)
5806 {
5807 u64 val, reg, bit;
5808
5809 if (np->flags & NIU_FLAGS_XMAC) {
5810 reg = XMAC_CONFIG;
5811 bit = XMAC_CONFIG_FORCE_LED_ON;
5812 } else {
5813 reg = BMAC_XIF_CONFIG;
5814 bit = BMAC_XIF_CONFIG_LINK_LED;
5815 }
5816
5817 val = nr64_mac(reg);
5818 if (on)
5819 val |= bit;
5820 else
5821 val &= ~bit;
5822 nw64_mac(reg, val);
5823 }
5824
5825 static int niu_phys_id(struct net_device *dev, u32 data)
5826 {
5827 struct niu *np = netdev_priv(dev);
5828 u64 orig_led_state;
5829 int i;
5830
5831 if (!netif_running(dev))
5832 return -EAGAIN;
5833
5834 if (data == 0)
5835 data = 2;
5836
5837 orig_led_state = niu_led_state_save(np);
5838 for (i = 0; i < (data * 2); i++) {
5839 int on = ((i % 2) == 0);
5840
5841 niu_force_led(np, on);
5842
5843 if (msleep_interruptible(500))
5844 break;
5845 }
5846 niu_led_state_restore(np, orig_led_state);
5847
5848 return 0;
5849 }
5850
5851 static const struct ethtool_ops niu_ethtool_ops = {
5852 .get_drvinfo = niu_get_drvinfo,
5853 .get_link = ethtool_op_get_link,
5854 .get_msglevel = niu_get_msglevel,
5855 .set_msglevel = niu_set_msglevel,
5856 .get_eeprom_len = niu_get_eeprom_len,
5857 .get_eeprom = niu_get_eeprom,
5858 .get_settings = niu_get_settings,
5859 .set_settings = niu_set_settings,
5860 .get_strings = niu_get_strings,
5861 .get_stats_count = niu_get_stats_count,
5862 .get_ethtool_stats = niu_get_ethtool_stats,
5863 .phys_id = niu_phys_id,
5864 };
5865
5866 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent,
5867 int ldg, int ldn)
5868 {
5869 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX)
5870 return -EINVAL;
5871 if (ldn < 0 || ldn > LDN_MAX)
5872 return -EINVAL;
5873
5874 parent->ldg_map[ldn] = ldg;
5875
5876 if (np->parent->plat_type == PLAT_TYPE_NIU) {
5877 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
5878 * the firmware, and we're not supposed to change them.
5879 * Validate the mapping, because if it's wrong we probably
5880 * won't get any interrupts and that's painful to debug.
5881 */
5882 if (nr64(LDG_NUM(ldn)) != ldg) {
5883 dev_err(np->device, PFX "Port %u, mis-matched "
5884 "LDG assignment "
5885 "for ldn %d, should be %d is %llu\n",
5886 np->port, ldn, ldg,
5887 (unsigned long long) nr64(LDG_NUM(ldn)));
5888 return -EINVAL;
5889 }
5890 } else
5891 nw64(LDG_NUM(ldn), ldg);
5892
5893 return 0;
5894 }
5895
5896 static int niu_set_ldg_timer_res(struct niu *np, int res)
5897 {
5898 if (res < 0 || res > LDG_TIMER_RES_VAL)
5899 return -EINVAL;
5900
5901
5902 nw64(LDG_TIMER_RES, res);
5903
5904 return 0;
5905 }
5906
5907 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector)
5908 {
5909 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) ||
5910 (func < 0 || func > 3) ||
5911 (vector < 0 || vector > 0x1f))
5912 return -EINVAL;
5913
5914 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
5915
5916 return 0;
5917 }
5918
5919 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr)
5920 {
5921 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START |
5922 (addr << ESPC_PIO_STAT_ADDR_SHIFT));
5923 int limit;
5924
5925 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT))
5926 return -EINVAL;
5927
5928 frame = frame_base;
5929 nw64(ESPC_PIO_STAT, frame);
5930 limit = 64;
5931 do {
5932 udelay(5);
5933 frame = nr64(ESPC_PIO_STAT);
5934 if (frame & ESPC_PIO_STAT_READ_END)
5935 break;
5936 } while (limit--);
5937 if (!(frame & ESPC_PIO_STAT_READ_END)) {
5938 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
5939 (unsigned long long) frame);
5940 return -ENODEV;
5941 }
5942
5943 frame = frame_base;
5944 nw64(ESPC_PIO_STAT, frame);
5945 limit = 64;
5946 do {
5947 udelay(5);
5948 frame = nr64(ESPC_PIO_STAT);
5949 if (frame & ESPC_PIO_STAT_READ_END)
5950 break;
5951 } while (limit--);
5952 if (!(frame & ESPC_PIO_STAT_READ_END)) {
5953 dev_err(np->device, PFX "EEPROM read timeout frame[%llx]\n",
5954 (unsigned long long) frame);
5955 return -ENODEV;
5956 }
5957
5958 frame = nr64(ESPC_PIO_STAT);
5959 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT;
5960 }
5961
5962 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off)
5963 {
5964 int err = niu_pci_eeprom_read(np, off);
5965 u16 val;
5966
5967 if (err < 0)
5968 return err;
5969 val = (err << 8);
5970 err = niu_pci_eeprom_read(np, off + 1);
5971 if (err < 0)
5972 return err;
5973 val |= (err & 0xff);
5974
5975 return val;
5976 }
5977
5978 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off)
5979 {
5980 int err = niu_pci_eeprom_read(np, off);
5981 u16 val;
5982
5983 if (err < 0)
5984 return err;
5985
5986 val = (err & 0xff);
5987 err = niu_pci_eeprom_read(np, off + 1);
5988 if (err < 0)
5989 return err;
5990
5991 val |= (err & 0xff) << 8;
5992
5993 return val;
5994 }
5995
5996 static int __devinit niu_pci_vpd_get_propname(struct niu *np,
5997 u32 off,
5998 char *namebuf,
5999 int namebuf_len)
6000 {
6001 int i;
6002
6003 for (i = 0; i < namebuf_len; i++) {
6004 int err = niu_pci_eeprom_read(np, off + i);
6005 if (err < 0)
6006 return err;
6007 *namebuf++ = err;
6008 if (!err)
6009 break;
6010 }
6011 if (i >= namebuf_len)
6012 return -EINVAL;
6013
6014 return i + 1;
6015 }
6016
6017 static void __devinit niu_vpd_parse_version(struct niu *np)
6018 {
6019 struct niu_vpd *vpd = &np->vpd;
6020 int len = strlen(vpd->version) + 1;
6021 const char *s = vpd->version;
6022 int i;
6023
6024 for (i = 0; i < len - 5; i++) {
6025 if (!strncmp(s + i, "FCode ", 5))
6026 break;
6027 }
6028 if (i >= len - 5)
6029 return;
6030
6031 s += i + 5;
6032 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor);
6033
6034 niudbg(PROBE, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
6035 vpd->fcode_major, vpd->fcode_minor);
6036 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR ||
6037 (vpd->fcode_major == NIU_VPD_MIN_MAJOR &&
6038 vpd->fcode_minor >= NIU_VPD_MIN_MINOR))
6039 np->flags |= NIU_FLAGS_VPD_VALID;
6040 }
6041
6042 /* ESPC_PIO_EN_ENABLE must be set */
6043 static int __devinit niu_pci_vpd_scan_props(struct niu *np,
6044 u32 start, u32 end)
6045 {
6046 unsigned int found_mask = 0;
6047 #define FOUND_MASK_MODEL 0x00000001
6048 #define FOUND_MASK_BMODEL 0x00000002
6049 #define FOUND_MASK_VERS 0x00000004
6050 #define FOUND_MASK_MAC 0x00000008
6051 #define FOUND_MASK_NMAC 0x00000010
6052 #define FOUND_MASK_PHY 0x00000020
6053 #define FOUND_MASK_ALL 0x0000003f
6054
6055 niudbg(PROBE, "VPD_SCAN: start[%x] end[%x]\n",
6056 start, end);
6057 while (start < end) {
6058 int len, err, instance, type, prop_len;
6059 char namebuf[64];
6060 u8 *prop_buf;
6061 int max_len;
6062
6063 if (found_mask == FOUND_MASK_ALL) {
6064 niu_vpd_parse_version(np);
6065 return 1;
6066 }
6067
6068 err = niu_pci_eeprom_read(np, start + 2);
6069 if (err < 0)
6070 return err;
6071 len = err;
6072 start += 3;
6073
6074 instance = niu_pci_eeprom_read(np, start);
6075 type = niu_pci_eeprom_read(np, start + 3);
6076 prop_len = niu_pci_eeprom_read(np, start + 4);
6077 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
6078 if (err < 0)
6079 return err;
6080
6081 prop_buf = NULL;
6082 max_len = 0;
6083 if (!strcmp(namebuf, "model")) {
6084 prop_buf = np->vpd.model;
6085 max_len = NIU_VPD_MODEL_MAX;
6086 found_mask |= FOUND_MASK_MODEL;
6087 } else if (!strcmp(namebuf, "board-model")) {
6088 prop_buf = np->vpd.board_model;
6089 max_len = NIU_VPD_BD_MODEL_MAX;
6090 found_mask |= FOUND_MASK_BMODEL;
6091 } else if (!strcmp(namebuf, "version")) {
6092 prop_buf = np->vpd.version;
6093 max_len = NIU_VPD_VERSION_MAX;
6094 found_mask |= FOUND_MASK_VERS;
6095 } else if (!strcmp(namebuf, "local-mac-address")) {
6096 prop_buf = np->vpd.local_mac;
6097 max_len = ETH_ALEN;
6098 found_mask |= FOUND_MASK_MAC;
6099 } else if (!strcmp(namebuf, "num-mac-addresses")) {
6100 prop_buf = &np->vpd.mac_num;
6101 max_len = 1;
6102 found_mask |= FOUND_MASK_NMAC;
6103 } else if (!strcmp(namebuf, "phy-type")) {
6104 prop_buf = np->vpd.phy_type;
6105 max_len = NIU_VPD_PHY_TYPE_MAX;
6106 found_mask |= FOUND_MASK_PHY;
6107 }
6108
6109 if (max_len && prop_len > max_len) {
6110 dev_err(np->device, PFX "Property '%s' length (%d) is "
6111 "too long.\n", namebuf, prop_len);
6112 return -EINVAL;
6113 }
6114
6115 if (prop_buf) {
6116 u32 off = start + 5 + err;
6117 int i;
6118
6119 niudbg(PROBE, "VPD_SCAN: Reading in property [%s] "
6120 "len[%d]\n", namebuf, prop_len);
6121 for (i = 0; i < prop_len; i++)
6122 *prop_buf++ = niu_pci_eeprom_read(np, off + i);
6123 }
6124
6125 start += len;
6126 }
6127
6128 return 0;
6129 }
6130
6131 /* ESPC_PIO_EN_ENABLE must be set */
6132 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start)
6133 {
6134 u32 offset;
6135 int err;
6136
6137 err = niu_pci_eeprom_read16_swp(np, start + 1);
6138 if (err < 0)
6139 return;
6140
6141 offset = err + 3;
6142
6143 while (start + offset < ESPC_EEPROM_SIZE) {
6144 u32 here = start + offset;
6145 u32 end;
6146
6147 err = niu_pci_eeprom_read(np, here);
6148 if (err != 0x90)
6149 return;
6150
6151 err = niu_pci_eeprom_read16_swp(np, here + 1);
6152 if (err < 0)
6153 return;
6154
6155 here = start + offset + 3;
6156 end = start + offset + err;
6157
6158 offset += err;
6159
6160 err = niu_pci_vpd_scan_props(np, here, end);
6161 if (err < 0 || err == 1)
6162 return;
6163 }
6164 }
6165
6166 /* ESPC_PIO_EN_ENABLE must be set */
6167 static u32 __devinit niu_pci_vpd_offset(struct niu *np)
6168 {
6169 u32 start = 0, end = ESPC_EEPROM_SIZE, ret;
6170 int err;
6171
6172 while (start < end) {
6173 ret = start;
6174
6175 /* ROM header signature? */
6176 err = niu_pci_eeprom_read16(np, start + 0);
6177 if (err != 0x55aa)
6178 return 0;
6179
6180 /* Apply offset to PCI data structure. */
6181 err = niu_pci_eeprom_read16(np, start + 23);
6182 if (err < 0)
6183 return 0;
6184 start += err;
6185
6186 /* Check for "PCIR" signature. */
6187 err = niu_pci_eeprom_read16(np, start + 0);
6188 if (err != 0x5043)
6189 return 0;
6190 err = niu_pci_eeprom_read16(np, start + 2);
6191 if (err != 0x4952)
6192 return 0;
6193
6194 /* Check for OBP image type. */
6195 err = niu_pci_eeprom_read(np, start + 20);
6196 if (err < 0)
6197 return 0;
6198 if (err != 0x01) {
6199 err = niu_pci_eeprom_read(np, ret + 2);
6200 if (err < 0)
6201 return 0;
6202
6203 start = ret + (err * 512);
6204 continue;
6205 }
6206
6207 err = niu_pci_eeprom_read16_swp(np, start + 8);
6208 if (err < 0)
6209 return err;
6210 ret += err;
6211
6212 err = niu_pci_eeprom_read(np, ret + 0);
6213 if (err != 0x82)
6214 return 0;
6215
6216 return ret;
6217 }
6218
6219 return 0;
6220 }
6221
6222 static int __devinit niu_phy_type_prop_decode(struct niu *np,
6223 const char *phy_prop)
6224 {
6225 if (!strcmp(phy_prop, "mif")) {
6226 /* 1G copper, MII */
6227 np->flags &= ~(NIU_FLAGS_FIBER |
6228 NIU_FLAGS_10G);
6229 np->mac_xcvr = MAC_XCVR_MII;
6230 } else if (!strcmp(phy_prop, "xgf")) {
6231 /* 10G fiber, XPCS */
6232 np->flags |= (NIU_FLAGS_10G |
6233 NIU_FLAGS_FIBER);
6234 np->mac_xcvr = MAC_XCVR_XPCS;
6235 } else if (!strcmp(phy_prop, "pcs")) {
6236 /* 1G fiber, PCS */
6237 np->flags &= ~NIU_FLAGS_10G;
6238 np->flags |= NIU_FLAGS_FIBER;
6239 np->mac_xcvr = MAC_XCVR_PCS;
6240 } else if (!strcmp(phy_prop, "xgc")) {
6241 /* 10G copper, XPCS */
6242 np->flags |= NIU_FLAGS_10G;
6243 np->flags &= ~NIU_FLAGS_FIBER;
6244 np->mac_xcvr = MAC_XCVR_XPCS;
6245 } else {
6246 return -EINVAL;
6247 }
6248 return 0;
6249 }
6250
6251 static void __devinit niu_pci_vpd_validate(struct niu *np)
6252 {
6253 struct net_device *dev = np->dev;
6254 struct niu_vpd *vpd = &np->vpd;
6255 u8 val8;
6256
6257 if (!is_valid_ether_addr(&vpd->local_mac[0])) {
6258 dev_err(np->device, PFX "VPD MAC invalid, "
6259 "falling back to SPROM.\n");
6260
6261 np->flags &= ~NIU_FLAGS_VPD_VALID;
6262 return;
6263 }
6264
6265 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
6266 dev_err(np->device, PFX "Illegal phy string [%s].\n",
6267 np->vpd.phy_type);
6268 dev_err(np->device, PFX "Falling back to SPROM.\n");
6269 np->flags &= ~NIU_FLAGS_VPD_VALID;
6270 return;
6271 }
6272
6273 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN);
6274
6275 val8 = dev->perm_addr[5];
6276 dev->perm_addr[5] += np->port;
6277 if (dev->perm_addr[5] < val8)
6278 dev->perm_addr[4]++;
6279
6280 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6281 }
6282
6283 static int __devinit niu_pci_probe_sprom(struct niu *np)
6284 {
6285 struct net_device *dev = np->dev;
6286 int len, i;
6287 u64 val, sum;
6288 u8 val8;
6289
6290 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
6291 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
6292 len = val / 4;
6293
6294 np->eeprom_len = len;
6295
6296 niudbg(PROBE, "SPROM: Image size %llu\n", (unsigned long long) val);
6297
6298 sum = 0;
6299 for (i = 0; i < len; i++) {
6300 val = nr64(ESPC_NCR(i));
6301 sum += (val >> 0) & 0xff;
6302 sum += (val >> 8) & 0xff;
6303 sum += (val >> 16) & 0xff;
6304 sum += (val >> 24) & 0xff;
6305 }
6306 niudbg(PROBE, "SPROM: Checksum %x\n", (int)(sum & 0xff));
6307 if ((sum & 0xff) != 0xab) {
6308 dev_err(np->device, PFX "Bad SPROM checksum "
6309 "(%x, should be 0xab)\n", (int) (sum & 0xff));
6310 return -EINVAL;
6311 }
6312
6313 val = nr64(ESPC_PHY_TYPE);
6314 switch (np->port) {
6315 case 0:
6316 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
6317 ESPC_PHY_TYPE_PORT0_SHIFT;
6318 break;
6319 case 1:
6320 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
6321 ESPC_PHY_TYPE_PORT1_SHIFT;
6322 break;
6323 case 2:
6324 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
6325 ESPC_PHY_TYPE_PORT2_SHIFT;
6326 break;
6327 case 3:
6328 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
6329 ESPC_PHY_TYPE_PORT3_SHIFT;
6330 break;
6331 default:
6332 dev_err(np->device, PFX "Bogus port number %u\n",
6333 np->port);
6334 return -EINVAL;
6335 }
6336 niudbg(PROBE, "SPROM: PHY type %x\n", val8);
6337
6338 switch (val8) {
6339 case ESPC_PHY_TYPE_1G_COPPER:
6340 /* 1G copper, MII */
6341 np->flags &= ~(NIU_FLAGS_FIBER |
6342 NIU_FLAGS_10G);
6343 np->mac_xcvr = MAC_XCVR_MII;
6344 break;
6345
6346 case ESPC_PHY_TYPE_1G_FIBER:
6347 /* 1G fiber, PCS */
6348 np->flags &= ~NIU_FLAGS_10G;
6349 np->flags |= NIU_FLAGS_FIBER;
6350 np->mac_xcvr = MAC_XCVR_PCS;
6351 break;
6352
6353 case ESPC_PHY_TYPE_10G_COPPER:
6354 /* 10G copper, XPCS */
6355 np->flags |= NIU_FLAGS_10G;
6356 np->flags &= ~NIU_FLAGS_FIBER;
6357 np->mac_xcvr = MAC_XCVR_XPCS;
6358 break;
6359
6360 case ESPC_PHY_TYPE_10G_FIBER:
6361 /* 10G fiber, XPCS */
6362 np->flags |= (NIU_FLAGS_10G |
6363 NIU_FLAGS_FIBER);
6364 np->mac_xcvr = MAC_XCVR_XPCS;
6365 break;
6366
6367 default:
6368 dev_err(np->device, PFX "Bogus SPROM phy type %u\n", val8);
6369 return -EINVAL;
6370 }
6371
6372 val = nr64(ESPC_MAC_ADDR0);
6373 niudbg(PROBE, "SPROM: MAC_ADDR0[%08llx]\n",
6374 (unsigned long long) val);
6375 dev->perm_addr[0] = (val >> 0) & 0xff;
6376 dev->perm_addr[1] = (val >> 8) & 0xff;
6377 dev->perm_addr[2] = (val >> 16) & 0xff;
6378 dev->perm_addr[3] = (val >> 24) & 0xff;
6379
6380 val = nr64(ESPC_MAC_ADDR1);
6381 niudbg(PROBE, "SPROM: MAC_ADDR1[%08llx]\n",
6382 (unsigned long long) val);
6383 dev->perm_addr[4] = (val >> 0) & 0xff;
6384 dev->perm_addr[5] = (val >> 8) & 0xff;
6385
6386 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
6387 dev_err(np->device, PFX "SPROM MAC address invalid\n");
6388 dev_err(np->device, PFX "[ \n");
6389 for (i = 0; i < 6; i++)
6390 printk("%02x ", dev->perm_addr[i]);
6391 printk("]\n");
6392 return -EINVAL;
6393 }
6394
6395 val8 = dev->perm_addr[5];
6396 dev->perm_addr[5] += np->port;
6397 if (dev->perm_addr[5] < val8)
6398 dev->perm_addr[4]++;
6399
6400 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
6401
6402 val = nr64(ESPC_MOD_STR_LEN);
6403 niudbg(PROBE, "SPROM: MOD_STR_LEN[%llu]\n",
6404 (unsigned long long) val);
6405 if (val >= 8 * 4)
6406 return -EINVAL;
6407
6408 for (i = 0; i < val; i += 4) {
6409 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
6410
6411 np->vpd.model[i + 3] = (tmp >> 0) & 0xff;
6412 np->vpd.model[i + 2] = (tmp >> 8) & 0xff;
6413 np->vpd.model[i + 1] = (tmp >> 16) & 0xff;
6414 np->vpd.model[i + 0] = (tmp >> 24) & 0xff;
6415 }
6416 np->vpd.model[val] = '\0';
6417
6418 val = nr64(ESPC_BD_MOD_STR_LEN);
6419 niudbg(PROBE, "SPROM: BD_MOD_STR_LEN[%llu]\n",
6420 (unsigned long long) val);
6421 if (val >= 4 * 4)
6422 return -EINVAL;
6423
6424 for (i = 0; i < val; i += 4) {
6425 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
6426
6427 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff;
6428 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff;
6429 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff;
6430 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff;
6431 }
6432 np->vpd.board_model[val] = '\0';
6433
6434 np->vpd.mac_num =
6435 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
6436 niudbg(PROBE, "SPROM: NUM_PORTS_MACS[%d]\n",
6437 np->vpd.mac_num);
6438
6439 return 0;
6440 }
6441
6442 static int __devinit niu_get_and_validate_port(struct niu *np)
6443 {
6444 struct niu_parent *parent = np->parent;
6445
6446 if (np->port <= 1)
6447 np->flags |= NIU_FLAGS_XMAC;
6448
6449 if (!parent->num_ports) {
6450 if (parent->plat_type == PLAT_TYPE_NIU) {
6451 parent->num_ports = 2;
6452 } else {
6453 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &
6454 ESPC_NUM_PORTS_MACS_VAL;
6455
6456 if (!parent->num_ports)
6457 parent->num_ports = 4;
6458 }
6459 }
6460
6461 niudbg(PROBE, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
6462 np->port, parent->num_ports);
6463 if (np->port >= parent->num_ports)
6464 return -ENODEV;
6465
6466 return 0;
6467 }
6468
6469 static int __devinit phy_record(struct niu_parent *parent,
6470 struct phy_probe_info *p,
6471 int dev_id_1, int dev_id_2, u8 phy_port,
6472 int type)
6473 {
6474 u32 id = (dev_id_1 << 16) | dev_id_2;
6475 u8 idx;
6476
6477 if (dev_id_1 < 0 || dev_id_2 < 0)
6478 return 0;
6479 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) {
6480 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) &&
6481 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011))
6482 return 0;
6483 } else {
6484 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R)
6485 return 0;
6486 }
6487
6488 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
6489 parent->index, id,
6490 (type == PHY_TYPE_PMA_PMD ?
6491 "PMA/PMD" :
6492 (type == PHY_TYPE_PCS ?
6493 "PCS" : "MII")),
6494 phy_port);
6495
6496 if (p->cur[type] >= NIU_MAX_PORTS) {
6497 printk(KERN_ERR PFX "Too many PHY ports.\n");
6498 return -EINVAL;
6499 }
6500 idx = p->cur[type];
6501 p->phy_id[type][idx] = id;
6502 p->phy_port[type][idx] = phy_port;
6503 p->cur[type] = idx + 1;
6504 return 0;
6505 }
6506
6507 static int __devinit port_has_10g(struct phy_probe_info *p, int port)
6508 {
6509 int i;
6510
6511 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) {
6512 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
6513 return 1;
6514 }
6515 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) {
6516 if (p->phy_port[PHY_TYPE_PCS][i] == port)
6517 return 1;
6518 }
6519
6520 return 0;
6521 }
6522
6523 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest)
6524 {
6525 int port, cnt;
6526
6527 cnt = 0;
6528 *lowest = 32;
6529 for (port = 8; port < 32; port++) {
6530 if (port_has_10g(p, port)) {
6531 if (!cnt)
6532 *lowest = port;
6533 cnt++;
6534 }
6535 }
6536
6537 return cnt;
6538 }
6539
6540 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest)
6541 {
6542 *lowest = 32;
6543 if (p->cur[PHY_TYPE_MII])
6544 *lowest = p->phy_port[PHY_TYPE_MII][0];
6545
6546 return p->cur[PHY_TYPE_MII];
6547 }
6548
6549 static void __devinit niu_n2_divide_channels(struct niu_parent *parent)
6550 {
6551 int num_ports = parent->num_ports;
6552 int i;
6553
6554 for (i = 0; i < num_ports; i++) {
6555 parent->rxchan_per_port[i] = (16 / num_ports);
6556 parent->txchan_per_port[i] = (16 / num_ports);
6557
6558 pr_info(PFX "niu%d: Port %u [%u RX chans] "
6559 "[%u TX chans]\n",
6560 parent->index, i,
6561 parent->rxchan_per_port[i],
6562 parent->txchan_per_port[i]);
6563 }
6564 }
6565
6566 static void __devinit niu_divide_channels(struct niu_parent *parent,
6567 int num_10g, int num_1g)
6568 {
6569 int num_ports = parent->num_ports;
6570 int rx_chans_per_10g, rx_chans_per_1g;
6571 int tx_chans_per_10g, tx_chans_per_1g;
6572 int i, tot_rx, tot_tx;
6573
6574 if (!num_10g || !num_1g) {
6575 rx_chans_per_10g = rx_chans_per_1g =
6576 (NIU_NUM_RXCHAN / num_ports);
6577 tx_chans_per_10g = tx_chans_per_1g =
6578 (NIU_NUM_TXCHAN / num_ports);
6579 } else {
6580 rx_chans_per_1g = NIU_NUM_RXCHAN / 8;
6581 rx_chans_per_10g = (NIU_NUM_RXCHAN -
6582 (rx_chans_per_1g * num_1g)) /
6583 num_10g;
6584
6585 tx_chans_per_1g = NIU_NUM_TXCHAN / 6;
6586 tx_chans_per_10g = (NIU_NUM_TXCHAN -
6587 (tx_chans_per_1g * num_1g)) /
6588 num_10g;
6589 }
6590
6591 tot_rx = tot_tx = 0;
6592 for (i = 0; i < num_ports; i++) {
6593 int type = phy_decode(parent->port_phy, i);
6594
6595 if (type == PORT_TYPE_10G) {
6596 parent->rxchan_per_port[i] = rx_chans_per_10g;
6597 parent->txchan_per_port[i] = tx_chans_per_10g;
6598 } else {
6599 parent->rxchan_per_port[i] = rx_chans_per_1g;
6600 parent->txchan_per_port[i] = tx_chans_per_1g;
6601 }
6602 pr_info(PFX "niu%d: Port %u [%u RX chans] "
6603 "[%u TX chans]\n",
6604 parent->index, i,
6605 parent->rxchan_per_port[i],
6606 parent->txchan_per_port[i]);
6607 tot_rx += parent->rxchan_per_port[i];
6608 tot_tx += parent->txchan_per_port[i];
6609 }
6610
6611 if (tot_rx > NIU_NUM_RXCHAN) {
6612 printk(KERN_ERR PFX "niu%d: Too many RX channels (%d), "
6613 "resetting to one per port.\n",
6614 parent->index, tot_rx);
6615 for (i = 0; i < num_ports; i++)
6616 parent->rxchan_per_port[i] = 1;
6617 }
6618 if (tot_tx > NIU_NUM_TXCHAN) {
6619 printk(KERN_ERR PFX "niu%d: Too many TX channels (%d), "
6620 "resetting to one per port.\n",
6621 parent->index, tot_tx);
6622 for (i = 0; i < num_ports; i++)
6623 parent->txchan_per_port[i] = 1;
6624 }
6625 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) {
6626 printk(KERN_WARNING PFX "niu%d: Driver bug, wasted channels, "
6627 "RX[%d] TX[%d]\n",
6628 parent->index, tot_rx, tot_tx);
6629 }
6630 }
6631
6632 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent,
6633 int num_10g, int num_1g)
6634 {
6635 int i, num_ports = parent->num_ports;
6636 int rdc_group, rdc_groups_per_port;
6637 int rdc_channel_base;
6638
6639 rdc_group = 0;
6640 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports;
6641
6642 rdc_channel_base = 0;
6643
6644 for (i = 0; i < num_ports; i++) {
6645 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i];
6646 int grp, num_channels = parent->rxchan_per_port[i];
6647 int this_channel_offset;
6648
6649 tp->first_table_num = rdc_group;
6650 tp->num_tables = rdc_groups_per_port;
6651 this_channel_offset = 0;
6652 for (grp = 0; grp < tp->num_tables; grp++) {
6653 struct rdc_table *rt = &tp->tables[grp];
6654 int slot;
6655
6656 pr_info(PFX "niu%d: Port %d RDC tbl(%d) [ ",
6657 parent->index, i, tp->first_table_num + grp);
6658 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) {
6659 rt->rxdma_channel[slot] =
6660 rdc_channel_base + this_channel_offset;
6661
6662 printk("%d ", rt->rxdma_channel[slot]);
6663
6664 if (++this_channel_offset == num_channels)
6665 this_channel_offset = 0;
6666 }
6667 printk("]\n");
6668 }
6669
6670 parent->rdc_default[i] = rdc_channel_base;
6671
6672 rdc_channel_base += num_channels;
6673 rdc_group += rdc_groups_per_port;
6674 }
6675 }
6676
6677 static int __devinit fill_phy_probe_info(struct niu *np,
6678 struct niu_parent *parent,
6679 struct phy_probe_info *info)
6680 {
6681 unsigned long flags;
6682 int port, err;
6683
6684 memset(info, 0, sizeof(*info));
6685
6686 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
6687 niu_lock_parent(np, flags);
6688 err = 0;
6689 for (port = 8; port < 32; port++) {
6690 int dev_id_1, dev_id_2;
6691
6692 dev_id_1 = mdio_read(np, port,
6693 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1);
6694 dev_id_2 = mdio_read(np, port,
6695 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2);
6696 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6697 PHY_TYPE_PMA_PMD);
6698 if (err)
6699 break;
6700 dev_id_1 = mdio_read(np, port,
6701 NIU_PCS_DEV_ADDR, MII_PHYSID1);
6702 dev_id_2 = mdio_read(np, port,
6703 NIU_PCS_DEV_ADDR, MII_PHYSID2);
6704 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6705 PHY_TYPE_PCS);
6706 if (err)
6707 break;
6708 dev_id_1 = mii_read(np, port, MII_PHYSID1);
6709 dev_id_2 = mii_read(np, port, MII_PHYSID2);
6710 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
6711 PHY_TYPE_MII);
6712 if (err)
6713 break;
6714 }
6715 niu_unlock_parent(np, flags);
6716
6717 return err;
6718 }
6719
6720 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent)
6721 {
6722 struct phy_probe_info *info = &parent->phy_probe_info;
6723 int lowest_10g, lowest_1g;
6724 int num_10g, num_1g;
6725 u32 val;
6726 int err;
6727
6728 err = fill_phy_probe_info(np, parent, info);
6729 if (err)
6730 return err;
6731
6732 num_10g = count_10g_ports(info, &lowest_10g);
6733 num_1g = count_1g_ports(info, &lowest_1g);
6734
6735 switch ((num_10g << 4) | num_1g) {
6736 case 0x24:
6737 if (lowest_1g == 10)
6738 parent->plat_type = PLAT_TYPE_VF_P0;
6739 else if (lowest_1g == 26)
6740 parent->plat_type = PLAT_TYPE_VF_P1;
6741 else
6742 goto unknown_vg_1g_port;
6743
6744 /* fallthru */
6745 case 0x22:
6746 val = (phy_encode(PORT_TYPE_10G, 0) |
6747 phy_encode(PORT_TYPE_10G, 1) |
6748 phy_encode(PORT_TYPE_1G, 2) |
6749 phy_encode(PORT_TYPE_1G, 3));
6750 break;
6751
6752 case 0x20:
6753 val = (phy_encode(PORT_TYPE_10G, 0) |
6754 phy_encode(PORT_TYPE_10G, 1));
6755 break;
6756
6757 case 0x10:
6758 val = phy_encode(PORT_TYPE_10G, np->port);
6759 break;
6760
6761 case 0x14:
6762 if (lowest_1g == 10)
6763 parent->plat_type = PLAT_TYPE_VF_P0;
6764 else if (lowest_1g == 26)
6765 parent->plat_type = PLAT_TYPE_VF_P1;
6766 else
6767 goto unknown_vg_1g_port;
6768
6769 /* fallthru */
6770 case 0x13:
6771 if ((lowest_10g & 0x7) == 0)
6772 val = (phy_encode(PORT_TYPE_10G, 0) |
6773 phy_encode(PORT_TYPE_1G, 1) |
6774 phy_encode(PORT_TYPE_1G, 2) |
6775 phy_encode(PORT_TYPE_1G, 3));
6776 else
6777 val = (phy_encode(PORT_TYPE_1G, 0) |
6778 phy_encode(PORT_TYPE_10G, 1) |
6779 phy_encode(PORT_TYPE_1G, 2) |
6780 phy_encode(PORT_TYPE_1G, 3));
6781 break;
6782
6783 case 0x04:
6784 if (lowest_1g == 10)
6785 parent->plat_type = PLAT_TYPE_VF_P0;
6786 else if (lowest_1g == 26)
6787 parent->plat_type = PLAT_TYPE_VF_P1;
6788 else
6789 goto unknown_vg_1g_port;
6790
6791 val = (phy_encode(PORT_TYPE_1G, 0) |
6792 phy_encode(PORT_TYPE_1G, 1) |
6793 phy_encode(PORT_TYPE_1G, 2) |
6794 phy_encode(PORT_TYPE_1G, 3));
6795 break;
6796
6797 default:
6798 printk(KERN_ERR PFX "Unsupported port config "
6799 "10G[%d] 1G[%d]\n",
6800 num_10g, num_1g);
6801 return -EINVAL;
6802 }
6803
6804 parent->port_phy = val;
6805
6806 if (parent->plat_type == PLAT_TYPE_NIU)
6807 niu_n2_divide_channels(parent);
6808 else
6809 niu_divide_channels(parent, num_10g, num_1g);
6810
6811 niu_divide_rdc_groups(parent, num_10g, num_1g);
6812
6813 return 0;
6814
6815 unknown_vg_1g_port:
6816 printk(KERN_ERR PFX "Cannot identify platform type, 1gport=%d\n",
6817 lowest_1g);
6818 return -EINVAL;
6819 }
6820
6821 static int __devinit niu_probe_ports(struct niu *np)
6822 {
6823 struct niu_parent *parent = np->parent;
6824 int err, i;
6825
6826 niudbg(PROBE, "niu_probe_ports(): port_phy[%08x]\n",
6827 parent->port_phy);
6828
6829 if (parent->port_phy == PORT_PHY_UNKNOWN) {
6830 err = walk_phys(np, parent);
6831 if (err)
6832 return err;
6833
6834 niu_set_ldg_timer_res(np, 2);
6835 for (i = 0; i <= LDN_MAX; i++)
6836 niu_ldn_irq_enable(np, i, 0);
6837 }
6838
6839 if (parent->port_phy == PORT_PHY_INVALID)
6840 return -EINVAL;
6841
6842 return 0;
6843 }
6844
6845 static int __devinit niu_classifier_swstate_init(struct niu *np)
6846 {
6847 struct niu_classifier *cp = &np->clas;
6848
6849 niudbg(PROBE, "niu_classifier_swstate_init: num_tcam(%d)\n",
6850 np->parent->tcam_num_entries);
6851
6852 cp->tcam_index = (u16) np->port;
6853 cp->h1_init = 0xffffffff;
6854 cp->h2_init = 0xffff;
6855
6856 return fflp_early_init(np);
6857 }
6858
6859 static void __devinit niu_link_config_init(struct niu *np)
6860 {
6861 struct niu_link_config *lp = &np->link_config;
6862
6863 lp->advertising = (ADVERTISED_10baseT_Half |
6864 ADVERTISED_10baseT_Full |
6865 ADVERTISED_100baseT_Half |
6866 ADVERTISED_100baseT_Full |
6867 ADVERTISED_1000baseT_Half |
6868 ADVERTISED_1000baseT_Full |
6869 ADVERTISED_10000baseT_Full |
6870 ADVERTISED_Autoneg);
6871 lp->speed = lp->active_speed = SPEED_INVALID;
6872 lp->duplex = lp->active_duplex = DUPLEX_INVALID;
6873 #if 0
6874 lp->loopback_mode = LOOPBACK_MAC;
6875 lp->active_speed = SPEED_10000;
6876 lp->active_duplex = DUPLEX_FULL;
6877 #else
6878 lp->loopback_mode = LOOPBACK_DISABLED;
6879 #endif
6880 }
6881
6882 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np)
6883 {
6884 switch (np->port) {
6885 case 0:
6886 np->mac_regs = np->regs + XMAC_PORT0_OFF;
6887 np->ipp_off = 0x00000;
6888 np->pcs_off = 0x04000;
6889 np->xpcs_off = 0x02000;
6890 break;
6891
6892 case 1:
6893 np->mac_regs = np->regs + XMAC_PORT1_OFF;
6894 np->ipp_off = 0x08000;
6895 np->pcs_off = 0x0a000;
6896 np->xpcs_off = 0x08000;
6897 break;
6898
6899 case 2:
6900 np->mac_regs = np->regs + BMAC_PORT2_OFF;
6901 np->ipp_off = 0x04000;
6902 np->pcs_off = 0x0e000;
6903 np->xpcs_off = ~0UL;
6904 break;
6905
6906 case 3:
6907 np->mac_regs = np->regs + BMAC_PORT3_OFF;
6908 np->ipp_off = 0x0c000;
6909 np->pcs_off = 0x12000;
6910 np->xpcs_off = ~0UL;
6911 break;
6912
6913 default:
6914 dev_err(np->device, PFX "Port %u is invalid, cannot "
6915 "compute MAC block offset.\n", np->port);
6916 return -EINVAL;
6917 }
6918
6919 return 0;
6920 }
6921
6922 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map)
6923 {
6924 struct msix_entry msi_vec[NIU_NUM_LDG];
6925 struct niu_parent *parent = np->parent;
6926 struct pci_dev *pdev = np->pdev;
6927 int i, num_irqs, err;
6928 u8 first_ldg;
6929
6930 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
6931 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++)
6932 ldg_num_map[i] = first_ldg + i;
6933
6934 num_irqs = (parent->rxchan_per_port[np->port] +
6935 parent->txchan_per_port[np->port] +
6936 (np->port == 0 ? 3 : 1));
6937 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports));
6938
6939 retry:
6940 for (i = 0; i < num_irqs; i++) {
6941 msi_vec[i].vector = 0;
6942 msi_vec[i].entry = i;
6943 }
6944
6945 err = pci_enable_msix(pdev, msi_vec, num_irqs);
6946 if (err < 0) {
6947 np->flags &= ~NIU_FLAGS_MSIX;
6948 return;
6949 }
6950 if (err > 0) {
6951 num_irqs = err;
6952 goto retry;
6953 }
6954
6955 np->flags |= NIU_FLAGS_MSIX;
6956 for (i = 0; i < num_irqs; i++)
6957 np->ldg[i].irq = msi_vec[i].vector;
6958 np->num_ldg = num_irqs;
6959 }
6960
6961 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map)
6962 {
6963 #ifdef CONFIG_SPARC64
6964 struct of_device *op = np->op;
6965 const u32 *int_prop;
6966 int i;
6967
6968 int_prop = of_get_property(op->node, "interrupts", NULL);
6969 if (!int_prop)
6970 return -ENODEV;
6971
6972 for (i = 0; i < op->num_irqs; i++) {
6973 ldg_num_map[i] = int_prop[i];
6974 np->ldg[i].irq = op->irqs[i];
6975 }
6976
6977 np->num_ldg = op->num_irqs;
6978
6979 return 0;
6980 #else
6981 return -EINVAL;
6982 #endif
6983 }
6984
6985 static int __devinit niu_ldg_init(struct niu *np)
6986 {
6987 struct niu_parent *parent = np->parent;
6988 u8 ldg_num_map[NIU_NUM_LDG];
6989 int first_chan, num_chan;
6990 int i, err, ldg_rotor;
6991 u8 port;
6992
6993 np->num_ldg = 1;
6994 np->ldg[0].irq = np->dev->irq;
6995 if (parent->plat_type == PLAT_TYPE_NIU) {
6996 err = niu_n2_irq_init(np, ldg_num_map);
6997 if (err)
6998 return err;
6999 } else
7000 niu_try_msix(np, ldg_num_map);
7001
7002 port = np->port;
7003 for (i = 0; i < np->num_ldg; i++) {
7004 struct niu_ldg *lp = &np->ldg[i];
7005
7006 netif_napi_add(np->dev, &lp->napi, niu_poll, 64);
7007
7008 lp->np = np;
7009 lp->ldg_num = ldg_num_map[i];
7010 lp->timer = 2; /* XXX */
7011
7012 /* On N2 NIU the firmware has setup the SID mappings so they go
7013 * to the correct values that will route the LDG to the proper
7014 * interrupt in the NCU interrupt table.
7015 */
7016 if (np->parent->plat_type != PLAT_TYPE_NIU) {
7017 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
7018 if (err)
7019 return err;
7020 }
7021 }
7022
7023 /* We adopt the LDG assignment ordering used by the N2 NIU
7024 * 'interrupt' properties because that simplifies a lot of
7025 * things. This ordering is:
7026 *
7027 * MAC
7028 * MIF (if port zero)
7029 * SYSERR (if port zero)
7030 * RX channels
7031 * TX channels
7032 */
7033
7034 ldg_rotor = 0;
7035
7036 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
7037 LDN_MAC(port));
7038 if (err)
7039 return err;
7040
7041 ldg_rotor++;
7042 if (ldg_rotor == np->num_ldg)
7043 ldg_rotor = 0;
7044
7045 if (port == 0) {
7046 err = niu_ldg_assign_ldn(np, parent,
7047 ldg_num_map[ldg_rotor],
7048 LDN_MIF);
7049 if (err)
7050 return err;
7051
7052 ldg_rotor++;
7053 if (ldg_rotor == np->num_ldg)
7054 ldg_rotor = 0;
7055
7056 err = niu_ldg_assign_ldn(np, parent,
7057 ldg_num_map[ldg_rotor],
7058 LDN_DEVICE_ERROR);
7059 if (err)
7060 return err;
7061
7062 ldg_rotor++;
7063 if (ldg_rotor == np->num_ldg)
7064 ldg_rotor = 0;
7065
7066 }
7067
7068 first_chan = 0;
7069 for (i = 0; i < port; i++)
7070 first_chan += parent->rxchan_per_port[port];
7071 num_chan = parent->rxchan_per_port[port];
7072
7073 for (i = first_chan; i < (first_chan + num_chan); i++) {
7074 err = niu_ldg_assign_ldn(np, parent,
7075 ldg_num_map[ldg_rotor],
7076 LDN_RXDMA(i));
7077 if (err)
7078 return err;
7079 ldg_rotor++;
7080 if (ldg_rotor == np->num_ldg)
7081 ldg_rotor = 0;
7082 }
7083
7084 first_chan = 0;
7085 for (i = 0; i < port; i++)
7086 first_chan += parent->txchan_per_port[port];
7087 num_chan = parent->txchan_per_port[port];
7088 for (i = first_chan; i < (first_chan + num_chan); i++) {
7089 err = niu_ldg_assign_ldn(np, parent,
7090 ldg_num_map[ldg_rotor],
7091 LDN_TXDMA(i));
7092 if (err)
7093 return err;
7094 ldg_rotor++;
7095 if (ldg_rotor == np->num_ldg)
7096 ldg_rotor = 0;
7097 }
7098
7099 return 0;
7100 }
7101
7102 static void __devexit niu_ldg_free(struct niu *np)
7103 {
7104 if (np->flags & NIU_FLAGS_MSIX)
7105 pci_disable_msix(np->pdev);
7106 }
7107
7108 static int __devinit niu_get_of_props(struct niu *np)
7109 {
7110 #ifdef CONFIG_SPARC64
7111 struct net_device *dev = np->dev;
7112 struct device_node *dp;
7113 const char *phy_type;
7114 const u8 *mac_addr;
7115 int prop_len;
7116
7117 if (np->parent->plat_type == PLAT_TYPE_NIU)
7118 dp = np->op->node;
7119 else
7120 dp = pci_device_to_OF_node(np->pdev);
7121
7122 phy_type = of_get_property(dp, "phy-type", &prop_len);
7123 if (!phy_type) {
7124 dev_err(np->device, PFX "%s: OF node lacks "
7125 "phy-type property\n",
7126 dp->full_name);
7127 return -EINVAL;
7128 }
7129
7130 if (!strcmp(phy_type, "none"))
7131 return -ENODEV;
7132
7133 strcpy(np->vpd.phy_type, phy_type);
7134
7135 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) {
7136 dev_err(np->device, PFX "%s: Illegal phy string [%s].\n",
7137 dp->full_name, np->vpd.phy_type);
7138 return -EINVAL;
7139 }
7140
7141 mac_addr = of_get_property(dp, "local-mac-address", &prop_len);
7142 if (!mac_addr) {
7143 dev_err(np->device, PFX "%s: OF node lacks "
7144 "local-mac-address property\n",
7145 dp->full_name);
7146 return -EINVAL;
7147 }
7148 if (prop_len != dev->addr_len) {
7149 dev_err(np->device, PFX "%s: OF MAC address prop len (%d) "
7150 "is wrong.\n",
7151 dp->full_name, prop_len);
7152 }
7153 memcpy(dev->perm_addr, mac_addr, dev->addr_len);
7154 if (!is_valid_ether_addr(&dev->perm_addr[0])) {
7155 int i;
7156
7157 dev_err(np->device, PFX "%s: OF MAC address is invalid\n",
7158 dp->full_name);
7159 dev_err(np->device, PFX "%s: [ \n",
7160 dp->full_name);
7161 for (i = 0; i < 6; i++)
7162 printk("%02x ", dev->perm_addr[i]);
7163 printk("]\n");
7164 return -EINVAL;
7165 }
7166
7167 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len);
7168
7169 return 0;
7170 #else
7171 return -EINVAL;
7172 #endif
7173 }
7174
7175 static int __devinit niu_get_invariants(struct niu *np)
7176 {
7177 int err, have_props;
7178 u32 offset;
7179
7180 err = niu_get_of_props(np);
7181 if (err == -ENODEV)
7182 return err;
7183
7184 have_props = !err;
7185
7186 err = niu_get_and_validate_port(np);
7187 if (err)
7188 return err;
7189
7190 err = niu_init_mac_ipp_pcs_base(np);
7191 if (err)
7192 return err;
7193
7194 if (!have_props) {
7195 if (np->parent->plat_type == PLAT_TYPE_NIU)
7196 return -EINVAL;
7197
7198 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
7199 offset = niu_pci_vpd_offset(np);
7200 niudbg(PROBE, "niu_get_invariants: VPD offset [%08x]\n",
7201 offset);
7202 if (offset)
7203 niu_pci_vpd_fetch(np, offset);
7204 nw64(ESPC_PIO_EN, 0);
7205
7206 if (np->flags & NIU_FLAGS_VPD_VALID)
7207 niu_pci_vpd_validate(np);
7208
7209 if (!(np->flags & NIU_FLAGS_VPD_VALID)) {
7210 err = niu_pci_probe_sprom(np);
7211 if (err)
7212 return err;
7213 }
7214 }
7215
7216 err = niu_probe_ports(np);
7217 if (err)
7218 return err;
7219
7220 niu_ldg_init(np);
7221
7222 niu_classifier_swstate_init(np);
7223 niu_link_config_init(np);
7224
7225 err = niu_determine_phy_disposition(np);
7226 if (!err)
7227 err = niu_init_link(np);
7228
7229 return err;
7230 }
7231
7232 static LIST_HEAD(niu_parent_list);
7233 static DEFINE_MUTEX(niu_parent_lock);
7234 static int niu_parent_index;
7235
7236 static ssize_t show_port_phy(struct device *dev,
7237 struct device_attribute *attr, char *buf)
7238 {
7239 struct platform_device *plat_dev = to_platform_device(dev);
7240 struct niu_parent *p = plat_dev->dev.platform_data;
7241 u32 port_phy = p->port_phy;
7242 char *orig_buf = buf;
7243 int i;
7244
7245 if (port_phy == PORT_PHY_UNKNOWN ||
7246 port_phy == PORT_PHY_INVALID)
7247 return 0;
7248
7249 for (i = 0; i < p->num_ports; i++) {
7250 const char *type_str;
7251 int type;
7252
7253 type = phy_decode(port_phy, i);
7254 if (type == PORT_TYPE_10G)
7255 type_str = "10G";
7256 else
7257 type_str = "1G";
7258 buf += sprintf(buf,
7259 (i == 0) ? "%s" : " %s",
7260 type_str);
7261 }
7262 buf += sprintf(buf, "\n");
7263 return buf - orig_buf;
7264 }
7265
7266 static ssize_t show_plat_type(struct device *dev,
7267 struct device_attribute *attr, char *buf)
7268 {
7269 struct platform_device *plat_dev = to_platform_device(dev);
7270 struct niu_parent *p = plat_dev->dev.platform_data;
7271 const char *type_str;
7272
7273 switch (p->plat_type) {
7274 case PLAT_TYPE_ATLAS:
7275 type_str = "atlas";
7276 break;
7277 case PLAT_TYPE_NIU:
7278 type_str = "niu";
7279 break;
7280 case PLAT_TYPE_VF_P0:
7281 type_str = "vf_p0";
7282 break;
7283 case PLAT_TYPE_VF_P1:
7284 type_str = "vf_p1";
7285 break;
7286 default:
7287 type_str = "unknown";
7288 break;
7289 }
7290
7291 return sprintf(buf, "%s\n", type_str);
7292 }
7293
7294 static ssize_t __show_chan_per_port(struct device *dev,
7295 struct device_attribute *attr, char *buf,
7296 int rx)
7297 {
7298 struct platform_device *plat_dev = to_platform_device(dev);
7299 struct niu_parent *p = plat_dev->dev.platform_data;
7300 char *orig_buf = buf;
7301 u8 *arr;
7302 int i;
7303
7304 arr = (rx ? p->rxchan_per_port : p->txchan_per_port);
7305
7306 for (i = 0; i < p->num_ports; i++) {
7307 buf += sprintf(buf,
7308 (i == 0) ? "%d" : " %d",
7309 arr[i]);
7310 }
7311 buf += sprintf(buf, "\n");
7312
7313 return buf - orig_buf;
7314 }
7315
7316 static ssize_t show_rxchan_per_port(struct device *dev,
7317 struct device_attribute *attr, char *buf)
7318 {
7319 return __show_chan_per_port(dev, attr, buf, 1);
7320 }
7321
7322 static ssize_t show_txchan_per_port(struct device *dev,
7323 struct device_attribute *attr, char *buf)
7324 {
7325 return __show_chan_per_port(dev, attr, buf, 1);
7326 }
7327
7328 static ssize_t show_num_ports(struct device *dev,
7329 struct device_attribute *attr, char *buf)
7330 {
7331 struct platform_device *plat_dev = to_platform_device(dev);
7332 struct niu_parent *p = plat_dev->dev.platform_data;
7333
7334 return sprintf(buf, "%d\n", p->num_ports);
7335 }
7336
7337 static struct device_attribute niu_parent_attributes[] = {
7338 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL),
7339 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL),
7340 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL),
7341 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL),
7342 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL),
7343 {}
7344 };
7345
7346 static struct niu_parent * __devinit niu_new_parent(struct niu *np,
7347 union niu_parent_id *id,
7348 u8 ptype)
7349 {
7350 struct platform_device *plat_dev;
7351 struct niu_parent *p;
7352 int i;
7353
7354 niudbg(PROBE, "niu_new_parent: Creating new parent.\n");
7355
7356 plat_dev = platform_device_register_simple("niu", niu_parent_index,
7357 NULL, 0);
7358 if (!plat_dev)
7359 return NULL;
7360
7361 for (i = 0; attr_name(niu_parent_attributes[i]); i++) {
7362 int err = device_create_file(&plat_dev->dev,
7363 &niu_parent_attributes[i]);
7364 if (err)
7365 goto fail_unregister;
7366 }
7367
7368 p = kzalloc(sizeof(*p), GFP_KERNEL);
7369 if (!p)
7370 goto fail_unregister;
7371
7372 p->index = niu_parent_index++;
7373
7374 plat_dev->dev.platform_data = p;
7375 p->plat_dev = plat_dev;
7376
7377 memcpy(&p->id, id, sizeof(*id));
7378 p->plat_type = ptype;
7379 INIT_LIST_HEAD(&p->list);
7380 atomic_set(&p->refcnt, 0);
7381 list_add(&p->list, &niu_parent_list);
7382 spin_lock_init(&p->lock);
7383
7384 p->rxdma_clock_divider = 7500;
7385
7386 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES;
7387 if (p->plat_type == PLAT_TYPE_NIU)
7388 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES;
7389
7390 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) {
7391 int index = i - CLASS_CODE_USER_PROG1;
7392
7393 p->tcam_key[index] = TCAM_KEY_TSEL;
7394 p->flow_key[index] = (FLOW_KEY_IPSA |
7395 FLOW_KEY_IPDA |
7396 FLOW_KEY_PROTO |
7397 (FLOW_KEY_L4_BYTE12 <<
7398 FLOW_KEY_L4_0_SHIFT) |
7399 (FLOW_KEY_L4_BYTE12 <<
7400 FLOW_KEY_L4_1_SHIFT));
7401 }
7402
7403 for (i = 0; i < LDN_MAX + 1; i++)
7404 p->ldg_map[i] = LDG_INVALID;
7405
7406 return p;
7407
7408 fail_unregister:
7409 platform_device_unregister(plat_dev);
7410 return NULL;
7411 }
7412
7413 static struct niu_parent * __devinit niu_get_parent(struct niu *np,
7414 union niu_parent_id *id,
7415 u8 ptype)
7416 {
7417 struct niu_parent *p, *tmp;
7418 int port = np->port;
7419
7420 niudbg(PROBE, "niu_get_parent: platform_type[%u] port[%u]\n",
7421 ptype, port);
7422
7423 mutex_lock(&niu_parent_lock);
7424 p = NULL;
7425 list_for_each_entry(tmp, &niu_parent_list, list) {
7426 if (!memcmp(id, &tmp->id, sizeof(*id))) {
7427 p = tmp;
7428 break;
7429 }
7430 }
7431 if (!p)
7432 p = niu_new_parent(np, id, ptype);
7433
7434 if (p) {
7435 char port_name[6];
7436 int err;
7437
7438 sprintf(port_name, "port%d", port);
7439 err = sysfs_create_link(&p->plat_dev->dev.kobj,
7440 &np->device->kobj,
7441 port_name);
7442 if (!err) {
7443 p->ports[port] = np;
7444 atomic_inc(&p->refcnt);
7445 }
7446 }
7447 mutex_unlock(&niu_parent_lock);
7448
7449 return p;
7450 }
7451
7452 static void niu_put_parent(struct niu *np)
7453 {
7454 struct niu_parent *p = np->parent;
7455 u8 port = np->port;
7456 char port_name[6];
7457
7458 BUG_ON(!p || p->ports[port] != np);
7459
7460 niudbg(PROBE, "niu_put_parent: port[%u]\n", port);
7461
7462 sprintf(port_name, "port%d", port);
7463
7464 mutex_lock(&niu_parent_lock);
7465
7466 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name);
7467
7468 p->ports[port] = NULL;
7469 np->parent = NULL;
7470
7471 if (atomic_dec_and_test(&p->refcnt)) {
7472 list_del(&p->list);
7473 platform_device_unregister(p->plat_dev);
7474 }
7475
7476 mutex_unlock(&niu_parent_lock);
7477 }
7478
7479 static void *niu_pci_alloc_coherent(struct device *dev, size_t size,
7480 u64 *handle, gfp_t flag)
7481 {
7482 dma_addr_t dh;
7483 void *ret;
7484
7485 ret = dma_alloc_coherent(dev, size, &dh, flag);
7486 if (ret)
7487 *handle = dh;
7488 return ret;
7489 }
7490
7491 static void niu_pci_free_coherent(struct device *dev, size_t size,
7492 void *cpu_addr, u64 handle)
7493 {
7494 dma_free_coherent(dev, size, cpu_addr, handle);
7495 }
7496
7497 static u64 niu_pci_map_page(struct device *dev, struct page *page,
7498 unsigned long offset, size_t size,
7499 enum dma_data_direction direction)
7500 {
7501 return dma_map_page(dev, page, offset, size, direction);
7502 }
7503
7504 static void niu_pci_unmap_page(struct device *dev, u64 dma_address,
7505 size_t size, enum dma_data_direction direction)
7506 {
7507 return dma_unmap_page(dev, dma_address, size, direction);
7508 }
7509
7510 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr,
7511 size_t size,
7512 enum dma_data_direction direction)
7513 {
7514 return dma_map_single(dev, cpu_addr, size, direction);
7515 }
7516
7517 static void niu_pci_unmap_single(struct device *dev, u64 dma_address,
7518 size_t size,
7519 enum dma_data_direction direction)
7520 {
7521 dma_unmap_single(dev, dma_address, size, direction);
7522 }
7523
7524 static const struct niu_ops niu_pci_ops = {
7525 .alloc_coherent = niu_pci_alloc_coherent,
7526 .free_coherent = niu_pci_free_coherent,
7527 .map_page = niu_pci_map_page,
7528 .unmap_page = niu_pci_unmap_page,
7529 .map_single = niu_pci_map_single,
7530 .unmap_single = niu_pci_unmap_single,
7531 };
7532
7533 static void __devinit niu_driver_version(void)
7534 {
7535 static int niu_version_printed;
7536
7537 if (niu_version_printed++ == 0)
7538 pr_info("%s", version);
7539 }
7540
7541 static struct net_device * __devinit niu_alloc_and_init(
7542 struct device *gen_dev, struct pci_dev *pdev,
7543 struct of_device *op, const struct niu_ops *ops,
7544 u8 port)
7545 {
7546 struct net_device *dev = alloc_etherdev(sizeof(struct niu));
7547 struct niu *np;
7548
7549 if (!dev) {
7550 dev_err(gen_dev, PFX "Etherdev alloc failed, aborting.\n");
7551 return NULL;
7552 }
7553
7554 SET_NETDEV_DEV(dev, gen_dev);
7555
7556 np = netdev_priv(dev);
7557 np->dev = dev;
7558 np->pdev = pdev;
7559 np->op = op;
7560 np->device = gen_dev;
7561 np->ops = ops;
7562
7563 np->msg_enable = niu_debug;
7564
7565 spin_lock_init(&np->lock);
7566 INIT_WORK(&np->reset_task, niu_reset_task);
7567
7568 np->port = port;
7569
7570 return dev;
7571 }
7572
7573 static void __devinit niu_assign_netdev_ops(struct net_device *dev)
7574 {
7575 dev->open = niu_open;
7576 dev->stop = niu_close;
7577 dev->get_stats = niu_get_stats;
7578 dev->set_multicast_list = niu_set_rx_mode;
7579 dev->set_mac_address = niu_set_mac_addr;
7580 dev->do_ioctl = niu_ioctl;
7581 dev->tx_timeout = niu_tx_timeout;
7582 dev->hard_start_xmit = niu_start_xmit;
7583 dev->ethtool_ops = &niu_ethtool_ops;
7584 dev->watchdog_timeo = NIU_TX_TIMEOUT;
7585 dev->change_mtu = niu_change_mtu;
7586 }
7587
7588 static void __devinit niu_device_announce(struct niu *np)
7589 {
7590 struct net_device *dev = np->dev;
7591 DECLARE_MAC_BUF(mac);
7592
7593 pr_info("%s: NIU Ethernet %s\n",
7594 dev->name, print_mac(mac, dev->dev_addr));
7595
7596 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
7597 dev->name,
7598 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"),
7599 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"),
7600 (np->flags & NIU_FLAGS_FIBER ? "FIBER" : "COPPER"),
7601 (np->mac_xcvr == MAC_XCVR_MII ? "MII" :
7602 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")),
7603 np->vpd.phy_type);
7604 }
7605
7606 static int __devinit niu_pci_init_one(struct pci_dev *pdev,
7607 const struct pci_device_id *ent)
7608 {
7609 unsigned long niureg_base, niureg_len;
7610 union niu_parent_id parent_id;
7611 struct net_device *dev;
7612 struct niu *np;
7613 int err, pos;
7614 u64 dma_mask;
7615 u16 val16;
7616
7617 niu_driver_version();
7618
7619 err = pci_enable_device(pdev);
7620 if (err) {
7621 dev_err(&pdev->dev, PFX "Cannot enable PCI device, "
7622 "aborting.\n");
7623 return err;
7624 }
7625
7626 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
7627 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
7628 dev_err(&pdev->dev, PFX "Cannot find proper PCI device "
7629 "base addresses, aborting.\n");
7630 err = -ENODEV;
7631 goto err_out_disable_pdev;
7632 }
7633
7634 err = pci_request_regions(pdev, DRV_MODULE_NAME);
7635 if (err) {
7636 dev_err(&pdev->dev, PFX "Cannot obtain PCI resources, "
7637 "aborting.\n");
7638 goto err_out_disable_pdev;
7639 }
7640
7641 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
7642 if (pos <= 0) {
7643 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
7644 "aborting.\n");
7645 goto err_out_free_res;
7646 }
7647
7648 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL,
7649 &niu_pci_ops, PCI_FUNC(pdev->devfn));
7650 if (!dev) {
7651 err = -ENOMEM;
7652 goto err_out_free_res;
7653 }
7654 np = netdev_priv(dev);
7655
7656 memset(&parent_id, 0, sizeof(parent_id));
7657 parent_id.pci.domain = pci_domain_nr(pdev->bus);
7658 parent_id.pci.bus = pdev->bus->number;
7659 parent_id.pci.device = PCI_SLOT(pdev->devfn);
7660
7661 np->parent = niu_get_parent(np, &parent_id,
7662 PLAT_TYPE_ATLAS);
7663 if (!np->parent) {
7664 err = -ENOMEM;
7665 goto err_out_free_dev;
7666 }
7667
7668 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
7669 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
7670 val16 |= (PCI_EXP_DEVCTL_CERE |
7671 PCI_EXP_DEVCTL_NFERE |
7672 PCI_EXP_DEVCTL_FERE |
7673 PCI_EXP_DEVCTL_URRE |
7674 PCI_EXP_DEVCTL_RELAX_EN);
7675 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
7676
7677 dma_mask = DMA_44BIT_MASK;
7678 err = pci_set_dma_mask(pdev, dma_mask);
7679 if (!err) {
7680 dev->features |= NETIF_F_HIGHDMA;
7681 err = pci_set_consistent_dma_mask(pdev, dma_mask);
7682 if (err) {
7683 dev_err(&pdev->dev, PFX "Unable to obtain 44 bit "
7684 "DMA for consistent allocations, "
7685 "aborting.\n");
7686 goto err_out_release_parent;
7687 }
7688 }
7689 if (err || dma_mask == DMA_32BIT_MASK) {
7690 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
7691 if (err) {
7692 dev_err(&pdev->dev, PFX "No usable DMA configuration, "
7693 "aborting.\n");
7694 goto err_out_release_parent;
7695 }
7696 }
7697
7698 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
7699
7700 niureg_base = pci_resource_start(pdev, 0);
7701 niureg_len = pci_resource_len(pdev, 0);
7702
7703 np->regs = ioremap_nocache(niureg_base, niureg_len);
7704 if (!np->regs) {
7705 dev_err(&pdev->dev, PFX "Cannot map device registers, "
7706 "aborting.\n");
7707 err = -ENOMEM;
7708 goto err_out_release_parent;
7709 }
7710
7711 pci_set_master(pdev);
7712 pci_save_state(pdev);
7713
7714 dev->irq = pdev->irq;
7715
7716 niu_assign_netdev_ops(dev);
7717
7718 err = niu_get_invariants(np);
7719 if (err) {
7720 if (err != -ENODEV)
7721 dev_err(&pdev->dev, PFX "Problem fetching invariants "
7722 "of chip, aborting.\n");
7723 goto err_out_iounmap;
7724 }
7725
7726 err = register_netdev(dev);
7727 if (err) {
7728 dev_err(&pdev->dev, PFX "Cannot register net device, "
7729 "aborting.\n");
7730 goto err_out_iounmap;
7731 }
7732
7733 pci_set_drvdata(pdev, dev);
7734
7735 niu_device_announce(np);
7736
7737 return 0;
7738
7739 err_out_iounmap:
7740 if (np->regs) {
7741 iounmap(np->regs);
7742 np->regs = NULL;
7743 }
7744
7745 err_out_release_parent:
7746 niu_put_parent(np);
7747
7748 err_out_free_dev:
7749 free_netdev(dev);
7750
7751 err_out_free_res:
7752 pci_release_regions(pdev);
7753
7754 err_out_disable_pdev:
7755 pci_disable_device(pdev);
7756 pci_set_drvdata(pdev, NULL);
7757
7758 return err;
7759 }
7760
7761 static void __devexit niu_pci_remove_one(struct pci_dev *pdev)
7762 {
7763 struct net_device *dev = pci_get_drvdata(pdev);
7764
7765 if (dev) {
7766 struct niu *np = netdev_priv(dev);
7767
7768 unregister_netdev(dev);
7769 if (np->regs) {
7770 iounmap(np->regs);
7771 np->regs = NULL;
7772 }
7773
7774 niu_ldg_free(np);
7775
7776 niu_put_parent(np);
7777
7778 free_netdev(dev);
7779 pci_release_regions(pdev);
7780 pci_disable_device(pdev);
7781 pci_set_drvdata(pdev, NULL);
7782 }
7783 }
7784
7785 static int niu_suspend(struct pci_dev *pdev, pm_message_t state)
7786 {
7787 struct net_device *dev = pci_get_drvdata(pdev);
7788 struct niu *np = netdev_priv(dev);
7789 unsigned long flags;
7790
7791 if (!netif_running(dev))
7792 return 0;
7793
7794 flush_scheduled_work();
7795 niu_netif_stop(np);
7796
7797 del_timer_sync(&np->timer);
7798
7799 spin_lock_irqsave(&np->lock, flags);
7800 niu_enable_interrupts(np, 0);
7801 spin_unlock_irqrestore(&np->lock, flags);
7802
7803 netif_device_detach(dev);
7804
7805 spin_lock_irqsave(&np->lock, flags);
7806 niu_stop_hw(np);
7807 spin_unlock_irqrestore(&np->lock, flags);
7808
7809 pci_save_state(pdev);
7810
7811 return 0;
7812 }
7813
7814 static int niu_resume(struct pci_dev *pdev)
7815 {
7816 struct net_device *dev = pci_get_drvdata(pdev);
7817 struct niu *np = netdev_priv(dev);
7818 unsigned long flags;
7819 int err;
7820
7821 if (!netif_running(dev))
7822 return 0;
7823
7824 pci_restore_state(pdev);
7825
7826 netif_device_attach(dev);
7827
7828 spin_lock_irqsave(&np->lock, flags);
7829
7830 err = niu_init_hw(np);
7831 if (!err) {
7832 np->timer.expires = jiffies + HZ;
7833 add_timer(&np->timer);
7834 niu_netif_start(np);
7835 }
7836
7837 spin_unlock_irqrestore(&np->lock, flags);
7838
7839 return err;
7840 }
7841
7842 static struct pci_driver niu_pci_driver = {
7843 .name = DRV_MODULE_NAME,
7844 .id_table = niu_pci_tbl,
7845 .probe = niu_pci_init_one,
7846 .remove = __devexit_p(niu_pci_remove_one),
7847 .suspend = niu_suspend,
7848 .resume = niu_resume,
7849 };
7850
7851 #ifdef CONFIG_SPARC64
7852 static void *niu_phys_alloc_coherent(struct device *dev, size_t size,
7853 u64 *dma_addr, gfp_t flag)
7854 {
7855 unsigned long order = get_order(size);
7856 unsigned long page = __get_free_pages(flag, order);
7857
7858 if (page == 0UL)
7859 return NULL;
7860 memset((char *)page, 0, PAGE_SIZE << order);
7861 *dma_addr = __pa(page);
7862
7863 return (void *) page;
7864 }
7865
7866 static void niu_phys_free_coherent(struct device *dev, size_t size,
7867 void *cpu_addr, u64 handle)
7868 {
7869 unsigned long order = get_order(size);
7870
7871 free_pages((unsigned long) cpu_addr, order);
7872 }
7873
7874 static u64 niu_phys_map_page(struct device *dev, struct page *page,
7875 unsigned long offset, size_t size,
7876 enum dma_data_direction direction)
7877 {
7878 return page_to_phys(page) + offset;
7879 }
7880
7881 static void niu_phys_unmap_page(struct device *dev, u64 dma_address,
7882 size_t size, enum dma_data_direction direction)
7883 {
7884 /* Nothing to do. */
7885 }
7886
7887 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr,
7888 size_t size,
7889 enum dma_data_direction direction)
7890 {
7891 return __pa(cpu_addr);
7892 }
7893
7894 static void niu_phys_unmap_single(struct device *dev, u64 dma_address,
7895 size_t size,
7896 enum dma_data_direction direction)
7897 {
7898 /* Nothing to do. */
7899 }
7900
7901 static const struct niu_ops niu_phys_ops = {
7902 .alloc_coherent = niu_phys_alloc_coherent,
7903 .free_coherent = niu_phys_free_coherent,
7904 .map_page = niu_phys_map_page,
7905 .unmap_page = niu_phys_unmap_page,
7906 .map_single = niu_phys_map_single,
7907 .unmap_single = niu_phys_unmap_single,
7908 };
7909
7910 static unsigned long res_size(struct resource *r)
7911 {
7912 return r->end - r->start + 1UL;
7913 }
7914
7915 static int __devinit niu_of_probe(struct of_device *op,
7916 const struct of_device_id *match)
7917 {
7918 union niu_parent_id parent_id;
7919 struct net_device *dev;
7920 struct niu *np;
7921 const u32 *reg;
7922 int err;
7923
7924 niu_driver_version();
7925
7926 reg = of_get_property(op->node, "reg", NULL);
7927 if (!reg) {
7928 dev_err(&op->dev, PFX "%s: No 'reg' property, aborting.\n",
7929 op->node->full_name);
7930 return -ENODEV;
7931 }
7932
7933 dev = niu_alloc_and_init(&op->dev, NULL, op,
7934 &niu_phys_ops, reg[0] & 0x1);
7935 if (!dev) {
7936 err = -ENOMEM;
7937 goto err_out;
7938 }
7939 np = netdev_priv(dev);
7940
7941 memset(&parent_id, 0, sizeof(parent_id));
7942 parent_id.of = of_get_parent(op->node);
7943
7944 np->parent = niu_get_parent(np, &parent_id,
7945 PLAT_TYPE_NIU);
7946 if (!np->parent) {
7947 err = -ENOMEM;
7948 goto err_out_free_dev;
7949 }
7950
7951 dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM);
7952
7953 np->regs = of_ioremap(&op->resource[1], 0,
7954 res_size(&op->resource[1]),
7955 "niu regs");
7956 if (!np->regs) {
7957 dev_err(&op->dev, PFX "Cannot map device registers, "
7958 "aborting.\n");
7959 err = -ENOMEM;
7960 goto err_out_release_parent;
7961 }
7962
7963 np->vir_regs_1 = of_ioremap(&op->resource[2], 0,
7964 res_size(&op->resource[2]),
7965 "niu vregs-1");
7966 if (!np->vir_regs_1) {
7967 dev_err(&op->dev, PFX "Cannot map device vir registers 1, "
7968 "aborting.\n");
7969 err = -ENOMEM;
7970 goto err_out_iounmap;
7971 }
7972
7973 np->vir_regs_2 = of_ioremap(&op->resource[3], 0,
7974 res_size(&op->resource[3]),
7975 "niu vregs-2");
7976 if (!np->vir_regs_2) {
7977 dev_err(&op->dev, PFX "Cannot map device vir registers 2, "
7978 "aborting.\n");
7979 err = -ENOMEM;
7980 goto err_out_iounmap;
7981 }
7982
7983 niu_assign_netdev_ops(dev);
7984
7985 err = niu_get_invariants(np);
7986 if (err) {
7987 if (err != -ENODEV)
7988 dev_err(&op->dev, PFX "Problem fetching invariants "
7989 "of chip, aborting.\n");
7990 goto err_out_iounmap;
7991 }
7992
7993 err = register_netdev(dev);
7994 if (err) {
7995 dev_err(&op->dev, PFX "Cannot register net device, "
7996 "aborting.\n");
7997 goto err_out_iounmap;
7998 }
7999
8000 dev_set_drvdata(&op->dev, dev);
8001
8002 niu_device_announce(np);
8003
8004 return 0;
8005
8006 err_out_iounmap:
8007 if (np->vir_regs_1) {
8008 of_iounmap(&op->resource[2], np->vir_regs_1,
8009 res_size(&op->resource[2]));
8010 np->vir_regs_1 = NULL;
8011 }
8012
8013 if (np->vir_regs_2) {
8014 of_iounmap(&op->resource[3], np->vir_regs_2,
8015 res_size(&op->resource[3]));
8016 np->vir_regs_2 = NULL;
8017 }
8018
8019 if (np->regs) {
8020 of_iounmap(&op->resource[1], np->regs,
8021 res_size(&op->resource[1]));
8022 np->regs = NULL;
8023 }
8024
8025 err_out_release_parent:
8026 niu_put_parent(np);
8027
8028 err_out_free_dev:
8029 free_netdev(dev);
8030
8031 err_out:
8032 return err;
8033 }
8034
8035 static int __devexit niu_of_remove(struct of_device *op)
8036 {
8037 struct net_device *dev = dev_get_drvdata(&op->dev);
8038
8039 if (dev) {
8040 struct niu *np = netdev_priv(dev);
8041
8042 unregister_netdev(dev);
8043
8044 if (np->vir_regs_1) {
8045 of_iounmap(&op->resource[2], np->vir_regs_1,
8046 res_size(&op->resource[2]));
8047 np->vir_regs_1 = NULL;
8048 }
8049
8050 if (np->vir_regs_2) {
8051 of_iounmap(&op->resource[3], np->vir_regs_2,
8052 res_size(&op->resource[3]));
8053 np->vir_regs_2 = NULL;
8054 }
8055
8056 if (np->regs) {
8057 of_iounmap(&op->resource[1], np->regs,
8058 res_size(&op->resource[1]));
8059 np->regs = NULL;
8060 }
8061
8062 niu_ldg_free(np);
8063
8064 niu_put_parent(np);
8065
8066 free_netdev(dev);
8067 dev_set_drvdata(&op->dev, NULL);
8068 }
8069 return 0;
8070 }
8071
8072 static struct of_device_id niu_match[] = {
8073 {
8074 .name = "network",
8075 .compatible = "SUNW,niusl",
8076 },
8077 {},
8078 };
8079 MODULE_DEVICE_TABLE(of, niu_match);
8080
8081 static struct of_platform_driver niu_of_driver = {
8082 .name = "niu",
8083 .match_table = niu_match,
8084 .probe = niu_of_probe,
8085 .remove = __devexit_p(niu_of_remove),
8086 };
8087
8088 #endif /* CONFIG_SPARC64 */
8089
8090 static int __init niu_init(void)
8091 {
8092 int err = 0;
8093
8094 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024);
8095
8096 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT);
8097
8098 #ifdef CONFIG_SPARC64
8099 err = of_register_driver(&niu_of_driver, &of_bus_type);
8100 #endif
8101
8102 if (!err) {
8103 err = pci_register_driver(&niu_pci_driver);
8104 #ifdef CONFIG_SPARC64
8105 if (err)
8106 of_unregister_driver(&niu_of_driver);
8107 #endif
8108 }
8109
8110 return err;
8111 }
8112
8113 static void __exit niu_exit(void)
8114 {
8115 pci_unregister_driver(&niu_pci_driver);
8116 #ifdef CONFIG_SPARC64
8117 of_unregister_driver(&niu_of_driver);
8118 #endif
8119 }
8120
8121 module_init(niu_init);
8122 module_exit(niu_exit);
WRT350N Kernel Patches