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x86: cpa: move clflush_cache_range()
[wrt350n-kernel.git] / drivers / net / r6040.c
blob2334f4ebf907cc076c49db4a1eccda205c94a63c
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/version.h>
28 #include <linux/moduleparam.h>
29 #include <linux/string.h>
30 #include <linux/timer.h>
31 #include <linux/errno.h>
32 #include <linux/ioport.h>
33 #include <linux/slab.h>
34 #include <linux/interrupt.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/init.h>
40 #include <linux/delay.h>
41 #include <linux/mii.h>
42 #include <linux/ethtool.h>
43 #include <linux/crc32.h>
44 #include <linux/spinlock.h>
45 #include <linux/bitops.h>
46 #include <linux/io.h>
47 #include <linux/irq.h>
48 #include <linux/uaccess.h>
49
50 #include <asm/processor.h>
51
52 #define DRV_NAME "r6040"
53 #define DRV_VERSION "0.16"
54 #define DRV_RELDATE "10Nov2007"
55
56 /* PHY CHIP Address */
57 #define PHY1_ADDR 1 /* For MAC1 */
58 #define PHY2_ADDR 2 /* For MAC2 */
59 #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */
60 #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */
61
62 /* Time in jiffies before concluding the transmitter is hung. */
63 #define TX_TIMEOUT (6000 * HZ / 1000)
64 #define TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
65
66 /* RDC MAC I/O Size */
67 #define R6040_IO_SIZE 256
68
69 /* MAX RDC MAC */
70 #define MAX_MAC 2
71
72 /* MAC registers */
73 #define MCR0 0x00 /* Control register 0 */
74 #define MCR1 0x04 /* Control register 1 */
75 #define MAC_RST 0x0001 /* Reset the MAC */
76 #define MBCR 0x08 /* Bus control */
77 #define MT_ICR 0x0C /* TX interrupt control */
78 #define MR_ICR 0x10 /* RX interrupt control */
79 #define MTPR 0x14 /* TX poll command register */
80 #define MR_BSR 0x18 /* RX buffer size */
81 #define MR_DCR 0x1A /* RX descriptor control */
82 #define MLSR 0x1C /* Last status */
83 #define MMDIO 0x20 /* MDIO control register */
84 #define MDIO_WRITE 0x4000 /* MDIO write */
85 #define MDIO_READ 0x2000 /* MDIO read */
86 #define MMRD 0x24 /* MDIO read data register */
87 #define MMWD 0x28 /* MDIO write data register */
88 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
89 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
90 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
91 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
92 #define MISR 0x3C /* Status register */
93 #define MIER 0x40 /* INT enable register */
94 #define MSK_INT 0x0000 /* Mask off interrupts */
95 #define ME_CISR 0x44 /* Event counter INT status */
96 #define ME_CIER 0x48 /* Event counter INT enable */
97 #define MR_CNT 0x50 /* Successfully received packet counter */
98 #define ME_CNT0 0x52 /* Event counter 0 */
99 #define ME_CNT1 0x54 /* Event counter 1 */
100 #define ME_CNT2 0x56 /* Event counter 2 */
101 #define ME_CNT3 0x58 /* Event counter 3 */
102 #define MT_CNT 0x5A /* Successfully transmit packet counter */
103 #define ME_CNT4 0x5C /* Event counter 4 */
104 #define MP_CNT 0x5E /* Pause frame counter register */
105 #define MAR0 0x60 /* Hash table 0 */
106 #define MAR1 0x62 /* Hash table 1 */
107 #define MAR2 0x64 /* Hash table 2 */
108 #define MAR3 0x66 /* Hash table 3 */
109 #define MID_0L 0x68 /* Multicast address MID0 Low */
110 #define MID_0M 0x6A /* Multicast address MID0 Medium */
111 #define MID_0H 0x6C /* Multicast address MID0 High */
112 #define MID_1L 0x70 /* MID1 Low */
113 #define MID_1M 0x72 /* MID1 Medium */
114 #define MID_1H 0x74 /* MID1 High */
115 #define MID_2L 0x78 /* MID2 Low */
116 #define MID_2M 0x7A /* MID2 Medium */
117 #define MID_2H 0x7C /* MID2 High */
118 #define MID_3L 0x80 /* MID3 Low */
119 #define MID_3M 0x82 /* MID3 Medium */
120 #define MID_3H 0x84 /* MID3 High */
121 #define PHY_CC 0x88 /* PHY status change configuration register */
122 #define PHY_ST 0x8A /* PHY status register */
123 #define MAC_SM 0xAC /* MAC status machine */
124 #define MAC_ID 0xBE /* Identifier register */
125
126 #define TX_DCNT 0x80 /* TX descriptor count */
127 #define RX_DCNT 0x80 /* RX descriptor count */
128 #define MAX_BUF_SIZE 0x600
129 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
130 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
131 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
132 #define MCAST_MAX 4 /* Max number multicast addresses to filter */
133
134 /* PHY settings */
135 #define ICPLUS_PHY_ID 0x0243
136
137 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
138 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
139 "Florian Fainelli <florian@openwrt.org>");
140 MODULE_LICENSE("GPL");
141 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
142
143 #define RX_INT 0x0001
144 #define TX_INT 0x0010
145 #define RX_NO_DESC_INT 0x0002
146 #define INT_MASK (RX_INT | TX_INT)
147
148 struct r6040_descriptor {
149 u16 status, len; /* 0-3 */
150 __le32 buf; /* 4-7 */
151 __le32 ndesc; /* 8-B */
152 u32 rev1; /* C-F */
153 char *vbufp; /* 10-13 */
154 struct r6040_descriptor *vndescp; /* 14-17 */
155 struct sk_buff *skb_ptr; /* 18-1B */
156 u32 rev2; /* 1C-1F */
157 } __attribute__((aligned(32)));
158
159 struct r6040_private {
160 spinlock_t lock; /* driver lock */
161 struct timer_list timer;
162 struct pci_dev *pdev;
163 struct r6040_descriptor *rx_insert_ptr;
164 struct r6040_descriptor *rx_remove_ptr;
165 struct r6040_descriptor *tx_insert_ptr;
166 struct r6040_descriptor *tx_remove_ptr;
167 struct r6040_descriptor *rx_ring;
168 struct r6040_descriptor *tx_ring;
169 dma_addr_t rx_ring_dma;
170 dma_addr_t tx_ring_dma;
171 u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode;
172 u16 mcr0, mcr1;
173 u16 switch_sig;
174 struct net_device *dev;
175 struct mii_if_info mii_if;
176 struct napi_struct napi;
177 struct net_device_stats stats;
178 u16 napi_rx_running;
179 void __iomem *base;
180 };
181
182 static char version[] __devinitdata = KERN_INFO DRV_NAME
183 ": RDC R6040 NAPI net driver,"
184 "version "DRV_VERSION " (" DRV_RELDATE ")\n";
185
186 static int phy_table[] = { PHY1_ADDR, PHY2_ADDR };
187
188 /* Read a word data from PHY Chip */
189 static int phy_read(void __iomem *ioaddr, int phy_addr, int reg)
190 {
191 int limit = 2048;
192 u16 cmd;
193
194 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
195 /* Wait for the read bit to be cleared */
196 while (limit--) {
197 cmd = ioread16(ioaddr + MMDIO);
198 if (cmd & MDIO_READ)
199 break;
200 }
201
202 return ioread16(ioaddr + MMRD);
203 }
204
205 /* Write a word data from PHY Chip */
206 static void phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val)
207 {
208 int limit = 2048;
209 u16 cmd;
210
211 iowrite16(val, ioaddr + MMWD);
212 /* Write the command to the MDIO bus */
213 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
214 /* Wait for the write bit to be cleared */
215 while (limit--) {
216 cmd = ioread16(ioaddr + MMDIO);
217 if (cmd & MDIO_WRITE)
218 break;
219 }
220 }
221
222 static int mdio_read(struct net_device *dev, int mii_id, int reg)
223 {
224 struct r6040_private *lp = netdev_priv(dev);
225 void __iomem *ioaddr = lp->base;
226
227 return (phy_read(ioaddr, lp->phy_addr, reg));
228 }
229
230 static void mdio_write(struct net_device *dev, int mii_id, int reg, int val)
231 {
232 struct r6040_private *lp = netdev_priv(dev);
233 void __iomem *ioaddr = lp->base;
234
235 phy_write(ioaddr, lp->phy_addr, reg, val);
236 }
237
238 static void r6040_tx_timeout(struct net_device *dev)
239 {
240 struct r6040_private *priv = netdev_priv(dev);
241
242 disable_irq(dev->irq);
243 napi_disable(&priv->napi);
244 spin_lock(&priv->lock);
245 dev->stats.tx_errors++;
246 spin_unlock(&priv->lock);
247
248 netif_stop_queue(dev);
249 }
250
251 /* Allocate skb buffer for rx descriptor */
252 static void rx_buf_alloc(struct r6040_private *lp, struct net_device *dev)
253 {
254 struct r6040_descriptor *descptr;
255 void __iomem *ioaddr = lp->base;
256
257 descptr = lp->rx_insert_ptr;
258 while (lp->rx_free_desc < RX_DCNT) {
259 descptr->skb_ptr = dev_alloc_skb(MAX_BUF_SIZE);
260
261 if (!descptr->skb_ptr)
262 break;
263 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
264 descptr->skb_ptr->data,
265 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
266 descptr->status = 0x8000;
267 descptr = descptr->vndescp;
268 lp->rx_free_desc++;
269 /* Trigger RX DMA */
270 iowrite16(lp->mcr0 | 0x0002, ioaddr);
271 }
272 lp->rx_insert_ptr = descptr;
273 }
274
275
276 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
277 {
278 struct r6040_private *priv = netdev_priv(dev);
279 void __iomem *ioaddr = priv->base;
280 unsigned long flags;
281
282 spin_lock_irqsave(&priv->lock, flags);
283 priv->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
284 priv->stats.multicast += ioread8(ioaddr + ME_CNT0);
285 spin_unlock_irqrestore(&priv->lock, flags);
286
287 return &priv->stats;
288 }
289
290 /* Stop RDC MAC and Free the allocated resource */
291 static void r6040_down(struct net_device *dev)
292 {
293 struct r6040_private *lp = netdev_priv(dev);
294 void __iomem *ioaddr = lp->base;
295 struct pci_dev *pdev = lp->pdev;
296 int i;
297 int limit = 2048;
298 u16 *adrp;
299 u16 cmd;
300
301 /* Stop MAC */
302 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
303 iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */
304 while (limit--) {
305 cmd = ioread16(ioaddr + MCR1);
306 if (cmd & 0x1)
307 break;
308 }
309
310 /* Restore MAC Address to MIDx */
311 adrp = (u16 *) dev->dev_addr;
312 iowrite16(adrp[0], ioaddr + MID_0L);
313 iowrite16(adrp[1], ioaddr + MID_0M);
314 iowrite16(adrp[2], ioaddr + MID_0H);
315 free_irq(dev->irq, dev);
316 /* Free RX buffer */
317 for (i = 0; i < RX_DCNT; i++) {
318 if (lp->rx_insert_ptr->skb_ptr) {
319 pci_unmap_single(lp->pdev, lp->rx_insert_ptr->buf,
320 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
321 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
322 lp->rx_insert_ptr->skb_ptr = NULL;
323 }
324 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
325 }
326
327 /* Free TX buffer */
328 for (i = 0; i < TX_DCNT; i++) {
329 if (lp->tx_insert_ptr->skb_ptr) {
330 pci_unmap_single(lp->pdev, lp->tx_insert_ptr->buf,
331 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
332 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
333 lp->rx_insert_ptr->skb_ptr = NULL;
334 }
335 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
336 }
337
338 /* Free Descriptor memory */
339 pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
340 pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
341 }
342
343 static int r6040_close(struct net_device *dev)
344 {
345 struct r6040_private *lp = netdev_priv(dev);
346
347 /* deleted timer */
348 del_timer_sync(&lp->timer);
349
350 spin_lock_irq(&lp->lock);
351 netif_stop_queue(dev);
352 r6040_down(dev);
353 spin_unlock_irq(&lp->lock);
354
355 return 0;
356 }
357
358 /* Status of PHY CHIP */
359 static int phy_mode_chk(struct net_device *dev)
360 {
361 struct r6040_private *lp = netdev_priv(dev);
362 void __iomem *ioaddr = lp->base;
363 int phy_dat;
364
365 /* PHY Link Status Check */
366 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
367 if (!(phy_dat & 0x4))
368 phy_dat = 0x8000; /* Link Failed, full duplex */
369
370 /* PHY Chip Auto-Negotiation Status */
371 phy_dat = phy_read(ioaddr, lp->phy_addr, 1);
372 if (phy_dat & 0x0020) {
373 /* Auto Negotiation Mode */
374 phy_dat = phy_read(ioaddr, lp->phy_addr, 5);
375 phy_dat &= phy_read(ioaddr, lp->phy_addr, 4);
376 if (phy_dat & 0x140)
377 /* Force full duplex */
378 phy_dat = 0x8000;
379 else
380 phy_dat = 0;
381 } else {
382 /* Force Mode */
383 phy_dat = phy_read(ioaddr, lp->phy_addr, 0);
384 if (phy_dat & 0x100)
385 phy_dat = 0x8000;
386 else
387 phy_dat = 0x0000;
388 }
389
390 return phy_dat;
391 };
392
393 static void r6040_set_carrier(struct mii_if_info *mii)
394 {
395 if (phy_mode_chk(mii->dev)) {
396 /* autoneg is off: Link is always assumed to be up */
397 if (!netif_carrier_ok(mii->dev))
398 netif_carrier_on(mii->dev);
399 } else
400 phy_mode_chk(mii->dev);
401 }
402
403 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
404 {
405 struct r6040_private *lp = netdev_priv(dev);
406 struct mii_ioctl_data *data = if_mii(rq);
407 int rc;
408
409 if (!netif_running(dev))
410 return -EINVAL;
411 spin_lock_irq(&lp->lock);
412 rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
413 spin_unlock_irq(&lp->lock);
414 r6040_set_carrier(&lp->mii_if);
415 return rc;
416 }
417
418 static int r6040_rx(struct net_device *dev, int limit)
419 {
420 struct r6040_private *priv = netdev_priv(dev);
421 int count;
422 void __iomem *ioaddr = priv->base;
423 u16 err;
424
425 for (count = 0; count < limit; ++count) {
426 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
427 struct sk_buff *skb_ptr;
428
429 /* Disable RX interrupt */
430 iowrite16(ioread16(ioaddr + MIER) & (~RX_INT), ioaddr + MIER);
431 descptr = priv->rx_remove_ptr;
432
433 /* Check for errors */
434 err = ioread16(ioaddr + MLSR);
435 if (err & 0x0400) priv->stats.rx_errors++;
436 /* RX FIFO over-run */
437 if (err & 0x8000) priv->stats.rx_fifo_errors++;
438 /* RX descriptor unavailable */
439 if (err & 0x0080) priv->stats.rx_frame_errors++;
440 /* Received packet with length over buffer lenght */
441 if (err & 0x0020) priv->stats.rx_over_errors++;
442 /* Received packet with too long or short */
443 if (err & (0x0010|0x0008)) priv->stats.rx_length_errors++;
444 /* Received packet with CRC errors */
445 if (err & 0x0004) {
446 spin_lock(&priv->lock);
447 priv->stats.rx_crc_errors++;
448 spin_unlock(&priv->lock);
449 }
450
451 while (priv->rx_free_desc) {
452 /* No RX packet */
453 if (descptr->status & 0x8000)
454 break;
455 skb_ptr = descptr->skb_ptr;
456 if (!skb_ptr) {
457 printk(KERN_ERR "%s: Inconsistent RX"
458 "descriptor chain\n",
459 dev->name);
460 break;
461 }
462 descptr->skb_ptr = NULL;
463 skb_ptr->dev = priv->dev;
464 /* Do not count the CRC */
465 skb_put(skb_ptr, descptr->len - 4);
466 pci_unmap_single(priv->pdev, descptr->buf,
467 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
468 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
469 /* Send to upper layer */
470 netif_receive_skb(skb_ptr);
471 dev->last_rx = jiffies;
472 priv->dev->stats.rx_packets++;
473 priv->dev->stats.rx_bytes += descptr->len;
474 /* To next descriptor */
475 descptr = descptr->vndescp;
476 priv->rx_free_desc--;
477 }
478 priv->rx_remove_ptr = descptr;
479 }
480 /* Allocate new RX buffer */
481 if (priv->rx_free_desc < RX_DCNT)
482 rx_buf_alloc(priv, priv->dev);
483
484 return count;
485 }
486
487 static void r6040_tx(struct net_device *dev)
488 {
489 struct r6040_private *priv = netdev_priv(dev);
490 struct r6040_descriptor *descptr;
491 void __iomem *ioaddr = priv->base;
492 struct sk_buff *skb_ptr;
493 u16 err;
494
495 spin_lock(&priv->lock);
496 descptr = priv->tx_remove_ptr;
497 while (priv->tx_free_desc < TX_DCNT) {
498 /* Check for errors */
499 err = ioread16(ioaddr + MLSR);
500
501 if (err & 0x0200) priv->stats.rx_fifo_errors++;
502 if (err & (0x2000 | 0x4000)) priv->stats.tx_carrier_errors++;
503
504 if (descptr->status & 0x8000)
505 break; /* Not complte */
506 skb_ptr = descptr->skb_ptr;
507 pci_unmap_single(priv->pdev, descptr->buf,
508 skb_ptr->len, PCI_DMA_TODEVICE);
509 /* Free buffer */
510 dev_kfree_skb_irq(skb_ptr);
511 descptr->skb_ptr = NULL;
512 /* To next descriptor */
513 descptr = descptr->vndescp;
514 priv->tx_free_desc++;
515 }
516 priv->tx_remove_ptr = descptr;
517
518 if (priv->tx_free_desc)
519 netif_wake_queue(dev);
520 spin_unlock(&priv->lock);
521 }
522
523 static int r6040_poll(struct napi_struct *napi, int budget)
524 {
525 struct r6040_private *priv =
526 container_of(napi, struct r6040_private, napi);
527 struct net_device *dev = priv->dev;
528 void __iomem *ioaddr = priv->base;
529 int work_done;
530
531 work_done = r6040_rx(dev, budget);
532
533 if (work_done < budget) {
534 netif_rx_complete(dev, napi);
535 /* Enable RX interrupt */
536 iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER);
537 }
538 return work_done;
539 }
540
541 /* The RDC interrupt handler. */
542 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
543 {
544 struct net_device *dev = dev_id;
545 struct r6040_private *lp = netdev_priv(dev);
546 void __iomem *ioaddr = lp->base;
547 u16 status;
548 int handled = 1;
549
550 /* Mask off RDC MAC interrupt */
551 iowrite16(MSK_INT, ioaddr + MIER);
552 /* Read MISR status and clear */
553 status = ioread16(ioaddr + MISR);
554
555 if (status == 0x0000 || status == 0xffff)
556 return IRQ_NONE;
557
558 /* RX interrupt request */
559 if (status & 0x01) {
560 netif_rx_schedule(dev, &lp->napi);
561 iowrite16(TX_INT, ioaddr + MIER);
562 }
563
564 /* TX interrupt request */
565 if (status & 0x10)
566 r6040_tx(dev);
567
568 return IRQ_RETVAL(handled);
569 }
570
571 #ifdef CONFIG_NET_POLL_CONTROLLER
572 static void r6040_poll_controller(struct net_device *dev)
573 {
574 disable_irq(dev->irq);
575 r6040_interrupt(dev->irq, dev);
576 enable_irq(dev->irq);
577 }
578 #endif
579
580 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
581 dma_addr_t desc_dma, int size)
582 {
583 struct r6040_descriptor *desc = desc_ring;
584 dma_addr_t mapping = desc_dma;
585
586 while (size-- > 0) {
587 mapping += sizeof(sizeof(*desc));
588 desc->ndesc = cpu_to_le32(mapping);
589 desc->vndescp = desc + 1;
590 desc++;
591 }
592 desc--;
593 desc->ndesc = cpu_to_le32(desc_dma);
594 desc->vndescp = desc_ring;
595 }
596
597 /* Init RDC MAC */
598 static void r6040_up(struct net_device *dev)
599 {
600 struct r6040_private *lp = netdev_priv(dev);
601 void __iomem *ioaddr = lp->base;
602
603 /* Initialize */
604 lp->tx_free_desc = TX_DCNT;
605 lp->rx_free_desc = 0;
606 /* Init descriptor */
607 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
608 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
609 /* Init TX descriptor */
610 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
611
612 /* Init RX descriptor */
613 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
614
615 /* Allocate buffer for RX descriptor */
616 rx_buf_alloc(lp, dev);
617
618 /*
619 * TX and RX descriptor start registers.
620 * Lower 16-bits to MxD_SA0. Higher 16-bits to MxD_SA1.
621 */
622 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
623 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
624
625 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
626 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
627
628 /* Buffer Size Register */
629 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
630 /* Read the PHY ID */
631 lp->switch_sig = phy_read(ioaddr, 0, 2);
632
633 if (lp->switch_sig == ICPLUS_PHY_ID) {
634 phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */
635 lp->phy_mode = 0x8000;
636 } else {
637 /* PHY Mode Check */
638 phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP);
639 phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE);
640
641 if (PHY_MODE == 0x3100)
642 lp->phy_mode = phy_mode_chk(dev);
643 else
644 lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
645 }
646 /* MAC Bus Control Register */
647 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
648
649 /* MAC TX/RX Enable */
650 lp->mcr0 |= lp->phy_mode;
651 iowrite16(lp->mcr0, ioaddr);
652
653 /* set interrupt waiting time and packet numbers */
654 iowrite16(0x0F06, ioaddr + MT_ICR);
655 iowrite16(0x0F06, ioaddr + MR_ICR);
656
657 /* improve performance (by RDC guys) */
658 phy_write(ioaddr, 30, 17, (phy_read(ioaddr, 30, 17) | 0x4000));
659 phy_write(ioaddr, 30, 17, ~((~phy_read(ioaddr, 30, 17)) | 0x2000));
660 phy_write(ioaddr, 0, 19, 0x0000);
661 phy_write(ioaddr, 0, 30, 0x01F0);
662
663 /* Interrupt Mask Register */
664 iowrite16(INT_MASK, ioaddr + MIER);
665 }
666
667 /*
668 A periodic timer routine
669 Polling PHY Chip Link Status
670 */
671 static void r6040_timer(unsigned long data)
672 {
673 struct net_device *dev = (struct net_device *)data;
674 struct r6040_private *lp = netdev_priv(dev);
675 void __iomem *ioaddr = lp->base;
676 u16 phy_mode;
677
678 /* Polling PHY Chip Status */
679 if (PHY_MODE == 0x3100)
680 phy_mode = phy_mode_chk(dev);
681 else
682 phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0;
683
684 if (phy_mode != lp->phy_mode) {
685 lp->phy_mode = phy_mode;
686 lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode;
687 iowrite16(lp->mcr0, ioaddr);
688 printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr));
689 }
690
691 /* Timer active again */
692 lp->timer.expires = TIMER_WUT;
693 add_timer(&lp->timer);
694 }
695
696 /* Read/set MAC address routines */
697 static void r6040_mac_address(struct net_device *dev)
698 {
699 struct r6040_private *lp = netdev_priv(dev);
700 void __iomem *ioaddr = lp->base;
701 u16 *adrp;
702
703 /* MAC operation register */
704 iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */
705 iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */
706 iowrite16(0, ioaddr + MAC_SM);
707 udelay(5000);
708
709 /* Restore MAC Address */
710 adrp = (u16 *) dev->dev_addr;
711 iowrite16(adrp[0], ioaddr + MID_0L);
712 iowrite16(adrp[1], ioaddr + MID_0M);
713 iowrite16(adrp[2], ioaddr + MID_0H);
714 }
715
716 static int r6040_open(struct net_device *dev)
717 {
718 struct r6040_private *lp = netdev_priv(dev);
719 int ret;
720
721 /* Request IRQ and Register interrupt handler */
722 ret = request_irq(dev->irq, &r6040_interrupt,
723 IRQF_SHARED, dev->name, dev);
724 if (ret)
725 return ret;
726
727 /* Set MAC address */
728 r6040_mac_address(dev);
729
730 /* Allocate Descriptor memory */
731 lp->rx_ring =
732 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
733 if (!lp->rx_ring)
734 return -ENOMEM;
735
736 lp->tx_ring =
737 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
738 if (!lp->tx_ring) {
739 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
740 lp->rx_ring_dma);
741 return -ENOMEM;
742 }
743
744 r6040_up(dev);
745
746 napi_enable(&lp->napi);
747 netif_start_queue(dev);
748
749 if (lp->switch_sig != ICPLUS_PHY_ID) {
750 /* set and active a timer process */
751 init_timer(&lp->timer);
752 lp->timer.expires = TIMER_WUT;
753 lp->timer.data = (unsigned long)dev;
754 lp->timer.function = &r6040_timer;
755 add_timer(&lp->timer);
756 }
757 return 0;
758 }
759
760 static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev)
761 {
762 struct r6040_private *lp = netdev_priv(dev);
763 struct r6040_descriptor *descptr;
764 void __iomem *ioaddr = lp->base;
765 unsigned long flags;
766 int ret = NETDEV_TX_OK;
767
768 /* Critical Section */
769 spin_lock_irqsave(&lp->lock, flags);
770
771 /* TX resource check */
772 if (!lp->tx_free_desc) {
773 spin_unlock_irqrestore(&lp->lock, flags);
774 netif_stop_queue(dev);
775 printk(KERN_ERR DRV_NAME ": no tx descriptor\n");
776 ret = NETDEV_TX_BUSY;
777 return ret;
778 }
779
780 /* Statistic Counter */
781 dev->stats.tx_packets++;
782 dev->stats.tx_bytes += skb->len;
783 /* Set TX descriptor & Transmit it */
784 lp->tx_free_desc--;
785 descptr = lp->tx_insert_ptr;
786 if (skb->len < MISR)
787 descptr->len = MISR;
788 else
789 descptr->len = skb->len;
790
791 descptr->skb_ptr = skb;
792 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
793 skb->data, skb->len, PCI_DMA_TODEVICE));
794 descptr->status = 0x8000;
795 /* Trigger the MAC to check the TX descriptor */
796 iowrite16(0x01, ioaddr + MTPR);
797 lp->tx_insert_ptr = descptr->vndescp;
798
799 /* If no tx resource, stop */
800 if (!lp->tx_free_desc)
801 netif_stop_queue(dev);
802
803 dev->trans_start = jiffies;
804 spin_unlock_irqrestore(&lp->lock, flags);
805 return ret;
806 }
807
808 static void r6040_multicast_list(struct net_device *dev)
809 {
810 struct r6040_private *lp = netdev_priv(dev);
811 void __iomem *ioaddr = lp->base;
812 u16 *adrp;
813 u16 reg;
814 unsigned long flags;
815 struct dev_mc_list *dmi = dev->mc_list;
816 int i;
817
818 /* MAC Address */
819 adrp = (u16 *)dev->dev_addr;
820 iowrite16(adrp[0], ioaddr + MID_0L);
821 iowrite16(adrp[1], ioaddr + MID_0M);
822 iowrite16(adrp[2], ioaddr + MID_0H);
823
824 /* Promiscous Mode */
825 spin_lock_irqsave(&lp->lock, flags);
826
827 /* Clear AMCP & PROM bits */
828 reg = ioread16(ioaddr) & ~0x0120;
829 if (dev->flags & IFF_PROMISC) {
830 reg |= 0x0020;
831 lp->mcr0 |= 0x0020;
832 }
833 /* Too many multicast addresses
834 * accept all traffic */
835 else if ((dev->mc_count > MCAST_MAX)
836 || (dev->flags & IFF_ALLMULTI))
837 reg |= 0x0020;
838
839 iowrite16(reg, ioaddr);
840 spin_unlock_irqrestore(&lp->lock, flags);
841
842 /* Build the hash table */
843 if (dev->mc_count > MCAST_MAX) {
844 u16 hash_table[4];
845 u32 crc;
846
847 for (i = 0; i < 4; i++)
848 hash_table[i] = 0;
849
850 for (i = 0; i < dev->mc_count; i++) {
851 char *addrs = dmi->dmi_addr;
852
853 dmi = dmi->next;
854
855 if (!(*addrs & 1))
856 continue;
857
858 crc = ether_crc_le(6, addrs);
859 crc >>= 26;
860 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
861 }
862 /* Write the index of the hash table */
863 for (i = 0; i < 4; i++)
864 iowrite16(hash_table[i] << 14, ioaddr + MCR1);
865 /* Fill the MAC hash tables with their values */
866 iowrite16(hash_table[0], ioaddr + MAR0);
867 iowrite16(hash_table[1], ioaddr + MAR1);
868 iowrite16(hash_table[2], ioaddr + MAR2);
869 iowrite16(hash_table[3], ioaddr + MAR3);
870 }
871 /* Multicast Address 1~4 case */
872 for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) {
873 adrp = (u16 *)dmi->dmi_addr;
874 iowrite16(adrp[0], ioaddr + MID_1L + 8*i);
875 iowrite16(adrp[1], ioaddr + MID_1M + 8*i);
876 iowrite16(adrp[2], ioaddr + MID_1H + 8*i);
877 dmi = dmi->next;
878 }
879 for (i = dev->mc_count; i < MCAST_MAX; i++) {
880 iowrite16(0xffff, ioaddr + MID_0L + 8*i);
881 iowrite16(0xffff, ioaddr + MID_0M + 8*i);
882 iowrite16(0xffff, ioaddr + MID_0H + 8*i);
883 }
884 }
885
886 static void netdev_get_drvinfo(struct net_device *dev,
887 struct ethtool_drvinfo *info)
888 {
889 struct r6040_private *rp = netdev_priv(dev);
890
891 strcpy(info->driver, DRV_NAME);
892 strcpy(info->version, DRV_VERSION);
893 strcpy(info->bus_info, pci_name(rp->pdev));
894 }
895
896 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
897 {
898 struct r6040_private *rp = netdev_priv(dev);
899 int rc;
900
901 spin_lock_irq(&rp->lock);
902 rc = mii_ethtool_gset(&rp->mii_if, cmd);
903 spin_unlock_irq(&rp->lock);
904
905 return rc;
906 }
907
908 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
909 {
910 struct r6040_private *rp = netdev_priv(dev);
911 int rc;
912
913 spin_lock_irq(&rp->lock);
914 rc = mii_ethtool_sset(&rp->mii_if, cmd);
915 spin_unlock_irq(&rp->lock);
916 r6040_set_carrier(&rp->mii_if);
917
918 return rc;
919 }
920
921 static u32 netdev_get_link(struct net_device *dev)
922 {
923 struct r6040_private *rp = netdev_priv(dev);
924
925 return mii_link_ok(&rp->mii_if);
926 }
927
928 static struct ethtool_ops netdev_ethtool_ops = {
929 .get_drvinfo = netdev_get_drvinfo,
930 .get_settings = netdev_get_settings,
931 .set_settings = netdev_set_settings,
932 .get_link = netdev_get_link,
933 };
934
935 static int __devinit r6040_init_one(struct pci_dev *pdev,
936 const struct pci_device_id *ent)
937 {
938 struct net_device *dev;
939 struct r6040_private *lp;
940 void __iomem *ioaddr;
941 int err, io_size = R6040_IO_SIZE;
942 static int card_idx = -1;
943 int bar = 0;
944 long pioaddr;
945 u16 *adrp;
946
947 printk(KERN_INFO "%s\n", version);
948
949 err = pci_enable_device(pdev);
950 if (err)
951 return err;
952
953 /* this should always be supported */
954 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
955 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
956 "not supported by the card\n");
957 return -ENODEV;
958 }
959 if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
960 printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses"
961 "not supported by the card\n");
962 return -ENODEV;
963 }
964
965 /* IO Size check */
966 if (pci_resource_len(pdev, 0) < io_size) {
967 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
968 return -EIO;
969 }
970
971 pioaddr = pci_resource_start(pdev, 0); /* IO map base address */
972 pci_set_master(pdev);
973
974 dev = alloc_etherdev(sizeof(struct r6040_private));
975 if (!dev) {
976 printk(KERN_ERR "Failed to allocate etherdev\n");
977 return -ENOMEM;
978 }
979 SET_NETDEV_DEV(dev, &pdev->dev);
980 lp = netdev_priv(dev);
981 lp->pdev = pdev;
982
983 if (pci_request_regions(pdev, DRV_NAME)) {
984 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
985 err = -ENODEV;
986 goto err_out_disable;
987 }
988
989 ioaddr = pci_iomap(pdev, bar, io_size);
990 if (!ioaddr) {
991 printk(KERN_ERR "ioremap failed for device %s\n",
992 pci_name(pdev));
993 return -EIO;
994 }
995
996 /* Init system & device */
997 lp->base = ioaddr;
998 dev->irq = pdev->irq;
999
1000 spin_lock_init(&lp->lock);
1001 pci_set_drvdata(pdev, dev);
1002
1003 /* Set MAC address */
1004 card_idx++;
1005
1006 adrp = (u16 *)dev->dev_addr;
1007 adrp[0] = ioread16(ioaddr + MID_0L);
1008 adrp[1] = ioread16(ioaddr + MID_0M);
1009 adrp[2] = ioread16(ioaddr + MID_0H);
1010
1011 /* Link new device into r6040_root_dev */
1012 lp->pdev = pdev;
1013
1014 /* Init RDC private data */
1015 lp->mcr0 = 0x1002;
1016 lp->phy_addr = phy_table[card_idx];
1017 lp->switch_sig = 0;
1018
1019 /* The RDC-specific entries in the device structure. */
1020 dev->open = &r6040_open;
1021 dev->hard_start_xmit = &r6040_start_xmit;
1022 dev->stop = &r6040_close;
1023 dev->get_stats = r6040_get_stats;
1024 dev->set_multicast_list = &r6040_multicast_list;
1025 dev->do_ioctl = &r6040_ioctl;
1026 dev->ethtool_ops = &netdev_ethtool_ops;
1027 dev->tx_timeout = &r6040_tx_timeout;
1028 dev->watchdog_timeo = TX_TIMEOUT;
1029 #ifdef CONFIG_NET_POLL_CONTROLLER
1030 dev->poll_controller = r6040_poll_controller;
1031 #endif
1032 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1033 lp->mii_if.dev = dev;
1034 lp->mii_if.mdio_read = mdio_read;
1035 lp->mii_if.mdio_write = mdio_write;
1036 lp->mii_if.phy_id = lp->phy_addr;
1037 lp->mii_if.phy_id_mask = 0x1f;
1038 lp->mii_if.reg_num_mask = 0x1f;
1039
1040 /* Register net device. After this dev->name assign */
1041 err = register_netdev(dev);
1042 if (err) {
1043 printk(KERN_ERR DRV_NAME ": Failed to register net device\n");
1044 goto err_out_res;
1045 }
1046 return 0;
1047
1048 err_out_res:
1049 pci_release_regions(pdev);
1050 err_out_disable:
1051 pci_disable_device(pdev);
1052 pci_set_drvdata(pdev, NULL);
1053 free_netdev(dev);
1054
1055 return err;
1056 }
1057
1058 static void __devexit r6040_remove_one(struct pci_dev *pdev)
1059 {
1060 struct net_device *dev = pci_get_drvdata(pdev);
1061
1062 unregister_netdev(dev);
1063 pci_release_regions(pdev);
1064 free_netdev(dev);
1065 pci_disable_device(pdev);
1066 pci_set_drvdata(pdev, NULL);
1067 }
1068
1069
1070 static struct pci_device_id r6040_pci_tbl[] = {
1071 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1072 { 0 }
1073 };
1074 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1075
1076 static struct pci_driver r6040_driver = {
1077 .name = DRV_NAME,
1078 .id_table = r6040_pci_tbl,
1079 .probe = r6040_init_one,
1080 .remove = __devexit_p(r6040_remove_one),
1081 };
1082
1083
1084 static int __init r6040_init(void)
1085 {
1086 return pci_register_driver(&r6040_driver);
1087 }
1088
1089
1090 static void __exit r6040_cleanup(void)
1091 {
1092 pci_unregister_driver(&r6040_driver);
1093 }
1094
1095 module_init(r6040_init);
1096 module_exit(r6040_cleanup);
WRT350N Kernel Patches