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x86: cpa: move clflush_cache_range()
[wrt350n-kernel.git] / drivers / net / sky2.c
blob626190eb91e7ba567ea3c35ef9d26dac2aaf9b7e
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <net/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/debugfs.h>
43 #include <linux/mii.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.21"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3.
61 */
62
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67
68 #define TX_RING_SIZE 512
69 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
70 #define TX_MIN_PENDING 64
71 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
72
73 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
74 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
75 #define TX_WATCHDOG (5 * HZ)
76 #define NAPI_WEIGHT 64
77 #define PHY_RETRIES 1000
78
79 #define SKY2_EEPROM_MAGIC 0x9955aabb
80
81
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static const struct pci_device_id sky2_id_table[] = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
139 { 0 }
140 };
141
142 MODULE_DEVICE_TABLE(pci, sky2_id_table);
143
144 /* Avoid conditionals by using array */
145 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
146 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
147 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
148
149 /* This driver supports yukon2 chipset only */
150 static const char *yukon2_name[] = {
151 "XL", /* 0xb3 */
152 "EC Ultra", /* 0xb4 */
153 "Extreme", /* 0xb5 */
154 "EC", /* 0xb6 */
155 "FE", /* 0xb7 */
156 "FE+", /* 0xb8 */
157 };
158
159 static void sky2_set_multicast(struct net_device *dev);
160
161 /* Access to PHY via serial interconnect */
162 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
163 {
164 int i;
165
166 gma_write16(hw, port, GM_SMI_DATA, val);
167 gma_write16(hw, port, GM_SMI_CTRL,
168 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
169
170 for (i = 0; i < PHY_RETRIES; i++) {
171 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
172 if (ctrl == 0xffff)
173 goto io_error;
174
175 if (!(ctrl & GM_SMI_CT_BUSY))
176 return 0;
177
178 udelay(10);
179 }
180
181 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
182 return -ETIMEDOUT;
183
184 io_error:
185 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
186 return -EIO;
187 }
188
189 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
190 {
191 int i;
192
193 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
194 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
195
196 for (i = 0; i < PHY_RETRIES; i++) {
197 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
198 if (ctrl == 0xffff)
199 goto io_error;
200
201 if (ctrl & GM_SMI_CT_RD_VAL) {
202 *val = gma_read16(hw, port, GM_SMI_DATA);
203 return 0;
204 }
205
206 udelay(10);
207 }
208
209 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
210 return -ETIMEDOUT;
211 io_error:
212 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
213 return -EIO;
214 }
215
216 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
217 {
218 u16 v;
219 __gm_phy_read(hw, port, reg, &v);
220 return v;
221 }
222
223
224 static void sky2_power_on(struct sky2_hw *hw)
225 {
226 /* switch power to VCC (WA for VAUX problem) */
227 sky2_write8(hw, B0_POWER_CTRL,
228 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
229
230 /* disable Core Clock Division, */
231 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
232
233 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
234 /* enable bits are inverted */
235 sky2_write8(hw, B2_Y2_CLK_GATE,
236 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
237 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
238 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
239 else
240 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
241
242 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
243 u32 reg;
244
245 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
246
247 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
248 /* set all bits to 0 except bits 15..12 and 8 */
249 reg &= P_ASPM_CONTROL_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
251
252 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
253 /* set all bits to 0 except bits 28 & 27 */
254 reg &= P_CTL_TIM_VMAIN_AV_MSK;
255 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
256
257 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
258
259 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
260 reg = sky2_read32(hw, B2_GP_IO);
261 reg |= GLB_GPIO_STAT_RACE_DIS;
262 sky2_write32(hw, B2_GP_IO, reg);
263
264 sky2_read32(hw, B2_GP_IO);
265 }
266 }
267
268 static void sky2_power_aux(struct sky2_hw *hw)
269 {
270 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
271 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
272 else
273 /* enable bits are inverted */
274 sky2_write8(hw, B2_Y2_CLK_GATE,
275 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
278
279 /* switch power to VAUX */
280 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
281 sky2_write8(hw, B0_POWER_CTRL,
282 (PC_VAUX_ENA | PC_VCC_ENA |
283 PC_VAUX_ON | PC_VCC_OFF));
284 }
285
286 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
287 {
288 u16 reg;
289
290 /* disable all GMAC IRQ's */
291 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
292
293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
297
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
301 }
302
303 /* flow control to advertise bits */
304 static const u16 copper_fc_adv[] = {
305 [FC_NONE] = 0,
306 [FC_TX] = PHY_M_AN_ASP,
307 [FC_RX] = PHY_M_AN_PC,
308 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
309 };
310
311 /* flow control to advertise bits when using 1000BaseX */
312 static const u16 fiber_fc_adv[] = {
313 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
314 [FC_TX] = PHY_M_P_ASYM_MD_X,
315 [FC_RX] = PHY_M_P_SYM_MD_X,
316 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
317 };
318
319 /* flow control to GMA disable bits */
320 static const u16 gm_fc_disable[] = {
321 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
322 [FC_TX] = GM_GPCR_FC_RX_DIS,
323 [FC_RX] = GM_GPCR_FC_TX_DIS,
324 [FC_BOTH] = 0,
325 };
326
327
328 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
329 {
330 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
331 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
332
333 if (sky2->autoneg == AUTONEG_ENABLE &&
334 !(hw->flags & SKY2_HW_NEWER_PHY)) {
335 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
336
337 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
338 PHY_M_EC_MAC_S_MSK);
339 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
340
341 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
342 if (hw->chip_id == CHIP_ID_YUKON_EC)
343 /* set downshift counter to 3x and enable downshift */
344 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
345 else
346 /* set master & slave downshift counter to 1x */
347 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
348
349 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
350 }
351
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 if (sky2_is_copper(hw)) {
354 if (!(hw->flags & SKY2_HW_GIGABIT)) {
355 /* enable automatic crossover */
356 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
357
358 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
359 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
360 u16 spec;
361
362 /* Enable Class A driver for FE+ A0 */
363 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
364 spec |= PHY_M_FESC_SEL_CL_A;
365 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
366 }
367 } else {
368 /* disable energy detect */
369 ctrl &= ~PHY_M_PC_EN_DET_MSK;
370
371 /* enable automatic crossover */
372 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
373
374 /* downshift on PHY 88E1112 and 88E1149 is changed */
375 if (sky2->autoneg == AUTONEG_ENABLE
376 && (hw->flags & SKY2_HW_NEWER_PHY)) {
377 /* set downshift counter to 3x and enable downshift */
378 ctrl &= ~PHY_M_PC_DSC_MSK;
379 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
380 }
381 }
382 } else {
383 /* workaround for deviation #4.88 (CRC errors) */
384 /* disable Automatic Crossover */
385
386 ctrl &= ~PHY_M_PC_MDIX_MSK;
387 }
388
389 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
390
391 /* special setup for PHY 88E1112 Fiber */
392 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
393 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
394
395 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
396 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
397 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
398 ctrl &= ~PHY_M_MAC_MD_MSK;
399 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
400 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
401
402 if (hw->pmd_type == 'P') {
403 /* select page 1 to access Fiber registers */
404 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
405
406 /* for SFP-module set SIGDET polarity to low */
407 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
408 ctrl |= PHY_M_FIB_SIGD_POL;
409 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
410 }
411
412 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
413 }
414
415 ctrl = PHY_CT_RESET;
416 ct1000 = 0;
417 adv = PHY_AN_CSMA;
418 reg = 0;
419
420 if (sky2->autoneg == AUTONEG_ENABLE) {
421 if (sky2_is_copper(hw)) {
422 if (sky2->advertising & ADVERTISED_1000baseT_Full)
423 ct1000 |= PHY_M_1000C_AFD;
424 if (sky2->advertising & ADVERTISED_1000baseT_Half)
425 ct1000 |= PHY_M_1000C_AHD;
426 if (sky2->advertising & ADVERTISED_100baseT_Full)
427 adv |= PHY_M_AN_100_FD;
428 if (sky2->advertising & ADVERTISED_100baseT_Half)
429 adv |= PHY_M_AN_100_HD;
430 if (sky2->advertising & ADVERTISED_10baseT_Full)
431 adv |= PHY_M_AN_10_FD;
432 if (sky2->advertising & ADVERTISED_10baseT_Half)
433 adv |= PHY_M_AN_10_HD;
434
435 adv |= copper_fc_adv[sky2->flow_mode];
436 } else { /* special defines for FIBER (88E1040S only) */
437 if (sky2->advertising & ADVERTISED_1000baseT_Full)
438 adv |= PHY_M_AN_1000X_AFD;
439 if (sky2->advertising & ADVERTISED_1000baseT_Half)
440 adv |= PHY_M_AN_1000X_AHD;
441
442 adv |= fiber_fc_adv[sky2->flow_mode];
443 }
444
445 /* Restart Auto-negotiation */
446 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
447 } else {
448 /* forced speed/duplex settings */
449 ct1000 = PHY_M_1000C_MSE;
450
451 /* Disable auto update for duplex flow control and speed */
452 reg |= GM_GPCR_AU_ALL_DIS;
453
454 switch (sky2->speed) {
455 case SPEED_1000:
456 ctrl |= PHY_CT_SP1000;
457 reg |= GM_GPCR_SPEED_1000;
458 break;
459 case SPEED_100:
460 ctrl |= PHY_CT_SP100;
461 reg |= GM_GPCR_SPEED_100;
462 break;
463 }
464
465 if (sky2->duplex == DUPLEX_FULL) {
466 reg |= GM_GPCR_DUP_FULL;
467 ctrl |= PHY_CT_DUP_MD;
468 } else if (sky2->speed < SPEED_1000)
469 sky2->flow_mode = FC_NONE;
470
471
472 reg |= gm_fc_disable[sky2->flow_mode];
473
474 /* Forward pause packets to GMAC? */
475 if (sky2->flow_mode & FC_RX)
476 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
477 else
478 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
479 }
480
481 gma_write16(hw, port, GM_GP_CTRL, reg);
482
483 if (hw->flags & SKY2_HW_GIGABIT)
484 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
485
486 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
487 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
488
489 /* Setup Phy LED's */
490 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
491 ledover = 0;
492
493 switch (hw->chip_id) {
494 case CHIP_ID_YUKON_FE:
495 /* on 88E3082 these bits are at 11..9 (shifted left) */
496 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
497
498 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
499
500 /* delete ACT LED control bits */
501 ctrl &= ~PHY_M_FELP_LED1_MSK;
502 /* change ACT LED control to blink mode */
503 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
504 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
505 break;
506
507 case CHIP_ID_YUKON_FE_P:
508 /* Enable Link Partner Next Page */
509 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
510 ctrl |= PHY_M_PC_ENA_LIP_NP;
511
512 /* disable Energy Detect and enable scrambler */
513 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
514 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
515
516 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
517 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
518 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
519 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
520
521 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
522 break;
523
524 case CHIP_ID_YUKON_XL:
525 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
526
527 /* select page 3 to access LED control register */
528 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
529
530 /* set LED Function Control register */
531 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
532 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
533 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
534 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
535 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
536
537 /* set Polarity Control register */
538 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
539 (PHY_M_POLC_LS1_P_MIX(4) |
540 PHY_M_POLC_IS0_P_MIX(4) |
541 PHY_M_POLC_LOS_CTRL(2) |
542 PHY_M_POLC_INIT_CTRL(2) |
543 PHY_M_POLC_STA1_CTRL(2) |
544 PHY_M_POLC_STA0_CTRL(2)));
545
546 /* restore page register */
547 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
548 break;
549
550 case CHIP_ID_YUKON_EC_U:
551 case CHIP_ID_YUKON_EX:
552 case CHIP_ID_YUKON_SUPR:
553 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
554
555 /* select page 3 to access LED control register */
556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
557
558 /* set LED Function Control register */
559 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
560 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
561 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
562 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
563 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
564
565 /* set Blink Rate in LED Timer Control Register */
566 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
567 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
568 /* restore page register */
569 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
570 break;
571
572 default:
573 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
574 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
575 /* turn off the Rx LED (LED_RX) */
576 ledover &= ~PHY_M_LED_MO_RX;
577 }
578
579 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
580 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
581 /* apply fixes in PHY AFE */
582 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
583
584 /* increase differential signal amplitude in 10BASE-T */
585 gm_phy_write(hw, port, 0x18, 0xaa99);
586 gm_phy_write(hw, port, 0x17, 0x2011);
587
588 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
589 gm_phy_write(hw, port, 0x18, 0xa204);
590 gm_phy_write(hw, port, 0x17, 0x2002);
591
592 /* set page register to 0 */
593 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
594 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
595 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
596 /* apply workaround for integrated resistors calibration */
597 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
598 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
599 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
600 /* no effect on Yukon-XL */
601 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
602
603 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
604 /* turn on 100 Mbps LED (LED_LINK100) */
605 ledover |= PHY_M_LED_MO_100;
606 }
607
608 if (ledover)
609 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
610
611 }
612
613 /* Enable phy interrupt on auto-negotiation complete (or link up) */
614 if (sky2->autoneg == AUTONEG_ENABLE)
615 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
616 else
617 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
618 }
619
620 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
621 {
622 u32 reg1;
623 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
624 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
625
626 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
627 /* Turn on/off phy power saving */
628 if (onoff)
629 reg1 &= ~phy_power[port];
630 else
631 reg1 |= phy_power[port];
632
633 if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
634 reg1 |= coma_mode[port];
635
636 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
637 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
638
639 udelay(100);
640 }
641
642 /* Force a renegotiation */
643 static void sky2_phy_reinit(struct sky2_port *sky2)
644 {
645 spin_lock_bh(&sky2->phy_lock);
646 sky2_phy_init(sky2->hw, sky2->port);
647 spin_unlock_bh(&sky2->phy_lock);
648 }
649
650 /* Put device in state to listen for Wake On Lan */
651 static void sky2_wol_init(struct sky2_port *sky2)
652 {
653 struct sky2_hw *hw = sky2->hw;
654 unsigned port = sky2->port;
655 enum flow_control save_mode;
656 u16 ctrl;
657 u32 reg1;
658
659 /* Bring hardware out of reset */
660 sky2_write16(hw, B0_CTST, CS_RST_CLR);
661 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
662
663 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
664 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
665
666 /* Force to 10/100
667 * sky2_reset will re-enable on resume
668 */
669 save_mode = sky2->flow_mode;
670 ctrl = sky2->advertising;
671
672 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
673 sky2->flow_mode = FC_NONE;
674 sky2_phy_power(hw, port, 1);
675 sky2_phy_reinit(sky2);
676
677 sky2->flow_mode = save_mode;
678 sky2->advertising = ctrl;
679
680 /* Set GMAC to no flow control and auto update for speed/duplex */
681 gma_write16(hw, port, GM_GP_CTRL,
682 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
683 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
684
685 /* Set WOL address */
686 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
687 sky2->netdev->dev_addr, ETH_ALEN);
688
689 /* Turn on appropriate WOL control bits */
690 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
691 ctrl = 0;
692 if (sky2->wol & WAKE_PHY)
693 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
694 else
695 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
696
697 if (sky2->wol & WAKE_MAGIC)
698 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
699 else
700 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
701
702 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
703 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
704
705 /* Turn on legacy PCI-Express PME mode */
706 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
707 reg1 |= PCI_Y2_PME_LEGACY;
708 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
709
710 /* block receiver */
711 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
712
713 }
714
715 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
716 {
717 struct net_device *dev = hw->dev[port];
718
719 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
720 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
721 hw->chip_id == CHIP_ID_YUKON_FE_P ||
722 hw->chip_id == CHIP_ID_YUKON_SUPR) {
723 /* Yukon-Extreme B0 and further Extreme devices */
724 /* enable Store & Forward mode for TX */
725
726 if (dev->mtu <= ETH_DATA_LEN)
727 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
728 TX_JUMBO_DIS | TX_STFW_ENA);
729
730 else
731 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
732 TX_JUMBO_ENA| TX_STFW_ENA);
733 } else {
734 if (dev->mtu <= ETH_DATA_LEN)
735 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
736 else {
737 /* set Tx GMAC FIFO Almost Empty Threshold */
738 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
739 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
740
741 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
742
743 /* Can't do offload because of lack of store/forward */
744 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
745 }
746 }
747 }
748
749 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
750 {
751 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
752 u16 reg;
753 u32 rx_reg;
754 int i;
755 const u8 *addr = hw->dev[port]->dev_addr;
756
757 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
758 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
759
760 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
761
762 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
763 /* WA DEV_472 -- looks like crossed wires on port 2 */
764 /* clear GMAC 1 Control reset */
765 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
766 do {
767 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
768 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
769 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
770 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
771 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
772 }
773
774 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
775
776 /* Enable Transmit FIFO Underrun */
777 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
778
779 spin_lock_bh(&sky2->phy_lock);
780 sky2_phy_init(hw, port);
781 spin_unlock_bh(&sky2->phy_lock);
782
783 /* MIB clear */
784 reg = gma_read16(hw, port, GM_PHY_ADDR);
785 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
786
787 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
788 gma_read16(hw, port, i);
789 gma_write16(hw, port, GM_PHY_ADDR, reg);
790
791 /* transmit control */
792 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
793
794 /* receive control reg: unicast + multicast + no FCS */
795 gma_write16(hw, port, GM_RX_CTRL,
796 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
797
798 /* transmit flow control */
799 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
800
801 /* transmit parameter */
802 gma_write16(hw, port, GM_TX_PARAM,
803 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
804 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
805 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
806 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
807
808 /* serial mode register */
809 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
810 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
811
812 if (hw->dev[port]->mtu > ETH_DATA_LEN)
813 reg |= GM_SMOD_JUMBO_ENA;
814
815 gma_write16(hw, port, GM_SERIAL_MODE, reg);
816
817 /* virtual address for data */
818 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
819
820 /* physical address: used for pause frames */
821 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
822
823 /* ignore counter overflows */
824 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
825 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
826 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
827
828 /* Configure Rx MAC FIFO */
829 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
830 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
831 if (hw->chip_id == CHIP_ID_YUKON_EX ||
832 hw->chip_id == CHIP_ID_YUKON_FE_P)
833 rx_reg |= GMF_RX_OVER_ON;
834
835 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
836
837 if (hw->chip_id == CHIP_ID_YUKON_XL) {
838 /* Hardware errata - clear flush mask */
839 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
840 } else {
841 /* Flush Rx MAC FIFO on any flow control or error */
842 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
843 }
844
845 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
846 reg = RX_GMF_FL_THR_DEF + 1;
847 /* Another magic mystery workaround from sk98lin */
848 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
849 hw->chip_rev == CHIP_REV_YU_FE2_A0)
850 reg = 0x178;
851 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
852
853 /* Configure Tx MAC FIFO */
854 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
855 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
856
857 /* On chips without ram buffer, pause is controled by MAC level */
858 if (sky2_read8(hw, B2_E_0) == 0) {
859 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
860 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
861
862 sky2_set_tx_stfwd(hw, port);
863 }
864
865 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
866 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
867 /* disable dynamic watermark */
868 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
869 reg &= ~TX_DYN_WM_ENA;
870 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
871 }
872 }
873
874 /* Assign Ram Buffer allocation to queue */
875 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
876 {
877 u32 end;
878
879 /* convert from K bytes to qwords used for hw register */
880 start *= 1024/8;
881 space *= 1024/8;
882 end = start + space - 1;
883
884 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
885 sky2_write32(hw, RB_ADDR(q, RB_START), start);
886 sky2_write32(hw, RB_ADDR(q, RB_END), end);
887 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
888 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
889
890 if (q == Q_R1 || q == Q_R2) {
891 u32 tp = space - space/4;
892
893 /* On receive queue's set the thresholds
894 * give receiver priority when > 3/4 full
895 * send pause when down to 2K
896 */
897 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
898 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
899
900 tp = space - 2048/8;
901 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
902 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
903 } else {
904 /* Enable store & forward on Tx queue's because
905 * Tx FIFO is only 1K on Yukon
906 */
907 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
908 }
909
910 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
911 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
912 }
913
914 /* Setup Bus Memory Interface */
915 static void sky2_qset(struct sky2_hw *hw, u16 q)
916 {
917 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
918 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
919 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
920 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
921 }
922
923 /* Setup prefetch unit registers. This is the interface between
924 * hardware and driver list elements
925 */
926 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
927 u64 addr, u32 last)
928 {
929 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
930 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
931 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
932 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
933 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
934 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
935
936 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
937 }
938
939 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
940 {
941 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
942
943 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
944 le->ctrl = 0;
945 return le;
946 }
947
948 static void tx_init(struct sky2_port *sky2)
949 {
950 struct sky2_tx_le *le;
951
952 sky2->tx_prod = sky2->tx_cons = 0;
953 sky2->tx_tcpsum = 0;
954 sky2->tx_last_mss = 0;
955
956 le = get_tx_le(sky2);
957 le->addr = 0;
958 le->opcode = OP_ADDR64 | HW_OWNER;
959 }
960
961 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
962 struct sky2_tx_le *le)
963 {
964 return sky2->tx_ring + (le - sky2->tx_le);
965 }
966
967 /* Update chip's next pointer */
968 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
969 {
970 /* Make sure write' to descriptors are complete before we tell hardware */
971 wmb();
972 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
973
974 /* Synchronize I/O on since next processor may write to tail */
975 mmiowb();
976 }
977
978
979 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
980 {
981 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
982 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
983 le->ctrl = 0;
984 return le;
985 }
986
987 /* Build description to hardware for one receive segment */
988 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
989 dma_addr_t map, unsigned len)
990 {
991 struct sky2_rx_le *le;
992
993 if (sizeof(dma_addr_t) > sizeof(u32)) {
994 le = sky2_next_rx(sky2);
995 le->addr = cpu_to_le32(upper_32_bits(map));
996 le->opcode = OP_ADDR64 | HW_OWNER;
997 }
998
999 le = sky2_next_rx(sky2);
1000 le->addr = cpu_to_le32((u32) map);
1001 le->length = cpu_to_le16(len);
1002 le->opcode = op | HW_OWNER;
1003 }
1004
1005 /* Build description to hardware for one possibly fragmented skb */
1006 static void sky2_rx_submit(struct sky2_port *sky2,
1007 const struct rx_ring_info *re)
1008 {
1009 int i;
1010
1011 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1012
1013 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1014 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1015 }
1016
1017
1018 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1019 unsigned size)
1020 {
1021 struct sk_buff *skb = re->skb;
1022 int i;
1023
1024 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1025 pci_unmap_len_set(re, data_size, size);
1026
1027 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1028 re->frag_addr[i] = pci_map_page(pdev,
1029 skb_shinfo(skb)->frags[i].page,
1030 skb_shinfo(skb)->frags[i].page_offset,
1031 skb_shinfo(skb)->frags[i].size,
1032 PCI_DMA_FROMDEVICE);
1033 }
1034
1035 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1036 {
1037 struct sk_buff *skb = re->skb;
1038 int i;
1039
1040 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1041 PCI_DMA_FROMDEVICE);
1042
1043 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1044 pci_unmap_page(pdev, re->frag_addr[i],
1045 skb_shinfo(skb)->frags[i].size,
1046 PCI_DMA_FROMDEVICE);
1047 }
1048
1049 /* Tell chip where to start receive checksum.
1050 * Actually has two checksums, but set both same to avoid possible byte
1051 * order problems.
1052 */
1053 static void rx_set_checksum(struct sky2_port *sky2)
1054 {
1055 struct sky2_rx_le *le = sky2_next_rx(sky2);
1056
1057 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1058 le->ctrl = 0;
1059 le->opcode = OP_TCPSTART | HW_OWNER;
1060
1061 sky2_write32(sky2->hw,
1062 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1063 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1064 }
1065
1066 /*
1067 * The RX Stop command will not work for Yukon-2 if the BMU does not
1068 * reach the end of packet and since we can't make sure that we have
1069 * incoming data, we must reset the BMU while it is not doing a DMA
1070 * transfer. Since it is possible that the RX path is still active,
1071 * the RX RAM buffer will be stopped first, so any possible incoming
1072 * data will not trigger a DMA. After the RAM buffer is stopped, the
1073 * BMU is polled until any DMA in progress is ended and only then it
1074 * will be reset.
1075 */
1076 static void sky2_rx_stop(struct sky2_port *sky2)
1077 {
1078 struct sky2_hw *hw = sky2->hw;
1079 unsigned rxq = rxqaddr[sky2->port];
1080 int i;
1081
1082 /* disable the RAM Buffer receive queue */
1083 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1084
1085 for (i = 0; i < 0xffff; i++)
1086 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1087 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1088 goto stopped;
1089
1090 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1091 sky2->netdev->name);
1092 stopped:
1093 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1094
1095 /* reset the Rx prefetch unit */
1096 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1097 mmiowb();
1098 }
1099
1100 /* Clean out receive buffer area, assumes receiver hardware stopped */
1101 static void sky2_rx_clean(struct sky2_port *sky2)
1102 {
1103 unsigned i;
1104
1105 memset(sky2->rx_le, 0, RX_LE_BYTES);
1106 for (i = 0; i < sky2->rx_pending; i++) {
1107 struct rx_ring_info *re = sky2->rx_ring + i;
1108
1109 if (re->skb) {
1110 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1111 kfree_skb(re->skb);
1112 re->skb = NULL;
1113 }
1114 }
1115 }
1116
1117 /* Basic MII support */
1118 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1119 {
1120 struct mii_ioctl_data *data = if_mii(ifr);
1121 struct sky2_port *sky2 = netdev_priv(dev);
1122 struct sky2_hw *hw = sky2->hw;
1123 int err = -EOPNOTSUPP;
1124
1125 if (!netif_running(dev))
1126 return -ENODEV; /* Phy still in reset */
1127
1128 switch (cmd) {
1129 case SIOCGMIIPHY:
1130 data->phy_id = PHY_ADDR_MARV;
1131
1132 /* fallthru */
1133 case SIOCGMIIREG: {
1134 u16 val = 0;
1135
1136 spin_lock_bh(&sky2->phy_lock);
1137 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1138 spin_unlock_bh(&sky2->phy_lock);
1139
1140 data->val_out = val;
1141 break;
1142 }
1143
1144 case SIOCSMIIREG:
1145 if (!capable(CAP_NET_ADMIN))
1146 return -EPERM;
1147
1148 spin_lock_bh(&sky2->phy_lock);
1149 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1150 data->val_in);
1151 spin_unlock_bh(&sky2->phy_lock);
1152 break;
1153 }
1154 return err;
1155 }
1156
1157 #ifdef SKY2_VLAN_TAG_USED
1158 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1159 {
1160 struct sky2_port *sky2 = netdev_priv(dev);
1161 struct sky2_hw *hw = sky2->hw;
1162 u16 port = sky2->port;
1163
1164 netif_tx_lock_bh(dev);
1165 napi_disable(&hw->napi);
1166
1167 sky2->vlgrp = grp;
1168 if (grp) {
1169 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1170 RX_VLAN_STRIP_ON);
1171 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1172 TX_VLAN_TAG_ON);
1173 } else {
1174 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1175 RX_VLAN_STRIP_OFF);
1176 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1177 TX_VLAN_TAG_OFF);
1178 }
1179
1180 sky2_read32(hw, B0_Y2_SP_LISR);
1181 napi_enable(&hw->napi);
1182 netif_tx_unlock_bh(dev);
1183 }
1184 #endif
1185
1186 /*
1187 * Allocate an skb for receiving. If the MTU is large enough
1188 * make the skb non-linear with a fragment list of pages.
1189 */
1190 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1191 {
1192 struct sk_buff *skb;
1193 int i;
1194
1195 if (sky2->hw->flags & SKY2_HW_FIFO_HANG_CHECK) {
1196 unsigned char *start;
1197 /*
1198 * Workaround for a bug in FIFO that cause hang
1199 * if the FIFO if the receive buffer is not 64 byte aligned.
1200 * The buffer returned from netdev_alloc_skb is
1201 * aligned except if slab debugging is enabled.
1202 */
1203 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + 8);
1204 if (!skb)
1205 goto nomem;
1206 start = PTR_ALIGN(skb->data, 8);
1207 skb_reserve(skb, start - skb->data);
1208 } else {
1209 skb = netdev_alloc_skb(sky2->netdev,
1210 sky2->rx_data_size + NET_IP_ALIGN);
1211 if (!skb)
1212 goto nomem;
1213 skb_reserve(skb, NET_IP_ALIGN);
1214 }
1215
1216 for (i = 0; i < sky2->rx_nfrags; i++) {
1217 struct page *page = alloc_page(GFP_ATOMIC);
1218
1219 if (!page)
1220 goto free_partial;
1221 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1222 }
1223
1224 return skb;
1225 free_partial:
1226 kfree_skb(skb);
1227 nomem:
1228 return NULL;
1229 }
1230
1231 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1232 {
1233 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1234 }
1235
1236 /*
1237 * Allocate and setup receiver buffer pool.
1238 * Normal case this ends up creating one list element for skb
1239 * in the receive ring. Worst case if using large MTU and each
1240 * allocation falls on a different 64 bit region, that results
1241 * in 6 list elements per ring entry.
1242 * One element is used for checksum enable/disable, and one
1243 * extra to avoid wrap.
1244 */
1245 static int sky2_rx_start(struct sky2_port *sky2)
1246 {
1247 struct sky2_hw *hw = sky2->hw;
1248 struct rx_ring_info *re;
1249 unsigned rxq = rxqaddr[sky2->port];
1250 unsigned i, size, thresh;
1251
1252 sky2->rx_put = sky2->rx_next = 0;
1253 sky2_qset(hw, rxq);
1254
1255 /* On PCI express lowering the watermark gives better performance */
1256 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1257 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1258
1259 /* These chips have no ram buffer?
1260 * MAC Rx RAM Read is controlled by hardware */
1261 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1262 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1263 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1264 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1265
1266 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1267
1268 if (!(hw->flags & SKY2_HW_NEW_LE))
1269 rx_set_checksum(sky2);
1270
1271 /* Space needed for frame data + headers rounded up */
1272 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1273
1274 /* Stopping point for hardware truncation */
1275 thresh = (size - 8) / sizeof(u32);
1276
1277 sky2->rx_nfrags = size >> PAGE_SHIFT;
1278 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1279
1280 /* Compute residue after pages */
1281 size -= sky2->rx_nfrags << PAGE_SHIFT;
1282
1283 /* Optimize to handle small packets and headers */
1284 if (size < copybreak)
1285 size = copybreak;
1286 if (size < ETH_HLEN)
1287 size = ETH_HLEN;
1288
1289 sky2->rx_data_size = size;
1290
1291 /* Fill Rx ring */
1292 for (i = 0; i < sky2->rx_pending; i++) {
1293 re = sky2->rx_ring + i;
1294
1295 re->skb = sky2_rx_alloc(sky2);
1296 if (!re->skb)
1297 goto nomem;
1298
1299 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1300 sky2_rx_submit(sky2, re);
1301 }
1302
1303 /*
1304 * The receiver hangs if it receives frames larger than the
1305 * packet buffer. As a workaround, truncate oversize frames, but
1306 * the register is limited to 9 bits, so if you do frames > 2052
1307 * you better get the MTU right!
1308 */
1309 if (thresh > 0x1ff)
1310 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1311 else {
1312 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1313 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1314 }
1315
1316 /* Tell chip about available buffers */
1317 sky2_rx_update(sky2, rxq);
1318 return 0;
1319 nomem:
1320 sky2_rx_clean(sky2);
1321 return -ENOMEM;
1322 }
1323
1324 /* Bring up network interface. */
1325 static int sky2_up(struct net_device *dev)
1326 {
1327 struct sky2_port *sky2 = netdev_priv(dev);
1328 struct sky2_hw *hw = sky2->hw;
1329 unsigned port = sky2->port;
1330 u32 imask, ramsize;
1331 int cap, err = -ENOMEM;
1332 struct net_device *otherdev = hw->dev[sky2->port^1];
1333
1334 /*
1335 * On dual port PCI-X card, there is an problem where status
1336 * can be received out of order due to split transactions
1337 */
1338 if (otherdev && netif_running(otherdev) &&
1339 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1340 u16 cmd;
1341
1342 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1343 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1344 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1345
1346 }
1347
1348 if (netif_msg_ifup(sky2))
1349 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1350
1351 netif_carrier_off(dev);
1352
1353 /* must be power of 2 */
1354 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1355 TX_RING_SIZE *
1356 sizeof(struct sky2_tx_le),
1357 &sky2->tx_le_map);
1358 if (!sky2->tx_le)
1359 goto err_out;
1360
1361 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1362 GFP_KERNEL);
1363 if (!sky2->tx_ring)
1364 goto err_out;
1365
1366 tx_init(sky2);
1367
1368 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1369 &sky2->rx_le_map);
1370 if (!sky2->rx_le)
1371 goto err_out;
1372 memset(sky2->rx_le, 0, RX_LE_BYTES);
1373
1374 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1375 GFP_KERNEL);
1376 if (!sky2->rx_ring)
1377 goto err_out;
1378
1379 sky2_phy_power(hw, port, 1);
1380
1381 sky2_mac_init(hw, port);
1382
1383 /* Register is number of 4K blocks on internal RAM buffer. */
1384 ramsize = sky2_read8(hw, B2_E_0) * 4;
1385 if (ramsize > 0) {
1386 u32 rxspace;
1387
1388 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1389 if (ramsize < 16)
1390 rxspace = ramsize / 2;
1391 else
1392 rxspace = 8 + (2*(ramsize - 16))/3;
1393
1394 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1395 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1396
1397 /* Make sure SyncQ is disabled */
1398 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1399 RB_RST_SET);
1400 }
1401
1402 sky2_qset(hw, txqaddr[port]);
1403
1404 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1405 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1406 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1407
1408 /* Set almost empty threshold */
1409 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1410 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1411 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1412
1413 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1414 TX_RING_SIZE - 1);
1415
1416 err = sky2_rx_start(sky2);
1417 if (err)
1418 goto err_out;
1419
1420 /* Enable interrupts from phy/mac for port */
1421 imask = sky2_read32(hw, B0_IMSK);
1422 imask |= portirq_msk[port];
1423 sky2_write32(hw, B0_IMSK, imask);
1424
1425 return 0;
1426
1427 err_out:
1428 if (sky2->rx_le) {
1429 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1430 sky2->rx_le, sky2->rx_le_map);
1431 sky2->rx_le = NULL;
1432 }
1433 if (sky2->tx_le) {
1434 pci_free_consistent(hw->pdev,
1435 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1436 sky2->tx_le, sky2->tx_le_map);
1437 sky2->tx_le = NULL;
1438 }
1439 kfree(sky2->tx_ring);
1440 kfree(sky2->rx_ring);
1441
1442 sky2->tx_ring = NULL;
1443 sky2->rx_ring = NULL;
1444 return err;
1445 }
1446
1447 /* Modular subtraction in ring */
1448 static inline int tx_dist(unsigned tail, unsigned head)
1449 {
1450 return (head - tail) & (TX_RING_SIZE - 1);
1451 }
1452
1453 /* Number of list elements available for next tx */
1454 static inline int tx_avail(const struct sky2_port *sky2)
1455 {
1456 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1457 }
1458
1459 /* Estimate of number of transmit list elements required */
1460 static unsigned tx_le_req(const struct sk_buff *skb)
1461 {
1462 unsigned count;
1463
1464 count = sizeof(dma_addr_t) / sizeof(u32);
1465 count += skb_shinfo(skb)->nr_frags * count;
1466
1467 if (skb_is_gso(skb))
1468 ++count;
1469
1470 if (skb->ip_summed == CHECKSUM_PARTIAL)
1471 ++count;
1472
1473 return count;
1474 }
1475
1476 /*
1477 * Put one packet in ring for transmit.
1478 * A single packet can generate multiple list elements, and
1479 * the number of ring elements will probably be less than the number
1480 * of list elements used.
1481 */
1482 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1483 {
1484 struct sky2_port *sky2 = netdev_priv(dev);
1485 struct sky2_hw *hw = sky2->hw;
1486 struct sky2_tx_le *le = NULL;
1487 struct tx_ring_info *re;
1488 unsigned i, len;
1489 dma_addr_t mapping;
1490 u16 mss;
1491 u8 ctrl;
1492
1493 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1494 return NETDEV_TX_BUSY;
1495
1496 if (unlikely(netif_msg_tx_queued(sky2)))
1497 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1498 dev->name, sky2->tx_prod, skb->len);
1499
1500 len = skb_headlen(skb);
1501 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1502
1503 /* Send high bits if needed */
1504 if (sizeof(dma_addr_t) > sizeof(u32)) {
1505 le = get_tx_le(sky2);
1506 le->addr = cpu_to_le32(upper_32_bits(mapping));
1507 le->opcode = OP_ADDR64 | HW_OWNER;
1508 }
1509
1510 /* Check for TCP Segmentation Offload */
1511 mss = skb_shinfo(skb)->gso_size;
1512 if (mss != 0) {
1513
1514 if (!(hw->flags & SKY2_HW_NEW_LE))
1515 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1516
1517 if (mss != sky2->tx_last_mss) {
1518 le = get_tx_le(sky2);
1519 le->addr = cpu_to_le32(mss);
1520
1521 if (hw->flags & SKY2_HW_NEW_LE)
1522 le->opcode = OP_MSS | HW_OWNER;
1523 else
1524 le->opcode = OP_LRGLEN | HW_OWNER;
1525 sky2->tx_last_mss = mss;
1526 }
1527 }
1528
1529 ctrl = 0;
1530 #ifdef SKY2_VLAN_TAG_USED
1531 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1532 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1533 if (!le) {
1534 le = get_tx_le(sky2);
1535 le->addr = 0;
1536 le->opcode = OP_VLAN|HW_OWNER;
1537 } else
1538 le->opcode |= OP_VLAN;
1539 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1540 ctrl |= INS_VLAN;
1541 }
1542 #endif
1543
1544 /* Handle TCP checksum offload */
1545 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1546 /* On Yukon EX (some versions) encoding change. */
1547 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1548 ctrl |= CALSUM; /* auto checksum */
1549 else {
1550 const unsigned offset = skb_transport_offset(skb);
1551 u32 tcpsum;
1552
1553 tcpsum = offset << 16; /* sum start */
1554 tcpsum |= offset + skb->csum_offset; /* sum write */
1555
1556 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1557 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1558 ctrl |= UDPTCP;
1559
1560 if (tcpsum != sky2->tx_tcpsum) {
1561 sky2->tx_tcpsum = tcpsum;
1562
1563 le = get_tx_le(sky2);
1564 le->addr = cpu_to_le32(tcpsum);
1565 le->length = 0; /* initial checksum value */
1566 le->ctrl = 1; /* one packet */
1567 le->opcode = OP_TCPLISW | HW_OWNER;
1568 }
1569 }
1570 }
1571
1572 le = get_tx_le(sky2);
1573 le->addr = cpu_to_le32((u32) mapping);
1574 le->length = cpu_to_le16(len);
1575 le->ctrl = ctrl;
1576 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1577
1578 re = tx_le_re(sky2, le);
1579 re->skb = skb;
1580 pci_unmap_addr_set(re, mapaddr, mapping);
1581 pci_unmap_len_set(re, maplen, len);
1582
1583 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1584 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1585
1586 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1587 frag->size, PCI_DMA_TODEVICE);
1588
1589 if (sizeof(dma_addr_t) > sizeof(u32)) {
1590 le = get_tx_le(sky2);
1591 le->addr = cpu_to_le32(upper_32_bits(mapping));
1592 le->ctrl = 0;
1593 le->opcode = OP_ADDR64 | HW_OWNER;
1594 }
1595
1596 le = get_tx_le(sky2);
1597 le->addr = cpu_to_le32((u32) mapping);
1598 le->length = cpu_to_le16(frag->size);
1599 le->ctrl = ctrl;
1600 le->opcode = OP_BUFFER | HW_OWNER;
1601
1602 re = tx_le_re(sky2, le);
1603 re->skb = skb;
1604 pci_unmap_addr_set(re, mapaddr, mapping);
1605 pci_unmap_len_set(re, maplen, frag->size);
1606 }
1607
1608 le->ctrl |= EOP;
1609
1610 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1611 netif_stop_queue(dev);
1612
1613 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1614
1615 dev->trans_start = jiffies;
1616 return NETDEV_TX_OK;
1617 }
1618
1619 /*
1620 * Free ring elements from starting at tx_cons until "done"
1621 *
1622 * NB: the hardware will tell us about partial completion of multi-part
1623 * buffers so make sure not to free skb to early.
1624 */
1625 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1626 {
1627 struct net_device *dev = sky2->netdev;
1628 struct pci_dev *pdev = sky2->hw->pdev;
1629 unsigned idx;
1630
1631 BUG_ON(done >= TX_RING_SIZE);
1632
1633 for (idx = sky2->tx_cons; idx != done;
1634 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1635 struct sky2_tx_le *le = sky2->tx_le + idx;
1636 struct tx_ring_info *re = sky2->tx_ring + idx;
1637
1638 switch(le->opcode & ~HW_OWNER) {
1639 case OP_LARGESEND:
1640 case OP_PACKET:
1641 pci_unmap_single(pdev,
1642 pci_unmap_addr(re, mapaddr),
1643 pci_unmap_len(re, maplen),
1644 PCI_DMA_TODEVICE);
1645 break;
1646 case OP_BUFFER:
1647 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1648 pci_unmap_len(re, maplen),
1649 PCI_DMA_TODEVICE);
1650 break;
1651 }
1652
1653 if (le->ctrl & EOP) {
1654 if (unlikely(netif_msg_tx_done(sky2)))
1655 printk(KERN_DEBUG "%s: tx done %u\n",
1656 dev->name, idx);
1657
1658 dev->stats.tx_packets++;
1659 dev->stats.tx_bytes += re->skb->len;
1660
1661 dev_kfree_skb_any(re->skb);
1662 sky2->tx_next = RING_NEXT(idx, TX_RING_SIZE);
1663 }
1664 }
1665
1666 sky2->tx_cons = idx;
1667 smp_mb();
1668
1669 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1670 netif_wake_queue(dev);
1671 }
1672
1673 /* Cleanup all untransmitted buffers, assume transmitter not running */
1674 static void sky2_tx_clean(struct net_device *dev)
1675 {
1676 struct sky2_port *sky2 = netdev_priv(dev);
1677
1678 netif_tx_lock_bh(dev);
1679 sky2_tx_complete(sky2, sky2->tx_prod);
1680 netif_tx_unlock_bh(dev);
1681 }
1682
1683 /* Network shutdown */
1684 static int sky2_down(struct net_device *dev)
1685 {
1686 struct sky2_port *sky2 = netdev_priv(dev);
1687 struct sky2_hw *hw = sky2->hw;
1688 unsigned port = sky2->port;
1689 u16 ctrl;
1690 u32 imask;
1691
1692 /* Never really got started! */
1693 if (!sky2->tx_le)
1694 return 0;
1695
1696 if (netif_msg_ifdown(sky2))
1697 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1698
1699 /* Stop more packets from being queued */
1700 netif_stop_queue(dev);
1701
1702 /* Disable port IRQ */
1703 imask = sky2_read32(hw, B0_IMSK);
1704 imask &= ~portirq_msk[port];
1705 sky2_write32(hw, B0_IMSK, imask);
1706
1707 synchronize_irq(hw->pdev->irq);
1708
1709 sky2_gmac_reset(hw, port);
1710
1711 /* Stop transmitter */
1712 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1713 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1714
1715 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1716 RB_RST_SET | RB_DIS_OP_MD);
1717
1718 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1719 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1720 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1721
1722 /* Make sure no packets are pending */
1723 napi_synchronize(&hw->napi);
1724
1725 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1726
1727 /* Workaround shared GMAC reset */
1728 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1729 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1730 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1731
1732 /* Disable Force Sync bit and Enable Alloc bit */
1733 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1734 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1735
1736 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1737 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1738 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1739
1740 /* Reset the PCI FIFO of the async Tx queue */
1741 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1742 BMU_RST_SET | BMU_FIFO_RST);
1743
1744 /* Reset the Tx prefetch units */
1745 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1746 PREF_UNIT_RST_SET);
1747
1748 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1749
1750 sky2_rx_stop(sky2);
1751
1752 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1753 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1754
1755 sky2_phy_power(hw, port, 0);
1756
1757 netif_carrier_off(dev);
1758
1759 /* turn off LED's */
1760 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1761
1762 sky2_tx_clean(dev);
1763 sky2_rx_clean(sky2);
1764
1765 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1766 sky2->rx_le, sky2->rx_le_map);
1767 kfree(sky2->rx_ring);
1768
1769 pci_free_consistent(hw->pdev,
1770 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1771 sky2->tx_le, sky2->tx_le_map);
1772 kfree(sky2->tx_ring);
1773
1774 sky2->tx_le = NULL;
1775 sky2->rx_le = NULL;
1776
1777 sky2->rx_ring = NULL;
1778 sky2->tx_ring = NULL;
1779
1780 return 0;
1781 }
1782
1783 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1784 {
1785 if (hw->flags & SKY2_HW_FIBRE_PHY)
1786 return SPEED_1000;
1787
1788 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1789 if (aux & PHY_M_PS_SPEED_100)
1790 return SPEED_100;
1791 else
1792 return SPEED_10;
1793 }
1794
1795 switch (aux & PHY_M_PS_SPEED_MSK) {
1796 case PHY_M_PS_SPEED_1000:
1797 return SPEED_1000;
1798 case PHY_M_PS_SPEED_100:
1799 return SPEED_100;
1800 default:
1801 return SPEED_10;
1802 }
1803 }
1804
1805 static void sky2_link_up(struct sky2_port *sky2)
1806 {
1807 struct sky2_hw *hw = sky2->hw;
1808 unsigned port = sky2->port;
1809 u16 reg;
1810 static const char *fc_name[] = {
1811 [FC_NONE] = "none",
1812 [FC_TX] = "tx",
1813 [FC_RX] = "rx",
1814 [FC_BOTH] = "both",
1815 };
1816
1817 /* enable Rx/Tx */
1818 reg = gma_read16(hw, port, GM_GP_CTRL);
1819 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1820 gma_write16(hw, port, GM_GP_CTRL, reg);
1821
1822 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1823
1824 netif_carrier_on(sky2->netdev);
1825
1826 mod_timer(&hw->watchdog_timer, jiffies + 1);
1827
1828 /* Turn on link LED */
1829 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1830 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1831
1832 if (netif_msg_link(sky2))
1833 printk(KERN_INFO PFX
1834 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1835 sky2->netdev->name, sky2->speed,
1836 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1837 fc_name[sky2->flow_status]);
1838 }
1839
1840 static void sky2_link_down(struct sky2_port *sky2)
1841 {
1842 struct sky2_hw *hw = sky2->hw;
1843 unsigned port = sky2->port;
1844 u16 reg;
1845
1846 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1847
1848 reg = gma_read16(hw, port, GM_GP_CTRL);
1849 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1850 gma_write16(hw, port, GM_GP_CTRL, reg);
1851
1852 netif_carrier_off(sky2->netdev);
1853
1854 /* Turn on link LED */
1855 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1856
1857 if (netif_msg_link(sky2))
1858 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1859
1860 sky2_phy_init(hw, port);
1861 }
1862
1863 static enum flow_control sky2_flow(int rx, int tx)
1864 {
1865 if (rx)
1866 return tx ? FC_BOTH : FC_RX;
1867 else
1868 return tx ? FC_TX : FC_NONE;
1869 }
1870
1871 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1872 {
1873 struct sky2_hw *hw = sky2->hw;
1874 unsigned port = sky2->port;
1875 u16 advert, lpa;
1876
1877 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1878 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1879 if (lpa & PHY_M_AN_RF) {
1880 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1881 return -1;
1882 }
1883
1884 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1885 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1886 sky2->netdev->name);
1887 return -1;
1888 }
1889
1890 sky2->speed = sky2_phy_speed(hw, aux);
1891 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1892
1893 /* Since the pause result bits seem to in different positions on
1894 * different chips. look at registers.
1895 */
1896 if (hw->flags & SKY2_HW_FIBRE_PHY) {
1897 /* Shift for bits in fiber PHY */
1898 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1899 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1900
1901 if (advert & ADVERTISE_1000XPAUSE)
1902 advert |= ADVERTISE_PAUSE_CAP;
1903 if (advert & ADVERTISE_1000XPSE_ASYM)
1904 advert |= ADVERTISE_PAUSE_ASYM;
1905 if (lpa & LPA_1000XPAUSE)
1906 lpa |= LPA_PAUSE_CAP;
1907 if (lpa & LPA_1000XPAUSE_ASYM)
1908 lpa |= LPA_PAUSE_ASYM;
1909 }
1910
1911 sky2->flow_status = FC_NONE;
1912 if (advert & ADVERTISE_PAUSE_CAP) {
1913 if (lpa & LPA_PAUSE_CAP)
1914 sky2->flow_status = FC_BOTH;
1915 else if (advert & ADVERTISE_PAUSE_ASYM)
1916 sky2->flow_status = FC_RX;
1917 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1918 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1919 sky2->flow_status = FC_TX;
1920 }
1921
1922 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1923 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1924 sky2->flow_status = FC_NONE;
1925
1926 if (sky2->flow_status & FC_TX)
1927 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1928 else
1929 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1930
1931 return 0;
1932 }
1933
1934 /* Interrupt from PHY */
1935 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1936 {
1937 struct net_device *dev = hw->dev[port];
1938 struct sky2_port *sky2 = netdev_priv(dev);
1939 u16 istatus, phystat;
1940
1941 if (!netif_running(dev))
1942 return;
1943
1944 spin_lock(&sky2->phy_lock);
1945 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1946 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1947
1948 if (netif_msg_intr(sky2))
1949 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1950 sky2->netdev->name, istatus, phystat);
1951
1952 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1953 if (sky2_autoneg_done(sky2, phystat) == 0)
1954 sky2_link_up(sky2);
1955 goto out;
1956 }
1957
1958 if (istatus & PHY_M_IS_LSP_CHANGE)
1959 sky2->speed = sky2_phy_speed(hw, phystat);
1960
1961 if (istatus & PHY_M_IS_DUP_CHANGE)
1962 sky2->duplex =
1963 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1964
1965 if (istatus & PHY_M_IS_LST_CHANGE) {
1966 if (phystat & PHY_M_PS_LINK_UP)
1967 sky2_link_up(sky2);
1968 else
1969 sky2_link_down(sky2);
1970 }
1971 out:
1972 spin_unlock(&sky2->phy_lock);
1973 }
1974
1975 /* Transmit timeout is only called if we are running, carrier is up
1976 * and tx queue is full (stopped).
1977 */
1978 static void sky2_tx_timeout(struct net_device *dev)
1979 {
1980 struct sky2_port *sky2 = netdev_priv(dev);
1981 struct sky2_hw *hw = sky2->hw;
1982
1983 if (netif_msg_timer(sky2))
1984 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1985
1986 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1987 dev->name, sky2->tx_cons, sky2->tx_prod,
1988 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1989 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1990
1991 /* can't restart safely under softirq */
1992 schedule_work(&hw->restart_work);
1993 }
1994
1995 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1996 {
1997 struct sky2_port *sky2 = netdev_priv(dev);
1998 struct sky2_hw *hw = sky2->hw;
1999 unsigned port = sky2->port;
2000 int err;
2001 u16 ctl, mode;
2002 u32 imask;
2003
2004 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2005 return -EINVAL;
2006
2007 if (new_mtu > ETH_DATA_LEN &&
2008 (hw->chip_id == CHIP_ID_YUKON_FE ||
2009 hw->chip_id == CHIP_ID_YUKON_FE_P))
2010 return -EINVAL;
2011
2012 if (!netif_running(dev)) {
2013 dev->mtu = new_mtu;
2014 return 0;
2015 }
2016
2017 imask = sky2_read32(hw, B0_IMSK);
2018 sky2_write32(hw, B0_IMSK, 0);
2019
2020 dev->trans_start = jiffies; /* prevent tx timeout */
2021 netif_stop_queue(dev);
2022 napi_disable(&hw->napi);
2023
2024 synchronize_irq(hw->pdev->irq);
2025
2026 if (sky2_read8(hw, B2_E_0) == 0)
2027 sky2_set_tx_stfwd(hw, port);
2028
2029 ctl = gma_read16(hw, port, GM_GP_CTRL);
2030 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2031 sky2_rx_stop(sky2);
2032 sky2_rx_clean(sky2);
2033
2034 dev->mtu = new_mtu;
2035
2036 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2037 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2038
2039 if (dev->mtu > ETH_DATA_LEN)
2040 mode |= GM_SMOD_JUMBO_ENA;
2041
2042 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2043
2044 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2045
2046 err = sky2_rx_start(sky2);
2047 sky2_write32(hw, B0_IMSK, imask);
2048
2049 sky2_read32(hw, B0_Y2_SP_LISR);
2050 napi_enable(&hw->napi);
2051
2052 if (err)
2053 dev_close(dev);
2054 else {
2055 gma_write16(hw, port, GM_GP_CTRL, ctl);
2056
2057 netif_wake_queue(dev);
2058 }
2059
2060 return err;
2061 }
2062
2063 /* For small just reuse existing skb for next receive */
2064 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2065 const struct rx_ring_info *re,
2066 unsigned length)
2067 {
2068 struct sk_buff *skb;
2069
2070 skb = netdev_alloc_skb(sky2->netdev, length + 2);
2071 if (likely(skb)) {
2072 skb_reserve(skb, 2);
2073 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2074 length, PCI_DMA_FROMDEVICE);
2075 skb_copy_from_linear_data(re->skb, skb->data, length);
2076 skb->ip_summed = re->skb->ip_summed;
2077 skb->csum = re->skb->csum;
2078 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2079 length, PCI_DMA_FROMDEVICE);
2080 re->skb->ip_summed = CHECKSUM_NONE;
2081 skb_put(skb, length);
2082 }
2083 return skb;
2084 }
2085
2086 /* Adjust length of skb with fragments to match received data */
2087 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2088 unsigned int length)
2089 {
2090 int i, num_frags;
2091 unsigned int size;
2092
2093 /* put header into skb */
2094 size = min(length, hdr_space);
2095 skb->tail += size;
2096 skb->len += size;
2097 length -= size;
2098
2099 num_frags = skb_shinfo(skb)->nr_frags;
2100 for (i = 0; i < num_frags; i++) {
2101 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2102
2103 if (length == 0) {
2104 /* don't need this page */
2105 __free_page(frag->page);
2106 --skb_shinfo(skb)->nr_frags;
2107 } else {
2108 size = min(length, (unsigned) PAGE_SIZE);
2109
2110 frag->size = size;
2111 skb->data_len += size;
2112 skb->truesize += size;
2113 skb->len += size;
2114 length -= size;
2115 }
2116 }
2117 }
2118
2119 /* Normal packet - take skb from ring element and put in a new one */
2120 static struct sk_buff *receive_new(struct sky2_port *sky2,
2121 struct rx_ring_info *re,
2122 unsigned int length)
2123 {
2124 struct sk_buff *skb, *nskb;
2125 unsigned hdr_space = sky2->rx_data_size;
2126
2127 /* Don't be tricky about reusing pages (yet) */
2128 nskb = sky2_rx_alloc(sky2);
2129 if (unlikely(!nskb))
2130 return NULL;
2131
2132 skb = re->skb;
2133 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2134
2135 prefetch(skb->data);
2136 re->skb = nskb;
2137 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2138
2139 if (skb_shinfo(skb)->nr_frags)
2140 skb_put_frags(skb, hdr_space, length);
2141 else
2142 skb_put(skb, length);
2143 return skb;
2144 }
2145
2146 /*
2147 * Receive one packet.
2148 * For larger packets, get new buffer.
2149 */
2150 static struct sk_buff *sky2_receive(struct net_device *dev,
2151 u16 length, u32 status)
2152 {
2153 struct sky2_port *sky2 = netdev_priv(dev);
2154 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2155 struct sk_buff *skb = NULL;
2156 u16 count = (status & GMR_FS_LEN) >> 16;
2157
2158 #ifdef SKY2_VLAN_TAG_USED
2159 /* Account for vlan tag */
2160 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2161 count -= VLAN_HLEN;
2162 #endif
2163
2164 if (unlikely(netif_msg_rx_status(sky2)))
2165 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2166 dev->name, sky2->rx_next, status, length);
2167
2168 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2169 prefetch(sky2->rx_ring + sky2->rx_next);
2170
2171 /* This chip has hardware problems that generates bogus status.
2172 * So do only marginal checking and expect higher level protocols
2173 * to handle crap frames.
2174 */
2175 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2176 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2177 length != count)
2178 goto okay;
2179
2180 if (status & GMR_FS_ANY_ERR)
2181 goto error;
2182
2183 if (!(status & GMR_FS_RX_OK))
2184 goto resubmit;
2185
2186 /* if length reported by DMA does not match PHY, packet was truncated */
2187 if (length != count)
2188 goto len_error;
2189
2190 okay:
2191 if (length < copybreak)
2192 skb = receive_copy(sky2, re, length);
2193 else
2194 skb = receive_new(sky2, re, length);
2195 resubmit:
2196 sky2_rx_submit(sky2, re);
2197
2198 return skb;
2199
2200 len_error:
2201 /* Truncation of overlength packets
2202 causes PHY length to not match MAC length */
2203 ++dev->stats.rx_length_errors;
2204 if (netif_msg_rx_err(sky2) && net_ratelimit())
2205 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2206 dev->name, status, length);
2207 goto resubmit;
2208
2209 error:
2210 ++dev->stats.rx_errors;
2211 if (status & GMR_FS_RX_FF_OV) {
2212 dev->stats.rx_over_errors++;
2213 goto resubmit;
2214 }
2215
2216 if (netif_msg_rx_err(sky2) && net_ratelimit())
2217 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2218 dev->name, status, length);
2219
2220 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2221 dev->stats.rx_length_errors++;
2222 if (status & GMR_FS_FRAGMENT)
2223 dev->stats.rx_frame_errors++;
2224 if (status & GMR_FS_CRC_ERR)
2225 dev->stats.rx_crc_errors++;
2226
2227 goto resubmit;
2228 }
2229
2230 /* Transmit complete */
2231 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2232 {
2233 struct sky2_port *sky2 = netdev_priv(dev);
2234
2235 if (netif_running(dev)) {
2236 netif_tx_lock(dev);
2237 sky2_tx_complete(sky2, last);
2238 netif_tx_unlock(dev);
2239 }
2240 }
2241
2242 /* Process status response ring */
2243 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2244 {
2245 int work_done = 0;
2246 unsigned rx[2] = { 0, 0 };
2247
2248 rmb();
2249 do {
2250 struct sky2_port *sky2;
2251 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2252 unsigned port;
2253 struct net_device *dev;
2254 struct sk_buff *skb;
2255 u32 status;
2256 u16 length;
2257 u8 opcode = le->opcode;
2258
2259 if (!(opcode & HW_OWNER))
2260 break;
2261
2262 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2263
2264 port = le->css & CSS_LINK_BIT;
2265 dev = hw->dev[port];
2266 sky2 = netdev_priv(dev);
2267 length = le16_to_cpu(le->length);
2268 status = le32_to_cpu(le->status);
2269
2270 le->opcode = 0;
2271 switch (opcode & ~HW_OWNER) {
2272 case OP_RXSTAT:
2273 ++rx[port];
2274 skb = sky2_receive(dev, length, status);
2275 if (unlikely(!skb)) {
2276 dev->stats.rx_dropped++;
2277 break;
2278 }
2279
2280 /* This chip reports checksum status differently */
2281 if (hw->flags & SKY2_HW_NEW_LE) {
2282 if (sky2->rx_csum &&
2283 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2284 (le->css & CSS_TCPUDPCSOK))
2285 skb->ip_summed = CHECKSUM_UNNECESSARY;
2286 else
2287 skb->ip_summed = CHECKSUM_NONE;
2288 }
2289
2290 skb->protocol = eth_type_trans(skb, dev);
2291 dev->stats.rx_packets++;
2292 dev->stats.rx_bytes += skb->len;
2293 dev->last_rx = jiffies;
2294
2295 #ifdef SKY2_VLAN_TAG_USED
2296 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2297 vlan_hwaccel_receive_skb(skb,
2298 sky2->vlgrp,
2299 be16_to_cpu(sky2->rx_tag));
2300 } else
2301 #endif
2302 netif_receive_skb(skb);
2303
2304 /* Stop after net poll weight */
2305 if (++work_done >= to_do)
2306 goto exit_loop;
2307 break;
2308
2309 #ifdef SKY2_VLAN_TAG_USED
2310 case OP_RXVLAN:
2311 sky2->rx_tag = length;
2312 break;
2313
2314 case OP_RXCHKSVLAN:
2315 sky2->rx_tag = length;
2316 /* fall through */
2317 #endif
2318 case OP_RXCHKS:
2319 if (!sky2->rx_csum)
2320 break;
2321
2322 /* If this happens then driver assuming wrong format */
2323 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2324 if (net_ratelimit())
2325 printk(KERN_NOTICE "%s: unexpected"
2326 " checksum status\n",
2327 dev->name);
2328 break;
2329 }
2330
2331 /* Both checksum counters are programmed to start at
2332 * the same offset, so unless there is a problem they
2333 * should match. This failure is an early indication that
2334 * hardware receive checksumming won't work.
2335 */
2336 if (likely(status >> 16 == (status & 0xffff))) {
2337 skb = sky2->rx_ring[sky2->rx_next].skb;
2338 skb->ip_summed = CHECKSUM_COMPLETE;
2339 skb->csum = status & 0xffff;
2340 } else {
2341 printk(KERN_NOTICE PFX "%s: hardware receive "
2342 "checksum problem (status = %#x)\n",
2343 dev->name, status);
2344 sky2->rx_csum = 0;
2345 sky2_write32(sky2->hw,
2346 Q_ADDR(rxqaddr[port], Q_CSR),
2347 BMU_DIS_RX_CHKSUM);
2348 }
2349 break;
2350
2351 case OP_TXINDEXLE:
2352 /* TX index reports status for both ports */
2353 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2354 sky2_tx_done(hw->dev[0], status & 0xfff);
2355 if (hw->dev[1])
2356 sky2_tx_done(hw->dev[1],
2357 ((status >> 24) & 0xff)
2358 | (u16)(length & 0xf) << 8);
2359 break;
2360
2361 default:
2362 if (net_ratelimit())
2363 printk(KERN_WARNING PFX
2364 "unknown status opcode 0x%x\n", opcode);
2365 }
2366 } while (hw->st_idx != idx);
2367
2368 /* Fully processed status ring so clear irq */
2369 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2370
2371 exit_loop:
2372 if (rx[0])
2373 sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
2374
2375 if (rx[1])
2376 sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
2377
2378 return work_done;
2379 }
2380
2381 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2382 {
2383 struct net_device *dev = hw->dev[port];
2384
2385 if (net_ratelimit())
2386 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2387 dev->name, status);
2388
2389 if (status & Y2_IS_PAR_RD1) {
2390 if (net_ratelimit())
2391 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2392 dev->name);
2393 /* Clear IRQ */
2394 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2395 }
2396
2397 if (status & Y2_IS_PAR_WR1) {
2398 if (net_ratelimit())
2399 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2400 dev->name);
2401
2402 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2403 }
2404
2405 if (status & Y2_IS_PAR_MAC1) {
2406 if (net_ratelimit())
2407 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2408 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2409 }
2410
2411 if (status & Y2_IS_PAR_RX1) {
2412 if (net_ratelimit())
2413 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2414 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2415 }
2416
2417 if (status & Y2_IS_TCP_TXA1) {
2418 if (net_ratelimit())
2419 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2420 dev->name);
2421 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2422 }
2423 }
2424
2425 static void sky2_hw_intr(struct sky2_hw *hw)
2426 {
2427 struct pci_dev *pdev = hw->pdev;
2428 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2429 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2430
2431 status &= hwmsk;
2432
2433 if (status & Y2_IS_TIST_OV)
2434 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2435
2436 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2437 u16 pci_err;
2438
2439 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2440 if (net_ratelimit())
2441 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2442 pci_err);
2443
2444 sky2_pci_write16(hw, PCI_STATUS,
2445 pci_err | PCI_STATUS_ERROR_BITS);
2446 }
2447
2448 if (status & Y2_IS_PCI_EXP) {
2449 /* PCI-Express uncorrectable Error occurred */
2450 u32 err;
2451
2452 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2453 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2454 0xfffffffful);
2455 if (net_ratelimit())
2456 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2457
2458 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2459 }
2460
2461 if (status & Y2_HWE_L1_MASK)
2462 sky2_hw_error(hw, 0, status);
2463 status >>= 8;
2464 if (status & Y2_HWE_L1_MASK)
2465 sky2_hw_error(hw, 1, status);
2466 }
2467
2468 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2469 {
2470 struct net_device *dev = hw->dev[port];
2471 struct sky2_port *sky2 = netdev_priv(dev);
2472 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2473
2474 if (netif_msg_intr(sky2))
2475 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2476 dev->name, status);
2477
2478 if (status & GM_IS_RX_CO_OV)
2479 gma_read16(hw, port, GM_RX_IRQ_SRC);
2480
2481 if (status & GM_IS_TX_CO_OV)
2482 gma_read16(hw, port, GM_TX_IRQ_SRC);
2483
2484 if (status & GM_IS_RX_FF_OR) {
2485 ++dev->stats.rx_fifo_errors;
2486 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2487 }
2488
2489 if (status & GM_IS_TX_FF_UR) {
2490 ++dev->stats.tx_fifo_errors;
2491 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2492 }
2493 }
2494
2495 /* This should never happen it is a bug. */
2496 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2497 u16 q, unsigned ring_size)
2498 {
2499 struct net_device *dev = hw->dev[port];
2500 struct sky2_port *sky2 = netdev_priv(dev);
2501 unsigned idx;
2502 const u64 *le = (q == Q_R1 || q == Q_R2)
2503 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2504
2505 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2506 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2507 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2508 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2509
2510 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2511 }
2512
2513 static int sky2_rx_hung(struct net_device *dev)
2514 {
2515 struct sky2_port *sky2 = netdev_priv(dev);
2516 struct sky2_hw *hw = sky2->hw;
2517 unsigned port = sky2->port;
2518 unsigned rxq = rxqaddr[port];
2519 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2520 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2521 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2522 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2523
2524 /* If idle and MAC or PCI is stuck */
2525 if (sky2->check.last == dev->last_rx &&
2526 ((mac_rp == sky2->check.mac_rp &&
2527 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2528 /* Check if the PCI RX hang */
2529 (fifo_rp == sky2->check.fifo_rp &&
2530 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2531 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2532 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2533 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2534 return 1;
2535 } else {
2536 sky2->check.last = dev->last_rx;
2537 sky2->check.mac_rp = mac_rp;
2538 sky2->check.mac_lev = mac_lev;
2539 sky2->check.fifo_rp = fifo_rp;
2540 sky2->check.fifo_lev = fifo_lev;
2541 return 0;
2542 }
2543 }
2544
2545 static void sky2_watchdog(unsigned long arg)
2546 {
2547 struct sky2_hw *hw = (struct sky2_hw *) arg;
2548
2549 /* Check for lost IRQ once a second */
2550 if (sky2_read32(hw, B0_ISRC)) {
2551 napi_schedule(&hw->napi);
2552 } else {
2553 int i, active = 0;
2554
2555 for (i = 0; i < hw->ports; i++) {
2556 struct net_device *dev = hw->dev[i];
2557 if (!netif_running(dev))
2558 continue;
2559 ++active;
2560
2561 /* For chips with Rx FIFO, check if stuck */
2562 if ((hw->flags & SKY2_HW_FIFO_HANG_CHECK) &&
2563 sky2_rx_hung(dev)) {
2564 pr_info(PFX "%s: receiver hang detected\n",
2565 dev->name);
2566 schedule_work(&hw->restart_work);
2567 return;
2568 }
2569 }
2570
2571 if (active == 0)
2572 return;
2573 }
2574
2575 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2576 }
2577
2578 /* Hardware/software error handling */
2579 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2580 {
2581 if (net_ratelimit())
2582 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2583
2584 if (status & Y2_IS_HW_ERR)
2585 sky2_hw_intr(hw);
2586
2587 if (status & Y2_IS_IRQ_MAC1)
2588 sky2_mac_intr(hw, 0);
2589
2590 if (status & Y2_IS_IRQ_MAC2)
2591 sky2_mac_intr(hw, 1);
2592
2593 if (status & Y2_IS_CHK_RX1)
2594 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2595
2596 if (status & Y2_IS_CHK_RX2)
2597 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2598
2599 if (status & Y2_IS_CHK_TXA1)
2600 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2601
2602 if (status & Y2_IS_CHK_TXA2)
2603 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2604 }
2605
2606 static int sky2_poll(struct napi_struct *napi, int work_limit)
2607 {
2608 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2609 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2610 int work_done = 0;
2611 u16 idx;
2612
2613 if (unlikely(status & Y2_IS_ERROR))
2614 sky2_err_intr(hw, status);
2615
2616 if (status & Y2_IS_IRQ_PHY1)
2617 sky2_phy_intr(hw, 0);
2618
2619 if (status & Y2_IS_IRQ_PHY2)
2620 sky2_phy_intr(hw, 1);
2621
2622 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2623 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2624
2625 if (work_done >= work_limit)
2626 goto done;
2627 }
2628
2629 /* Bug/Errata workaround?
2630 * Need to kick the TX irq moderation timer.
2631 */
2632 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
2633 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2634 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2635 }
2636 napi_complete(napi);
2637 sky2_read32(hw, B0_Y2_SP_LISR);
2638 done:
2639
2640 return work_done;
2641 }
2642
2643 static irqreturn_t sky2_intr(int irq, void *dev_id)
2644 {
2645 struct sky2_hw *hw = dev_id;
2646 u32 status;
2647
2648 /* Reading this mask interrupts as side effect */
2649 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2650 if (status == 0 || status == ~0)
2651 return IRQ_NONE;
2652
2653 prefetch(&hw->st_le[hw->st_idx]);
2654
2655 napi_schedule(&hw->napi);
2656
2657 return IRQ_HANDLED;
2658 }
2659
2660 #ifdef CONFIG_NET_POLL_CONTROLLER
2661 static void sky2_netpoll(struct net_device *dev)
2662 {
2663 struct sky2_port *sky2 = netdev_priv(dev);
2664
2665 napi_schedule(&sky2->hw->napi);
2666 }
2667 #endif
2668
2669 /* Chip internal frequency for clock calculations */
2670 static u32 sky2_mhz(const struct sky2_hw *hw)
2671 {
2672 switch (hw->chip_id) {
2673 case CHIP_ID_YUKON_EC:
2674 case CHIP_ID_YUKON_EC_U:
2675 case CHIP_ID_YUKON_EX:
2676 case CHIP_ID_YUKON_SUPR:
2677 return 125;
2678
2679 case CHIP_ID_YUKON_FE:
2680 return 100;
2681
2682 case CHIP_ID_YUKON_FE_P:
2683 return 50;
2684
2685 case CHIP_ID_YUKON_XL:
2686 return 156;
2687
2688 default:
2689 BUG();
2690 }
2691 }
2692
2693 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2694 {
2695 return sky2_mhz(hw) * us;
2696 }
2697
2698 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2699 {
2700 return clk / sky2_mhz(hw);
2701 }
2702
2703
2704 static int __devinit sky2_init(struct sky2_hw *hw)
2705 {
2706 u8 t8;
2707
2708 /* Enable all clocks and check for bad PCI access */
2709 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2710
2711 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2712
2713 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2714 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2715
2716 switch(hw->chip_id) {
2717 case CHIP_ID_YUKON_XL:
2718 hw->flags = SKY2_HW_GIGABIT
2719 | SKY2_HW_NEWER_PHY;
2720 if (hw->chip_rev < 3)
2721 hw->flags |= SKY2_HW_FIFO_HANG_CHECK;
2722
2723 break;
2724
2725 case CHIP_ID_YUKON_EC_U:
2726 hw->flags = SKY2_HW_GIGABIT
2727 | SKY2_HW_NEWER_PHY
2728 | SKY2_HW_ADV_POWER_CTL;
2729 break;
2730
2731 case CHIP_ID_YUKON_EX:
2732 hw->flags = SKY2_HW_GIGABIT
2733 | SKY2_HW_NEWER_PHY
2734 | SKY2_HW_NEW_LE
2735 | SKY2_HW_ADV_POWER_CTL;
2736
2737 /* New transmit checksum */
2738 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2739 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2740 break;
2741
2742 case CHIP_ID_YUKON_EC:
2743 /* This rev is really old, and requires untested workarounds */
2744 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2745 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2746 return -EOPNOTSUPP;
2747 }
2748 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_FIFO_HANG_CHECK;
2749 break;
2750
2751 case CHIP_ID_YUKON_FE:
2752 break;
2753
2754 case CHIP_ID_YUKON_FE_P:
2755 hw->flags = SKY2_HW_NEWER_PHY
2756 | SKY2_HW_NEW_LE
2757 | SKY2_HW_AUTO_TX_SUM
2758 | SKY2_HW_ADV_POWER_CTL;
2759 break;
2760
2761 case CHIP_ID_YUKON_SUPR:
2762 hw->flags = SKY2_HW_GIGABIT
2763 | SKY2_HW_NEWER_PHY
2764 | SKY2_HW_NEW_LE
2765 | SKY2_HW_AUTO_TX_SUM
2766 | SKY2_HW_ADV_POWER_CTL;
2767 break;
2768
2769 default:
2770 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2771 hw->chip_id);
2772 return -EOPNOTSUPP;
2773 }
2774
2775 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2776 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2777 hw->flags |= SKY2_HW_FIBRE_PHY;
2778
2779
2780 hw->ports = 1;
2781 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2782 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2783 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2784 ++hw->ports;
2785 }
2786
2787 return 0;
2788 }
2789
2790 static void sky2_reset(struct sky2_hw *hw)
2791 {
2792 struct pci_dev *pdev = hw->pdev;
2793 u16 status;
2794 int i, cap;
2795 u32 hwe_mask = Y2_HWE_ALL_MASK;
2796
2797 /* disable ASF */
2798 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2799 status = sky2_read16(hw, HCU_CCSR);
2800 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2801 HCU_CCSR_UC_STATE_MSK);
2802 sky2_write16(hw, HCU_CCSR, status);
2803 } else
2804 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2805 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2806
2807 /* do a SW reset */
2808 sky2_write8(hw, B0_CTST, CS_RST_SET);
2809 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2810
2811 /* allow writes to PCI config */
2812 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2813
2814 /* clear PCI errors, if any */
2815 status = sky2_pci_read16(hw, PCI_STATUS);
2816 status |= PCI_STATUS_ERROR_BITS;
2817 sky2_pci_write16(hw, PCI_STATUS, status);
2818
2819 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2820
2821 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2822 if (cap) {
2823 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2824 0xfffffffful);
2825
2826 /* If error bit is stuck on ignore it */
2827 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
2828 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
2829 else
2830 hwe_mask |= Y2_IS_PCI_EXP;
2831 }
2832
2833 sky2_power_on(hw);
2834
2835 for (i = 0; i < hw->ports; i++) {
2836 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2837 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2838
2839 if (hw->chip_id == CHIP_ID_YUKON_EX ||
2840 hw->chip_id == CHIP_ID_YUKON_SUPR)
2841 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
2842 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
2843 | GMC_BYP_RETR_ON);
2844 }
2845
2846 /* Clear I2C IRQ noise */
2847 sky2_write32(hw, B2_I2C_IRQ, 1);
2848
2849 /* turn off hardware timer (unused) */
2850 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2851 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2852
2853 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2854
2855 /* Turn off descriptor polling */
2856 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2857
2858 /* Turn off receive timestamp */
2859 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2860 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2861
2862 /* enable the Tx Arbiters */
2863 for (i = 0; i < hw->ports; i++)
2864 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2865
2866 /* Initialize ram interface */
2867 for (i = 0; i < hw->ports; i++) {
2868 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2869
2870 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2871 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2872 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2873 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2874 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2875 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2876 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2877 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2878 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2879 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2880 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2881 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2882 }
2883
2884 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
2885
2886 for (i = 0; i < hw->ports; i++)
2887 sky2_gmac_reset(hw, i);
2888
2889 memset(hw->st_le, 0, STATUS_LE_BYTES);
2890 hw->st_idx = 0;
2891
2892 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2893 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2894
2895 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2896 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2897
2898 /* Set the list last index */
2899 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2900
2901 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2902 sky2_write8(hw, STAT_FIFO_WM, 16);
2903
2904 /* set Status-FIFO ISR watermark */
2905 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2906 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2907 else
2908 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2909
2910 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2911 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2912 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2913
2914 /* enable status unit */
2915 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2916
2917 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2918 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2919 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2920 }
2921
2922 static void sky2_restart(struct work_struct *work)
2923 {
2924 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2925 struct net_device *dev;
2926 int i, err;
2927
2928 rtnl_lock();
2929 for (i = 0; i < hw->ports; i++) {
2930 dev = hw->dev[i];
2931 if (netif_running(dev))
2932 sky2_down(dev);
2933 }
2934
2935 napi_disable(&hw->napi);
2936 sky2_write32(hw, B0_IMSK, 0);
2937 sky2_reset(hw);
2938 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2939 napi_enable(&hw->napi);
2940
2941 for (i = 0; i < hw->ports; i++) {
2942 dev = hw->dev[i];
2943 if (netif_running(dev)) {
2944 err = sky2_up(dev);
2945 if (err) {
2946 printk(KERN_INFO PFX "%s: could not restart %d\n",
2947 dev->name, err);
2948 dev_close(dev);
2949 }
2950 }
2951 }
2952
2953 rtnl_unlock();
2954 }
2955
2956 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2957 {
2958 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2959 }
2960
2961 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2962 {
2963 const struct sky2_port *sky2 = netdev_priv(dev);
2964
2965 wol->supported = sky2_wol_supported(sky2->hw);
2966 wol->wolopts = sky2->wol;
2967 }
2968
2969 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2970 {
2971 struct sky2_port *sky2 = netdev_priv(dev);
2972 struct sky2_hw *hw = sky2->hw;
2973
2974 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2975 return -EOPNOTSUPP;
2976
2977 sky2->wol = wol->wolopts;
2978
2979 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
2980 hw->chip_id == CHIP_ID_YUKON_EX ||
2981 hw->chip_id == CHIP_ID_YUKON_FE_P)
2982 sky2_write32(hw, B0_CTST, sky2->wol
2983 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2984
2985 if (!netif_running(dev))
2986 sky2_wol_init(sky2);
2987 return 0;
2988 }
2989
2990 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2991 {
2992 if (sky2_is_copper(hw)) {
2993 u32 modes = SUPPORTED_10baseT_Half
2994 | SUPPORTED_10baseT_Full
2995 | SUPPORTED_100baseT_Half
2996 | SUPPORTED_100baseT_Full
2997 | SUPPORTED_Autoneg | SUPPORTED_TP;
2998
2999 if (hw->flags & SKY2_HW_GIGABIT)
3000 modes |= SUPPORTED_1000baseT_Half
3001 | SUPPORTED_1000baseT_Full;
3002 return modes;
3003 } else
3004 return SUPPORTED_1000baseT_Half
3005 | SUPPORTED_1000baseT_Full
3006 | SUPPORTED_Autoneg
3007 | SUPPORTED_FIBRE;
3008 }
3009
3010 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3011 {
3012 struct sky2_port *sky2 = netdev_priv(dev);
3013 struct sky2_hw *hw = sky2->hw;
3014
3015 ecmd->transceiver = XCVR_INTERNAL;
3016 ecmd->supported = sky2_supported_modes(hw);
3017 ecmd->phy_address = PHY_ADDR_MARV;
3018 if (sky2_is_copper(hw)) {
3019 ecmd->port = PORT_TP;
3020 ecmd->speed = sky2->speed;
3021 } else {
3022 ecmd->speed = SPEED_1000;
3023 ecmd->port = PORT_FIBRE;
3024 }
3025
3026 ecmd->advertising = sky2->advertising;
3027 ecmd->autoneg = sky2->autoneg;
3028 ecmd->duplex = sky2->duplex;
3029 return 0;
3030 }
3031
3032 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3033 {
3034 struct sky2_port *sky2 = netdev_priv(dev);
3035 const struct sky2_hw *hw = sky2->hw;
3036 u32 supported = sky2_supported_modes(hw);
3037
3038 if (ecmd->autoneg == AUTONEG_ENABLE) {
3039 ecmd->advertising = supported;
3040 sky2->duplex = -1;
3041 sky2->speed = -1;
3042 } else {
3043 u32 setting;
3044
3045 switch (ecmd->speed) {
3046 case SPEED_1000:
3047 if (ecmd->duplex == DUPLEX_FULL)
3048 setting = SUPPORTED_1000baseT_Full;
3049 else if (ecmd->duplex == DUPLEX_HALF)
3050 setting = SUPPORTED_1000baseT_Half;
3051 else
3052 return -EINVAL;
3053 break;
3054 case SPEED_100:
3055 if (ecmd->duplex == DUPLEX_FULL)
3056 setting = SUPPORTED_100baseT_Full;
3057 else if (ecmd->duplex == DUPLEX_HALF)
3058 setting = SUPPORTED_100baseT_Half;
3059 else
3060 return -EINVAL;
3061 break;
3062
3063 case SPEED_10:
3064 if (ecmd->duplex == DUPLEX_FULL)
3065 setting = SUPPORTED_10baseT_Full;
3066 else if (ecmd->duplex == DUPLEX_HALF)
3067 setting = SUPPORTED_10baseT_Half;
3068 else
3069 return -EINVAL;
3070 break;
3071 default:
3072 return -EINVAL;
3073 }
3074
3075 if ((setting & supported) == 0)
3076 return -EINVAL;
3077
3078 sky2->speed = ecmd->speed;
3079 sky2->duplex = ecmd->duplex;
3080 }
3081
3082 sky2->autoneg = ecmd->autoneg;
3083 sky2->advertising = ecmd->advertising;
3084
3085 if (netif_running(dev)) {
3086 sky2_phy_reinit(sky2);
3087 sky2_set_multicast(dev);
3088 }
3089
3090 return 0;
3091 }
3092
3093 static void sky2_get_drvinfo(struct net_device *dev,
3094 struct ethtool_drvinfo *info)
3095 {
3096 struct sky2_port *sky2 = netdev_priv(dev);
3097
3098 strcpy(info->driver, DRV_NAME);
3099 strcpy(info->version, DRV_VERSION);
3100 strcpy(info->fw_version, "N/A");
3101 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3102 }
3103
3104 static const struct sky2_stat {
3105 char name[ETH_GSTRING_LEN];
3106 u16 offset;
3107 } sky2_stats[] = {
3108 { "tx_bytes", GM_TXO_OK_HI },
3109 { "rx_bytes", GM_RXO_OK_HI },
3110 { "tx_broadcast", GM_TXF_BC_OK },
3111 { "rx_broadcast", GM_RXF_BC_OK },
3112 { "tx_multicast", GM_TXF_MC_OK },
3113 { "rx_multicast", GM_RXF_MC_OK },
3114 { "tx_unicast", GM_TXF_UC_OK },
3115 { "rx_unicast", GM_RXF_UC_OK },
3116 { "tx_mac_pause", GM_TXF_MPAUSE },
3117 { "rx_mac_pause", GM_RXF_MPAUSE },
3118 { "collisions", GM_TXF_COL },
3119 { "late_collision",GM_TXF_LAT_COL },
3120 { "aborted", GM_TXF_ABO_COL },
3121 { "single_collisions", GM_TXF_SNG_COL },
3122 { "multi_collisions", GM_TXF_MUL_COL },
3123
3124 { "rx_short", GM_RXF_SHT },
3125 { "rx_runt", GM_RXE_FRAG },
3126 { "rx_64_byte_packets", GM_RXF_64B },
3127 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3128 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3129 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3130 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3131 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3132 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3133 { "rx_too_long", GM_RXF_LNG_ERR },
3134 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3135 { "rx_jabber", GM_RXF_JAB_PKT },
3136 { "rx_fcs_error", GM_RXF_FCS_ERR },
3137
3138 { "tx_64_byte_packets", GM_TXF_64B },
3139 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3140 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3141 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3142 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3143 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3144 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3145 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3146 };
3147
3148 static u32 sky2_get_rx_csum(struct net_device *dev)
3149 {
3150 struct sky2_port *sky2 = netdev_priv(dev);
3151
3152 return sky2->rx_csum;
3153 }
3154
3155 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3156 {
3157 struct sky2_port *sky2 = netdev_priv(dev);
3158
3159 sky2->rx_csum = data;
3160
3161 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3162 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3163
3164 return 0;
3165 }
3166
3167 static u32 sky2_get_msglevel(struct net_device *netdev)
3168 {
3169 struct sky2_port *sky2 = netdev_priv(netdev);
3170 return sky2->msg_enable;
3171 }
3172
3173 static int sky2_nway_reset(struct net_device *dev)
3174 {
3175 struct sky2_port *sky2 = netdev_priv(dev);
3176
3177 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
3178 return -EINVAL;
3179
3180 sky2_phy_reinit(sky2);
3181 sky2_set_multicast(dev);
3182
3183 return 0;
3184 }
3185
3186 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3187 {
3188 struct sky2_hw *hw = sky2->hw;
3189 unsigned port = sky2->port;
3190 int i;
3191
3192 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3193 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3194 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3195 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3196
3197 for (i = 2; i < count; i++)
3198 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3199 }
3200
3201 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3202 {
3203 struct sky2_port *sky2 = netdev_priv(netdev);
3204 sky2->msg_enable = value;
3205 }
3206
3207 static int sky2_get_sset_count(struct net_device *dev, int sset)
3208 {
3209 switch (sset) {
3210 case ETH_SS_STATS:
3211 return ARRAY_SIZE(sky2_stats);
3212 default:
3213 return -EOPNOTSUPP;
3214 }
3215 }
3216
3217 static void sky2_get_ethtool_stats(struct net_device *dev,
3218 struct ethtool_stats *stats, u64 * data)
3219 {
3220 struct sky2_port *sky2 = netdev_priv(dev);
3221
3222 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3223 }
3224
3225 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3226 {
3227 int i;
3228
3229 switch (stringset) {
3230 case ETH_SS_STATS:
3231 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3232 memcpy(data + i * ETH_GSTRING_LEN,
3233 sky2_stats[i].name, ETH_GSTRING_LEN);
3234 break;
3235 }
3236 }
3237
3238 static int sky2_set_mac_address(struct net_device *dev, void *p)
3239 {
3240 struct sky2_port *sky2 = netdev_priv(dev);
3241 struct sky2_hw *hw = sky2->hw;
3242 unsigned port = sky2->port;
3243 const struct sockaddr *addr = p;
3244
3245 if (!is_valid_ether_addr(addr->sa_data))
3246 return -EADDRNOTAVAIL;
3247
3248 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3249 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3250 dev->dev_addr, ETH_ALEN);
3251 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3252 dev->dev_addr, ETH_ALEN);
3253
3254 /* virtual address for data */
3255 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3256
3257 /* physical address: used for pause frames */
3258 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3259
3260 return 0;
3261 }
3262
3263 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3264 {
3265 u32 bit;
3266
3267 bit = ether_crc(ETH_ALEN, addr) & 63;
3268 filter[bit >> 3] |= 1 << (bit & 7);
3269 }
3270
3271 static void sky2_set_multicast(struct net_device *dev)
3272 {
3273 struct sky2_port *sky2 = netdev_priv(dev);
3274 struct sky2_hw *hw = sky2->hw;
3275 unsigned port = sky2->port;
3276 struct dev_mc_list *list = dev->mc_list;
3277 u16 reg;
3278 u8 filter[8];
3279 int rx_pause;
3280 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3281
3282 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3283 memset(filter, 0, sizeof(filter));
3284
3285 reg = gma_read16(hw, port, GM_RX_CTRL);
3286 reg |= GM_RXCR_UCF_ENA;
3287
3288 if (dev->flags & IFF_PROMISC) /* promiscuous */
3289 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3290 else if (dev->flags & IFF_ALLMULTI)
3291 memset(filter, 0xff, sizeof(filter));
3292 else if (dev->mc_count == 0 && !rx_pause)
3293 reg &= ~GM_RXCR_MCF_ENA;
3294 else {
3295 int i;
3296 reg |= GM_RXCR_MCF_ENA;
3297
3298 if (rx_pause)
3299 sky2_add_filter(filter, pause_mc_addr);
3300
3301 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3302 sky2_add_filter(filter, list->dmi_addr);
3303 }
3304
3305 gma_write16(hw, port, GM_MC_ADDR_H1,
3306 (u16) filter[0] | ((u16) filter[1] << 8));
3307 gma_write16(hw, port, GM_MC_ADDR_H2,
3308 (u16) filter[2] | ((u16) filter[3] << 8));
3309 gma_write16(hw, port, GM_MC_ADDR_H3,
3310 (u16) filter[4] | ((u16) filter[5] << 8));
3311 gma_write16(hw, port, GM_MC_ADDR_H4,
3312 (u16) filter[6] | ((u16) filter[7] << 8));
3313
3314 gma_write16(hw, port, GM_RX_CTRL, reg);
3315 }
3316
3317 /* Can have one global because blinking is controlled by
3318 * ethtool and that is always under RTNL mutex
3319 */
3320 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3321 {
3322 u16 pg;
3323
3324 switch (hw->chip_id) {
3325 case CHIP_ID_YUKON_XL:
3326 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3327 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3328 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3329 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3330 PHY_M_LEDC_INIT_CTRL(7) |
3331 PHY_M_LEDC_STA1_CTRL(7) |
3332 PHY_M_LEDC_STA0_CTRL(7))
3333 : 0);
3334
3335 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3336 break;
3337
3338 default:
3339 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3340 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3341 on ? PHY_M_LED_ALL : 0);
3342 }
3343 }
3344
3345 /* blink LED's for finding board */
3346 static int sky2_phys_id(struct net_device *dev, u32 data)
3347 {
3348 struct sky2_port *sky2 = netdev_priv(dev);
3349 struct sky2_hw *hw = sky2->hw;
3350 unsigned port = sky2->port;
3351 u16 ledctrl, ledover = 0;
3352 long ms;
3353 int interrupted;
3354 int onoff = 1;
3355
3356 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3357 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3358 else
3359 ms = data * 1000;
3360
3361 /* save initial values */
3362 spin_lock_bh(&sky2->phy_lock);
3363 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3364 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3365 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3366 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3367 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3368 } else {
3369 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3370 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3371 }
3372
3373 interrupted = 0;
3374 while (!interrupted && ms > 0) {
3375 sky2_led(hw, port, onoff);
3376 onoff = !onoff;
3377
3378 spin_unlock_bh(&sky2->phy_lock);
3379 interrupted = msleep_interruptible(250);
3380 spin_lock_bh(&sky2->phy_lock);
3381
3382 ms -= 250;
3383 }
3384
3385 /* resume regularly scheduled programming */
3386 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3387 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3388 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3389 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3390 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3391 } else {
3392 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3393 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3394 }
3395 spin_unlock_bh(&sky2->phy_lock);
3396
3397 return 0;
3398 }
3399
3400 static void sky2_get_pauseparam(struct net_device *dev,
3401 struct ethtool_pauseparam *ecmd)
3402 {
3403 struct sky2_port *sky2 = netdev_priv(dev);
3404
3405 switch (sky2->flow_mode) {
3406 case FC_NONE:
3407 ecmd->tx_pause = ecmd->rx_pause = 0;
3408 break;
3409 case FC_TX:
3410 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3411 break;
3412 case FC_RX:
3413 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3414 break;
3415 case FC_BOTH:
3416 ecmd->tx_pause = ecmd->rx_pause = 1;
3417 }
3418
3419 ecmd->autoneg = sky2->autoneg;
3420 }
3421
3422 static int sky2_set_pauseparam(struct net_device *dev,
3423 struct ethtool_pauseparam *ecmd)
3424 {
3425 struct sky2_port *sky2 = netdev_priv(dev);
3426
3427 sky2->autoneg = ecmd->autoneg;
3428 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3429
3430 if (netif_running(dev))
3431 sky2_phy_reinit(sky2);
3432
3433 return 0;
3434 }
3435
3436 static int sky2_get_coalesce(struct net_device *dev,
3437 struct ethtool_coalesce *ecmd)
3438 {
3439 struct sky2_port *sky2 = netdev_priv(dev);
3440 struct sky2_hw *hw = sky2->hw;
3441
3442 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3443 ecmd->tx_coalesce_usecs = 0;
3444 else {
3445 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3446 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3447 }
3448 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3449
3450 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3451 ecmd->rx_coalesce_usecs = 0;
3452 else {
3453 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3454 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3455 }
3456 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3457
3458 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3459 ecmd->rx_coalesce_usecs_irq = 0;
3460 else {
3461 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3462 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3463 }
3464
3465 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3466
3467 return 0;
3468 }
3469
3470 /* Note: this affect both ports */
3471 static int sky2_set_coalesce(struct net_device *dev,
3472 struct ethtool_coalesce *ecmd)
3473 {
3474 struct sky2_port *sky2 = netdev_priv(dev);
3475 struct sky2_hw *hw = sky2->hw;
3476 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3477
3478 if (ecmd->tx_coalesce_usecs > tmax ||
3479 ecmd->rx_coalesce_usecs > tmax ||
3480 ecmd->rx_coalesce_usecs_irq > tmax)
3481 return -EINVAL;
3482
3483 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3484 return -EINVAL;
3485 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3486 return -EINVAL;
3487 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3488 return -EINVAL;
3489
3490 if (ecmd->tx_coalesce_usecs == 0)
3491 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3492 else {
3493 sky2_write32(hw, STAT_TX_TIMER_INI,
3494 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3495 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3496 }
3497 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3498
3499 if (ecmd->rx_coalesce_usecs == 0)
3500 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3501 else {
3502 sky2_write32(hw, STAT_LEV_TIMER_INI,
3503 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3504 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3505 }
3506 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3507
3508 if (ecmd->rx_coalesce_usecs_irq == 0)
3509 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3510 else {
3511 sky2_write32(hw, STAT_ISR_TIMER_INI,
3512 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3513 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3514 }
3515 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3516 return 0;
3517 }
3518
3519 static void sky2_get_ringparam(struct net_device *dev,
3520 struct ethtool_ringparam *ering)
3521 {
3522 struct sky2_port *sky2 = netdev_priv(dev);
3523
3524 ering->rx_max_pending = RX_MAX_PENDING;
3525 ering->rx_mini_max_pending = 0;
3526 ering->rx_jumbo_max_pending = 0;
3527 ering->tx_max_pending = TX_RING_SIZE - 1;
3528
3529 ering->rx_pending = sky2->rx_pending;
3530 ering->rx_mini_pending = 0;
3531 ering->rx_jumbo_pending = 0;
3532 ering->tx_pending = sky2->tx_pending;
3533 }
3534
3535 static int sky2_set_ringparam(struct net_device *dev,
3536 struct ethtool_ringparam *ering)
3537 {
3538 struct sky2_port *sky2 = netdev_priv(dev);
3539 int err = 0;
3540
3541 if (ering->rx_pending > RX_MAX_PENDING ||
3542 ering->rx_pending < 8 ||
3543 ering->tx_pending < MAX_SKB_TX_LE ||
3544 ering->tx_pending > TX_RING_SIZE - 1)
3545 return -EINVAL;
3546
3547 if (netif_running(dev))
3548 sky2_down(dev);
3549
3550 sky2->rx_pending = ering->rx_pending;
3551 sky2->tx_pending = ering->tx_pending;
3552
3553 if (netif_running(dev)) {
3554 err = sky2_up(dev);
3555 if (err)
3556 dev_close(dev);
3557 else
3558 sky2_set_multicast(dev);
3559 }
3560
3561 return err;
3562 }
3563
3564 static int sky2_get_regs_len(struct net_device *dev)
3565 {
3566 return 0x4000;
3567 }
3568
3569 /*
3570 * Returns copy of control register region
3571 * Note: ethtool_get_regs always provides full size (16k) buffer
3572 */
3573 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3574 void *p)
3575 {
3576 const struct sky2_port *sky2 = netdev_priv(dev);
3577 const void __iomem *io = sky2->hw->regs;
3578 unsigned int b;
3579
3580 regs->version = 1;
3581
3582 for (b = 0; b < 128; b++) {
3583 /* This complicated switch statement is to make sure and
3584 * only access regions that are unreserved.
3585 * Some blocks are only valid on dual port cards.
3586 * and block 3 has some special diagnostic registers that
3587 * are poison.
3588 */
3589 switch (b) {
3590 case 3:
3591 /* skip diagnostic ram region */
3592 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3593 break;
3594
3595 /* dual port cards only */
3596 case 5: /* Tx Arbiter 2 */
3597 case 9: /* RX2 */
3598 case 14 ... 15: /* TX2 */
3599 case 17: case 19: /* Ram Buffer 2 */
3600 case 22 ... 23: /* Tx Ram Buffer 2 */
3601 case 25: /* Rx MAC Fifo 1 */
3602 case 27: /* Tx MAC Fifo 2 */
3603 case 31: /* GPHY 2 */
3604 case 40 ... 47: /* Pattern Ram 2 */
3605 case 52: case 54: /* TCP Segmentation 2 */
3606 case 112 ... 116: /* GMAC 2 */
3607 if (sky2->hw->ports == 1)
3608 goto reserved;
3609 /* fall through */
3610 case 0: /* Control */
3611 case 2: /* Mac address */
3612 case 4: /* Tx Arbiter 1 */
3613 case 7: /* PCI express reg */
3614 case 8: /* RX1 */
3615 case 12 ... 13: /* TX1 */
3616 case 16: case 18:/* Rx Ram Buffer 1 */
3617 case 20 ... 21: /* Tx Ram Buffer 1 */
3618 case 24: /* Rx MAC Fifo 1 */
3619 case 26: /* Tx MAC Fifo 1 */
3620 case 28 ... 29: /* Descriptor and status unit */
3621 case 30: /* GPHY 1*/
3622 case 32 ... 39: /* Pattern Ram 1 */
3623 case 48: case 50: /* TCP Segmentation 1 */
3624 case 56 ... 60: /* PCI space */
3625 case 80 ... 84: /* GMAC 1 */
3626 memcpy_fromio(p, io, 128);
3627 break;
3628 default:
3629 reserved:
3630 memset(p, 0, 128);
3631 }
3632
3633 p += 128;
3634 io += 128;
3635 }
3636 }
3637
3638 /* In order to do Jumbo packets on these chips, need to turn off the
3639 * transmit store/forward. Therefore checksum offload won't work.
3640 */
3641 static int no_tx_offload(struct net_device *dev)
3642 {
3643 const struct sky2_port *sky2 = netdev_priv(dev);
3644 const struct sky2_hw *hw = sky2->hw;
3645
3646 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3647 }
3648
3649 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3650 {
3651 if (data && no_tx_offload(dev))
3652 return -EINVAL;
3653
3654 return ethtool_op_set_tx_csum(dev, data);
3655 }
3656
3657
3658 static int sky2_set_tso(struct net_device *dev, u32 data)
3659 {
3660 if (data && no_tx_offload(dev))
3661 return -EINVAL;
3662
3663 return ethtool_op_set_tso(dev, data);
3664 }
3665
3666 static int sky2_get_eeprom_len(struct net_device *dev)
3667 {
3668 struct sky2_port *sky2 = netdev_priv(dev);
3669 struct sky2_hw *hw = sky2->hw;
3670 u16 reg2;
3671
3672 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3673 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3674 }
3675
3676 static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset)
3677 {
3678 u32 val;
3679
3680 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
3681
3682 do {
3683 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3684 } while (!(offset & PCI_VPD_ADDR_F));
3685
3686 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
3687 return val;
3688 }
3689
3690 static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val)
3691 {
3692 sky2_pci_write16(hw, cap + PCI_VPD_DATA, val);
3693 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
3694 do {
3695 offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR);
3696 } while (offset & PCI_VPD_ADDR_F);
3697 }
3698
3699 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3700 u8 *data)
3701 {
3702 struct sky2_port *sky2 = netdev_priv(dev);
3703 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3704 int length = eeprom->len;
3705 u16 offset = eeprom->offset;
3706
3707 if (!cap)
3708 return -EINVAL;
3709
3710 eeprom->magic = SKY2_EEPROM_MAGIC;
3711
3712 while (length > 0) {
3713 u32 val = sky2_vpd_read(sky2->hw, cap, offset);
3714 int n = min_t(int, length, sizeof(val));
3715
3716 memcpy(data, &val, n);
3717 length -= n;
3718 data += n;
3719 offset += n;
3720 }
3721 return 0;
3722 }
3723
3724 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
3725 u8 *data)
3726 {
3727 struct sky2_port *sky2 = netdev_priv(dev);
3728 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
3729 int length = eeprom->len;
3730 u16 offset = eeprom->offset;
3731
3732 if (!cap)
3733 return -EINVAL;
3734
3735 if (eeprom->magic != SKY2_EEPROM_MAGIC)
3736 return -EINVAL;
3737
3738 while (length > 0) {
3739 u32 val;
3740 int n = min_t(int, length, sizeof(val));
3741
3742 if (n < sizeof(val))
3743 val = sky2_vpd_read(sky2->hw, cap, offset);
3744 memcpy(&val, data, n);
3745
3746 sky2_vpd_write(sky2->hw, cap, offset, val);
3747
3748 length -= n;
3749 data += n;
3750 offset += n;
3751 }
3752 return 0;
3753 }
3754
3755
3756 static const struct ethtool_ops sky2_ethtool_ops = {
3757 .get_settings = sky2_get_settings,
3758 .set_settings = sky2_set_settings,
3759 .get_drvinfo = sky2_get_drvinfo,
3760 .get_wol = sky2_get_wol,
3761 .set_wol = sky2_set_wol,
3762 .get_msglevel = sky2_get_msglevel,
3763 .set_msglevel = sky2_set_msglevel,
3764 .nway_reset = sky2_nway_reset,
3765 .get_regs_len = sky2_get_regs_len,
3766 .get_regs = sky2_get_regs,
3767 .get_link = ethtool_op_get_link,
3768 .get_eeprom_len = sky2_get_eeprom_len,
3769 .get_eeprom = sky2_get_eeprom,
3770 .set_eeprom = sky2_set_eeprom,
3771 .set_sg = ethtool_op_set_sg,
3772 .set_tx_csum = sky2_set_tx_csum,
3773 .set_tso = sky2_set_tso,
3774 .get_rx_csum = sky2_get_rx_csum,
3775 .set_rx_csum = sky2_set_rx_csum,
3776 .get_strings = sky2_get_strings,
3777 .get_coalesce = sky2_get_coalesce,
3778 .set_coalesce = sky2_set_coalesce,
3779 .get_ringparam = sky2_get_ringparam,
3780 .set_ringparam = sky2_set_ringparam,
3781 .get_pauseparam = sky2_get_pauseparam,
3782 .set_pauseparam = sky2_set_pauseparam,
3783 .phys_id = sky2_phys_id,
3784 .get_sset_count = sky2_get_sset_count,
3785 .get_ethtool_stats = sky2_get_ethtool_stats,
3786 };
3787
3788 #ifdef CONFIG_SKY2_DEBUG
3789
3790 static struct dentry *sky2_debug;
3791
3792 static int sky2_debug_show(struct seq_file *seq, void *v)
3793 {
3794 struct net_device *dev = seq->private;
3795 const struct sky2_port *sky2 = netdev_priv(dev);
3796 struct sky2_hw *hw = sky2->hw;
3797 unsigned port = sky2->port;
3798 unsigned idx, last;
3799 int sop;
3800
3801 if (!netif_running(dev))
3802 return -ENETDOWN;
3803
3804 seq_printf(seq, "IRQ src=%x mask=%x control=%x\n",
3805 sky2_read32(hw, B0_ISRC),
3806 sky2_read32(hw, B0_IMSK),
3807 sky2_read32(hw, B0_Y2_SP_ICR));
3808
3809 napi_disable(&hw->napi);
3810 last = sky2_read16(hw, STAT_PUT_IDX);
3811
3812 if (hw->st_idx == last)
3813 seq_puts(seq, "Status ring (empty)\n");
3814 else {
3815 seq_puts(seq, "Status ring\n");
3816 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
3817 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
3818 const struct sky2_status_le *le = hw->st_le + idx;
3819 seq_printf(seq, "[%d] %#x %d %#x\n",
3820 idx, le->opcode, le->length, le->status);
3821 }
3822 seq_puts(seq, "\n");
3823 }
3824
3825 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
3826 sky2->tx_cons, sky2->tx_prod,
3827 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
3828 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
3829
3830 /* Dump contents of tx ring */
3831 sop = 1;
3832 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < TX_RING_SIZE;
3833 idx = RING_NEXT(idx, TX_RING_SIZE)) {
3834 const struct sky2_tx_le *le = sky2->tx_le + idx;
3835 u32 a = le32_to_cpu(le->addr);
3836
3837 if (sop)
3838 seq_printf(seq, "%u:", idx);
3839 sop = 0;
3840
3841 switch(le->opcode & ~HW_OWNER) {
3842 case OP_ADDR64:
3843 seq_printf(seq, " %#x:", a);
3844 break;
3845 case OP_LRGLEN:
3846 seq_printf(seq, " mtu=%d", a);
3847 break;
3848 case OP_VLAN:
3849 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
3850 break;
3851 case OP_TCPLISW:
3852 seq_printf(seq, " csum=%#x", a);
3853 break;
3854 case OP_LARGESEND:
3855 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
3856 break;
3857 case OP_PACKET:
3858 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
3859 break;
3860 case OP_BUFFER:
3861 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
3862 break;
3863 default:
3864 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
3865 a, le16_to_cpu(le->length));
3866 }
3867
3868 if (le->ctrl & EOP) {
3869 seq_putc(seq, '\n');
3870 sop = 1;
3871 }
3872 }
3873
3874 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
3875 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
3876 last = sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3877 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
3878
3879 sky2_read32(hw, B0_Y2_SP_LISR);
3880 napi_enable(&hw->napi);
3881 return 0;
3882 }
3883
3884 static int sky2_debug_open(struct inode *inode, struct file *file)
3885 {
3886 return single_open(file, sky2_debug_show, inode->i_private);
3887 }
3888
3889 static const struct file_operations sky2_debug_fops = {
3890 .owner = THIS_MODULE,
3891 .open = sky2_debug_open,
3892 .read = seq_read,
3893 .llseek = seq_lseek,
3894 .release = single_release,
3895 };
3896
3897 /*
3898 * Use network device events to create/remove/rename
3899 * debugfs file entries
3900 */
3901 static int sky2_device_event(struct notifier_block *unused,
3902 unsigned long event, void *ptr)
3903 {
3904 struct net_device *dev = ptr;
3905 struct sky2_port *sky2 = netdev_priv(dev);
3906
3907 if (dev->open != sky2_up || !sky2_debug)
3908 return NOTIFY_DONE;
3909
3910 switch(event) {
3911 case NETDEV_CHANGENAME:
3912 if (sky2->debugfs) {
3913 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
3914 sky2_debug, dev->name);
3915 }
3916 break;
3917
3918 case NETDEV_GOING_DOWN:
3919 if (sky2->debugfs) {
3920 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
3921 dev->name);
3922 debugfs_remove(sky2->debugfs);
3923 sky2->debugfs = NULL;
3924 }
3925 break;
3926
3927 case NETDEV_UP:
3928 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
3929 sky2_debug, dev,
3930 &sky2_debug_fops);
3931 if (IS_ERR(sky2->debugfs))
3932 sky2->debugfs = NULL;
3933 }
3934
3935 return NOTIFY_DONE;
3936 }
3937
3938 static struct notifier_block sky2_notifier = {
3939 .notifier_call = sky2_device_event,
3940 };
3941
3942
3943 static __init void sky2_debug_init(void)
3944 {
3945 struct dentry *ent;
3946
3947 ent = debugfs_create_dir("sky2", NULL);
3948 if (!ent || IS_ERR(ent))
3949 return;
3950
3951 sky2_debug = ent;
3952 register_netdevice_notifier(&sky2_notifier);
3953 }
3954
3955 static __exit void sky2_debug_cleanup(void)
3956 {
3957 if (sky2_debug) {
3958 unregister_netdevice_notifier(&sky2_notifier);
3959 debugfs_remove(sky2_debug);
3960 sky2_debug = NULL;
3961 }
3962 }
3963
3964 #else
3965 #define sky2_debug_init()
3966 #define sky2_debug_cleanup()
3967 #endif
3968
3969
3970 /* Initialize network device */
3971 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3972 unsigned port,
3973 int highmem, int wol)
3974 {
3975 struct sky2_port *sky2;
3976 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3977
3978 if (!dev) {
3979 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3980 return NULL;
3981 }
3982
3983 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3984 dev->irq = hw->pdev->irq;
3985 dev->open = sky2_up;
3986 dev->stop = sky2_down;
3987 dev->do_ioctl = sky2_ioctl;
3988 dev->hard_start_xmit = sky2_xmit_frame;
3989 dev->set_multicast_list = sky2_set_multicast;
3990 dev->set_mac_address = sky2_set_mac_address;
3991 dev->change_mtu = sky2_change_mtu;
3992 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3993 dev->tx_timeout = sky2_tx_timeout;
3994 dev->watchdog_timeo = TX_WATCHDOG;
3995 #ifdef CONFIG_NET_POLL_CONTROLLER
3996 if (port == 0)
3997 dev->poll_controller = sky2_netpoll;
3998 #endif
3999
4000 sky2 = netdev_priv(dev);
4001 sky2->netdev = dev;
4002 sky2->hw = hw;
4003 sky2->msg_enable = netif_msg_init(debug, default_msg);
4004
4005 /* Auto speed and flow control */
4006 sky2->autoneg = AUTONEG_ENABLE;
4007 sky2->flow_mode = FC_BOTH;
4008
4009 sky2->duplex = -1;
4010 sky2->speed = -1;
4011 sky2->advertising = sky2_supported_modes(hw);
4012 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
4013 sky2->wol = wol;
4014
4015 spin_lock_init(&sky2->phy_lock);
4016 sky2->tx_pending = TX_DEF_PENDING;
4017 sky2->rx_pending = RX_DEF_PENDING;
4018
4019 hw->dev[port] = dev;
4020
4021 sky2->port = port;
4022
4023 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4024 if (highmem)
4025 dev->features |= NETIF_F_HIGHDMA;
4026
4027 #ifdef SKY2_VLAN_TAG_USED
4028 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4029 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4030 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4031 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4032 dev->vlan_rx_register = sky2_vlan_rx_register;
4033 }
4034 #endif
4035
4036 /* read the mac address */
4037 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4038 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4039
4040 return dev;
4041 }
4042
4043 static void __devinit sky2_show_addr(struct net_device *dev)
4044 {
4045 const struct sky2_port *sky2 = netdev_priv(dev);
4046 DECLARE_MAC_BUF(mac);
4047
4048 if (netif_msg_probe(sky2))
4049 printk(KERN_INFO PFX "%s: addr %s\n",
4050 dev->name, print_mac(mac, dev->dev_addr));
4051 }
4052
4053 /* Handle software interrupt used during MSI test */
4054 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4055 {
4056 struct sky2_hw *hw = dev_id;
4057 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4058
4059 if (status == 0)
4060 return IRQ_NONE;
4061
4062 if (status & Y2_IS_IRQ_SW) {
4063 hw->flags |= SKY2_HW_USE_MSI;
4064 wake_up(&hw->msi_wait);
4065 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4066 }
4067 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4068
4069 return IRQ_HANDLED;
4070 }
4071
4072 /* Test interrupt path by forcing a a software IRQ */
4073 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4074 {
4075 struct pci_dev *pdev = hw->pdev;
4076 int err;
4077
4078 init_waitqueue_head (&hw->msi_wait);
4079
4080 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4081
4082 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4083 if (err) {
4084 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4085 return err;
4086 }
4087
4088 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4089 sky2_read8(hw, B0_CTST);
4090
4091 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4092
4093 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4094 /* MSI test failed, go back to INTx mode */
4095 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4096 "switching to INTx mode.\n");
4097
4098 err = -EOPNOTSUPP;
4099 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4100 }
4101
4102 sky2_write32(hw, B0_IMSK, 0);
4103 sky2_read32(hw, B0_IMSK);
4104
4105 free_irq(pdev->irq, hw);
4106
4107 return err;
4108 }
4109
4110 static int __devinit pci_wake_enabled(struct pci_dev *dev)
4111 {
4112 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
4113 u16 value;
4114
4115 if (!pm)
4116 return 0;
4117 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
4118 return 0;
4119 return value & PCI_PM_CTRL_PME_ENABLE;
4120 }
4121
4122 static int __devinit sky2_probe(struct pci_dev *pdev,
4123 const struct pci_device_id *ent)
4124 {
4125 struct net_device *dev;
4126 struct sky2_hw *hw;
4127 int err, using_dac = 0, wol_default;
4128
4129 err = pci_enable_device(pdev);
4130 if (err) {
4131 dev_err(&pdev->dev, "cannot enable PCI device\n");
4132 goto err_out;
4133 }
4134
4135 err = pci_request_regions(pdev, DRV_NAME);
4136 if (err) {
4137 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4138 goto err_out_disable;
4139 }
4140
4141 pci_set_master(pdev);
4142
4143 if (sizeof(dma_addr_t) > sizeof(u32) &&
4144 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
4145 using_dac = 1;
4146 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
4147 if (err < 0) {
4148 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4149 "for consistent allocations\n");
4150 goto err_out_free_regions;
4151 }
4152 } else {
4153 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
4154 if (err) {
4155 dev_err(&pdev->dev, "no usable DMA configuration\n");
4156 goto err_out_free_regions;
4157 }
4158 }
4159
4160 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
4161
4162 err = -ENOMEM;
4163 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
4164 if (!hw) {
4165 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4166 goto err_out_free_regions;
4167 }
4168
4169 hw->pdev = pdev;
4170
4171 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4172 if (!hw->regs) {
4173 dev_err(&pdev->dev, "cannot map device registers\n");
4174 goto err_out_free_hw;
4175 }
4176
4177 #ifdef __BIG_ENDIAN
4178 /* The sk98lin vendor driver uses hardware byte swapping but
4179 * this driver uses software swapping.
4180 */
4181 {
4182 u32 reg;
4183 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
4184 reg &= ~PCI_REV_DESC;
4185 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
4186 }
4187 #endif
4188
4189 /* ring for status responses */
4190 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4191 if (!hw->st_le)
4192 goto err_out_iounmap;
4193
4194 err = sky2_init(hw);
4195 if (err)
4196 goto err_out_iounmap;
4197
4198 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
4199 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
4200 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
4201 hw->chip_id, hw->chip_rev);
4202
4203 sky2_reset(hw);
4204
4205 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4206 if (!dev) {
4207 err = -ENOMEM;
4208 goto err_out_free_pci;
4209 }
4210
4211 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4212 err = sky2_test_msi(hw);
4213 if (err == -EOPNOTSUPP)
4214 pci_disable_msi(pdev);
4215 else if (err)
4216 goto err_out_free_netdev;
4217 }
4218
4219 err = register_netdev(dev);
4220 if (err) {
4221 dev_err(&pdev->dev, "cannot register net device\n");
4222 goto err_out_free_netdev;
4223 }
4224
4225 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4226
4227 err = request_irq(pdev->irq, sky2_intr,
4228 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4229 dev->name, hw);
4230 if (err) {
4231 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4232 goto err_out_unregister;
4233 }
4234 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4235 napi_enable(&hw->napi);
4236
4237 sky2_show_addr(dev);
4238
4239 if (hw->ports > 1) {
4240 struct net_device *dev1;
4241
4242 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4243 if (!dev1)
4244 dev_warn(&pdev->dev, "allocation for second device failed\n");
4245 else if ((err = register_netdev(dev1))) {
4246 dev_warn(&pdev->dev,
4247 "register of second port failed (%d)\n", err);
4248 hw->dev[1] = NULL;
4249 free_netdev(dev1);
4250 } else
4251 sky2_show_addr(dev1);
4252 }
4253
4254 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4255 INIT_WORK(&hw->restart_work, sky2_restart);
4256
4257 pci_set_drvdata(pdev, hw);
4258
4259 return 0;
4260
4261 err_out_unregister:
4262 if (hw->flags & SKY2_HW_USE_MSI)
4263 pci_disable_msi(pdev);
4264 unregister_netdev(dev);
4265 err_out_free_netdev:
4266 free_netdev(dev);
4267 err_out_free_pci:
4268 sky2_write8(hw, B0_CTST, CS_RST_SET);
4269 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4270 err_out_iounmap:
4271 iounmap(hw->regs);
4272 err_out_free_hw:
4273 kfree(hw);
4274 err_out_free_regions:
4275 pci_release_regions(pdev);
4276 err_out_disable:
4277 pci_disable_device(pdev);
4278 err_out:
4279 pci_set_drvdata(pdev, NULL);
4280 return err;
4281 }
4282
4283 static void __devexit sky2_remove(struct pci_dev *pdev)
4284 {
4285 struct sky2_hw *hw = pci_get_drvdata(pdev);
4286 int i;
4287
4288 if (!hw)
4289 return;
4290
4291 del_timer_sync(&hw->watchdog_timer);
4292 cancel_work_sync(&hw->restart_work);
4293
4294 for (i = hw->ports-1; i >= 0; --i)
4295 unregister_netdev(hw->dev[i]);
4296
4297 sky2_write32(hw, B0_IMSK, 0);
4298
4299 sky2_power_aux(hw);
4300
4301 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
4302 sky2_write8(hw, B0_CTST, CS_RST_SET);
4303 sky2_read8(hw, B0_CTST);
4304
4305 free_irq(pdev->irq, hw);
4306 if (hw->flags & SKY2_HW_USE_MSI)
4307 pci_disable_msi(pdev);
4308 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4309 pci_release_regions(pdev);
4310 pci_disable_device(pdev);
4311
4312 for (i = hw->ports-1; i >= 0; --i)
4313 free_netdev(hw->dev[i]);
4314
4315 iounmap(hw->regs);
4316 kfree(hw);
4317
4318 pci_set_drvdata(pdev, NULL);
4319 }
4320
4321 #ifdef CONFIG_PM
4322 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4323 {
4324 struct sky2_hw *hw = pci_get_drvdata(pdev);
4325 int i, wol = 0;
4326
4327 if (!hw)
4328 return 0;
4329
4330 for (i = 0; i < hw->ports; i++) {
4331 struct net_device *dev = hw->dev[i];
4332 struct sky2_port *sky2 = netdev_priv(dev);
4333
4334 if (netif_running(dev))
4335 sky2_down(dev);
4336
4337 if (sky2->wol)
4338 sky2_wol_init(sky2);
4339
4340 wol |= sky2->wol;
4341 }
4342
4343 sky2_write32(hw, B0_IMSK, 0);
4344 napi_disable(&hw->napi);
4345 sky2_power_aux(hw);
4346
4347 pci_save_state(pdev);
4348 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4349 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4350
4351 return 0;
4352 }
4353
4354 static int sky2_resume(struct pci_dev *pdev)
4355 {
4356 struct sky2_hw *hw = pci_get_drvdata(pdev);
4357 int i, err;
4358
4359 if (!hw)
4360 return 0;
4361
4362 err = pci_set_power_state(pdev, PCI_D0);
4363 if (err)
4364 goto out;
4365
4366 err = pci_restore_state(pdev);
4367 if (err)
4368 goto out;
4369
4370 pci_enable_wake(pdev, PCI_D0, 0);
4371
4372 /* Re-enable all clocks */
4373 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4374 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4375 hw->chip_id == CHIP_ID_YUKON_FE_P)
4376 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4377
4378 sky2_reset(hw);
4379 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4380 napi_enable(&hw->napi);
4381
4382 for (i = 0; i < hw->ports; i++) {
4383 struct net_device *dev = hw->dev[i];
4384 if (netif_running(dev)) {
4385 err = sky2_up(dev);
4386 if (err) {
4387 printk(KERN_ERR PFX "%s: could not up: %d\n",
4388 dev->name, err);
4389 dev_close(dev);
4390 goto out;
4391 }
4392
4393 sky2_set_multicast(dev);
4394 }
4395 }
4396
4397 return 0;
4398 out:
4399 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4400 pci_disable_device(pdev);
4401 return err;
4402 }
4403 #endif
4404
4405 static void sky2_shutdown(struct pci_dev *pdev)
4406 {
4407 struct sky2_hw *hw = pci_get_drvdata(pdev);
4408 int i, wol = 0;
4409
4410 if (!hw)
4411 return;
4412
4413 del_timer_sync(&hw->watchdog_timer);
4414
4415 for (i = 0; i < hw->ports; i++) {
4416 struct net_device *dev = hw->dev[i];
4417 struct sky2_port *sky2 = netdev_priv(dev);
4418
4419 if (sky2->wol) {
4420 wol = 1;
4421 sky2_wol_init(sky2);
4422 }
4423 }
4424
4425 if (wol)
4426 sky2_power_aux(hw);
4427
4428 pci_enable_wake(pdev, PCI_D3hot, wol);
4429 pci_enable_wake(pdev, PCI_D3cold, wol);
4430
4431 pci_disable_device(pdev);
4432 pci_set_power_state(pdev, PCI_D3hot);
4433
4434 }
4435
4436 static struct pci_driver sky2_driver = {
4437 .name = DRV_NAME,
4438 .id_table = sky2_id_table,
4439 .probe = sky2_probe,
4440 .remove = __devexit_p(sky2_remove),
4441 #ifdef CONFIG_PM
4442 .suspend = sky2_suspend,
4443 .resume = sky2_resume,
4444 #endif
4445 .shutdown = sky2_shutdown,
4446 };
4447
4448 static int __init sky2_init_module(void)
4449 {
4450 sky2_debug_init();
4451 return pci_register_driver(&sky2_driver);
4452 }
4453
4454 static void __exit sky2_cleanup_module(void)
4455 {
4456 pci_unregister_driver(&sky2_driver);
4457 sky2_debug_cleanup();
4458 }
4459
4460 module_init(sky2_init_module);
4461 module_exit(sky2_cleanup_module);
4462
4463 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4464 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4465 MODULE_LICENSE("GPL");
4466 MODULE_VERSION(DRV_VERSION);
WRT350N Kernel Patches