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x86: cpa: move clflush_cache_range()
[wrt350n-kernel.git] / sound / sparc / dbri.c
blob376b98691c965bf228a585a0f619ed6a744fb50a
1 /*
2 * Driver for DBRI sound chip found on Sparcs.
3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
4 *
5 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
6 *
7 * Based entirely upon drivers/sbus/audio/dbri.c which is:
8 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
9 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
10 *
11 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
12 * on Sun SPARCStation 10, 20, LX and Voyager models.
13 *
14 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
15 * data time multiplexer with ISDN support (aka T7259)
16 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
17 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
18 * Documentation:
19 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
20 * Sparc Technology Business (courtesy of Sun Support)
21 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
22 * available from the Lucent (formerly AT&T microelectronics) home
23 * page.
24 * - http://www.freesoft.org/Linux/DBRI/
25 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
26 * Interfaces: CHI, Audio In & Out, 2 bits parallel
27 * Documentation: from the Crystal Semiconductor home page.
28 *
29 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
30 * memory and a serial device (long pipes, no. 0-15) or between two serial
31 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
32 * device (short pipes).
33 * A timeslot defines the bit-offset and no. of bits read from a serial device.
34 * The timeslots are linked to 6 circular lists, one for each direction for
35 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
36 * (the second one is a monitor/tee pipe, valid only for serial input).
37 *
38 * The mmcodec is connected via the CHI bus and needs the data & some
39 * parameters (volume, output selection) time multiplexed in 8 byte
40 * chunks. It also has a control mode, which serves for audio format setting.
41 *
42 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
43 * the same CHI bus, so I thought perhaps it is possible to use the on-board
44 * & the speakerbox codec simultaneously, giving 2 (not very independent :-)
45 * audio devices. But the SUN HW group decided against it, at least on my
46 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
47 * connected.
48 *
49 * I've tried to stick to the following function naming conventions:
50 * snd_* ALSA stuff
51 * cs4215_* CS4215 codec specific stuff
52 * dbri_* DBRI high-level stuff
53 * other DBRI low-level stuff
54 */
55
56 #include <sound/driver.h>
57 #include <linux/interrupt.h>
58 #include <linux/delay.h>
59 #include <linux/irq.h>
60 #include <linux/io.h>
61
62 #include <sound/core.h>
63 #include <sound/pcm.h>
64 #include <sound/pcm_params.h>
65 #include <sound/info.h>
66 #include <sound/control.h>
67 #include <sound/initval.h>
68
69 #include <linux/of.h>
70 #include <asm/sbus.h>
71 #include <asm/atomic.h>
72
73 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
74 MODULE_DESCRIPTION("Sun DBRI");
75 MODULE_LICENSE("GPL");
76 MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
77
78 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
79 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
80 /* Enable this card */
81 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
82
83 module_param_array(index, int, NULL, 0444);
84 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
85 module_param_array(id, charp, NULL, 0444);
86 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
87 module_param_array(enable, bool, NULL, 0444);
88 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
89
90 #undef DBRI_DEBUG
91
92 #define D_INT (1<<0)
93 #define D_GEN (1<<1)
94 #define D_CMD (1<<2)
95 #define D_MM (1<<3)
96 #define D_USR (1<<4)
97 #define D_DESC (1<<5)
98
99 static int dbri_debug;
100 module_param(dbri_debug, int, 0644);
101 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
102
103 #ifdef DBRI_DEBUG
104 static char *cmds[] = {
105 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
106 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
107 };
108
109 #define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x)
110
111 #else
112 #define dprintk(a, x...) do { } while (0)
113
114 #endif /* DBRI_DEBUG */
115
116 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
117 (intr << 27) | \
118 value)
119
120 /***************************************************************************
121 CS4215 specific definitions and structures
122 ****************************************************************************/
123
124 struct cs4215 {
125 __u8 data[4]; /* Data mode: Time slots 5-8 */
126 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
127 __u8 onboard;
128 __u8 offset; /* Bit offset from frame sync to time slot 1 */
129 volatile __u32 status;
130 volatile __u32 version;
131 __u8 precision; /* In bits, either 8 or 16 */
132 __u8 channels; /* 1 or 2 */
133 };
134
135 /*
136 * Control mode first
137 */
138
139 /* Time Slot 1, Status register */
140 #define CS4215_CLB (1<<2) /* Control Latch Bit */
141 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
142 /* 0: line: 2.8V, speaker 8V */
143 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
144 #define CS4215_RSRVD_1 (1<<5)
145
146 /* Time Slot 2, Data Format Register */
147 #define CS4215_DFR_LINEAR16 0
148 #define CS4215_DFR_ULAW 1
149 #define CS4215_DFR_ALAW 2
150 #define CS4215_DFR_LINEAR8 3
151 #define CS4215_DFR_STEREO (1<<2)
152 static struct {
153 unsigned short freq;
154 unsigned char xtal;
155 unsigned char csval;
156 } CS4215_FREQ[] = {
157 { 8000, (1 << 4), (0 << 3) },
158 { 16000, (1 << 4), (1 << 3) },
159 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
160 { 32000, (1 << 4), (3 << 3) },
161 /* { NA, (1 << 4), (4 << 3) }, */
162 /* { NA, (1 << 4), (5 << 3) }, */
163 { 48000, (1 << 4), (6 << 3) },
164 { 9600, (1 << 4), (7 << 3) },
165 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
166 { 11025, (2 << 4), (1 << 3) },
167 { 18900, (2 << 4), (2 << 3) },
168 { 22050, (2 << 4), (3 << 3) },
169 { 37800, (2 << 4), (4 << 3) },
170 { 44100, (2 << 4), (5 << 3) },
171 { 33075, (2 << 4), (6 << 3) },
172 { 6615, (2 << 4), (7 << 3) },
173 { 0, 0, 0}
174 };
175
176 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
177
178 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
179
180 /* Time Slot 3, Serial Port Control register */
181 #define CS4215_XEN (1<<0) /* 0: Enable serial output */
182 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
183 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
184 #define CS4215_BSEL_128 (1<<2)
185 #define CS4215_BSEL_256 (2<<2)
186 #define CS4215_MCK_MAST (0<<4) /* Master clock */
187 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
188 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
189 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
190 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
191
192 /* Time Slot 4, Test Register */
193 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
194 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */
195
196 /* Time Slot 5, Parallel Port Register */
197 /* Read only here and the same as the in data mode */
198
199 /* Time Slot 6, Reserved */
200
201 /* Time Slot 7, Version Register */
202 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
203
204 /* Time Slot 8, Reserved */
205
206 /*
207 * Data mode
208 */
209 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
210
211 /* Time Slot 5, Output Setting */
212 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
213 #define CS4215_LE (1<<6) /* Line Out Enable */
214 #define CS4215_HE (1<<7) /* Headphone Enable */
215
216 /* Time Slot 6, Output Setting */
217 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
218 #define CS4215_SE (1<<6) /* Speaker Enable */
219 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
220
221 /* Time Slot 7, Input Setting */
222 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
223 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
224 #define CS4215_OVR (1<<5) /* 1: Over range condition occurred */
225 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
226 #define CS4215_PIO1 (1<<7)
227
228 /* Time Slot 8, Input Setting */
229 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
230 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
231
232 /***************************************************************************
233 DBRI specific definitions and structures
234 ****************************************************************************/
235
236 /* DBRI main registers */
237 #define REG0 0x00 /* Status and Control */
238 #define REG1 0x04 /* Mode and Interrupt */
239 #define REG2 0x08 /* Parallel IO */
240 #define REG3 0x0c /* Test */
241 #define REG8 0x20 /* Command Queue Pointer */
242 #define REG9 0x24 /* Interrupt Queue Pointer */
243
244 #define DBRI_NO_CMDS 64
245 #define DBRI_INT_BLK 64
246 #define DBRI_NO_DESCS 64
247 #define DBRI_NO_PIPES 32
248 #define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
249
250 #define DBRI_REC 0
251 #define DBRI_PLAY 1
252 #define DBRI_NO_STREAMS 2
253
254 /* One transmit/receive descriptor */
255 /* When ba != 0 descriptor is used */
256 struct dbri_mem {
257 volatile __u32 word1;
258 __u32 ba; /* Transmit/Receive Buffer Address */
259 __u32 nda; /* Next Descriptor Address */
260 volatile __u32 word4;
261 };
262
263 /* This structure is in a DMA region where it can accessed by both
264 * the CPU and the DBRI
265 */
266 struct dbri_dma {
267 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
268 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
269 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
270 };
271
272 #define dbri_dma_off(member, elem) \
273 ((u32)(unsigned long) \
274 (&(((struct dbri_dma *)0)->member[elem])))
275
276 enum in_or_out { PIPEinput, PIPEoutput };
277
278 struct dbri_pipe {
279 u32 sdp; /* SDP command word */
280 int nextpipe; /* Next pipe in linked list */
281 int length; /* Length of timeslot (bits) */
282 int first_desc; /* Index of first descriptor */
283 int desc; /* Index of active descriptor */
284 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
285 };
286
287 /* Per stream (playback or record) information */
288 struct dbri_streaminfo {
289 struct snd_pcm_substream *substream;
290 u32 dvma_buffer; /* Device view of ALSA DMA buffer */
291 int size; /* Size of DMA buffer */
292 size_t offset; /* offset in user buffer */
293 int pipe; /* Data pipe used */
294 int left_gain; /* mixer elements */
295 int right_gain;
296 };
297
298 /* This structure holds the information for both chips (DBRI & CS4215) */
299 struct snd_dbri {
300 int regs_size, irq; /* Needed for unload */
301 struct sbus_dev *sdev; /* SBUS device info */
302 spinlock_t lock;
303
304 struct dbri_dma *dma; /* Pointer to our DMA block */
305 u32 dma_dvma; /* DBRI visible DMA address */
306
307 void __iomem *regs; /* dbri HW regs */
308 int dbri_irqp; /* intr queue pointer */
309
310 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
311 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
312 spinlock_t cmdlock; /* Protects cmd queue accesses */
313 s32 *cmdptr; /* Pointer to the last queued cmd */
314
315 int chi_bpf;
316
317 struct cs4215 mm; /* mmcodec special info */
318 /* per stream (playback/record) info */
319 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
320 };
321
322 #define DBRI_MAX_VOLUME 63 /* Output volume */
323 #define DBRI_MAX_GAIN 15 /* Input gain */
324
325 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
326 #define D_P (1<<15) /* Program command & queue pointer valid */
327 #define D_G (1<<14) /* Allow 4-Word SBus Burst */
328 #define D_S (1<<13) /* Allow 16-Word SBus Burst */
329 #define D_E (1<<12) /* Allow 8-Word SBus Burst */
330 #define D_X (1<<7) /* Sanity Timer Disable */
331 #define D_T (1<<6) /* Permit activation of the TE interface */
332 #define D_N (1<<5) /* Permit activation of the NT interface */
333 #define D_C (1<<4) /* Permit activation of the CHI interface */
334 #define D_F (1<<3) /* Force Sanity Timer Time-Out */
335 #define D_D (1<<2) /* Disable Master Mode */
336 #define D_H (1<<1) /* Halt for Analysis */
337 #define D_R (1<<0) /* Soft Reset */
338
339 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
340 #define D_LITTLE_END (1<<8) /* Byte Order */
341 #define D_BIG_END (0<<8) /* Byte Order */
342 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */
343 #define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */
344 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */
345 #define D_MBE (1<<1) /* Burst Error on SBus (read only) */
346 #define D_IR (1<<0) /* Interrupt Indicator (read only) */
347
348 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
349 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */
350 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */
351 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */
352 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */
353 #define D_ENPIO (0xf0) /* Enable all the pins */
354 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
355 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
356 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
357 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
358
359 /* DBRI Commands (Page 20) */
360 #define D_WAIT 0x0 /* Stop execution */
361 #define D_PAUSE 0x1 /* Flush long pipes */
362 #define D_JUMP 0x2 /* New command queue */
363 #define D_IIQ 0x3 /* Initialize Interrupt Queue */
364 #define D_REX 0x4 /* Report command execution via interrupt */
365 #define D_SDP 0x5 /* Setup Data Pipe */
366 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
367 #define D_DTS 0x7 /* Define Time Slot */
368 #define D_SSP 0x8 /* Set short Data Pipe */
369 #define D_CHI 0x9 /* Set CHI Global Mode */
370 #define D_NT 0xa /* NT Command */
371 #define D_TE 0xb /* TE Command */
372 #define D_CDEC 0xc /* Codec setup */
373 #define D_TEST 0xd /* No comment */
374 #define D_CDM 0xe /* CHI Data mode command */
375
376 /* Special bits for some commands */
377 #define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */
378
379 /* Setup Data Pipe */
380 /* IRM */
381 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */
382 #define D_SDP_CHANGE (2<<18) /* Report any changes */
383 #define D_SDP_EVERY (3<<18) /* Report any changes */
384 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */
385 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
386
387 /* Pipe data MODE */
388 #define D_SDP_MEM (0<<13) /* To/from memory */
389 #define D_SDP_HDLC (2<<13)
390 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
391 #define D_SDP_SER (4<<13) /* Serial to serial */
392 #define D_SDP_FIXED (6<<13) /* Short only */
393 #define D_SDP_MODE(v) ((v)&(7<<13))
394
395 #define D_SDP_TO_SER (1<<12) /* Direction */
396 #define D_SDP_FROM_SER (0<<12) /* Direction */
397 #define D_SDP_MSB (1<<11) /* Bit order within Byte */
398 #define D_SDP_LSB (0<<11) /* Bit order within Byte */
399 #define D_SDP_P (1<<10) /* Pointer Valid */
400 #define D_SDP_A (1<<8) /* Abort */
401 #define D_SDP_C (1<<7) /* Clear */
402
403 /* Define Time Slot */
404 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
405 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
406 #define D_DTS_INS (1<<15) /* Insert Time Slot */
407 #define D_DTS_DEL (0<<15) /* Delete Time Slot */
408 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
409 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
410
411 /* Time Slot defines */
412 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
413 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
414 #define D_TS_DI (1<<13) /* Data Invert */
415 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
416 #define D_TS_MONITOR (2<<10) /* Monitor pipe */
417 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
418 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */
419 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
420 #define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */
421
422 /* Concentration Highway Interface Modes */
423 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
424 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
425 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
426 #define D_CHI_OD (1<<13) /* Open Drain Enable */
427 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
428 #define D_CHI_FD (1<<11) /* Frame Drive */
429 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
430
431 /* NT: These are here for completeness */
432 #define D_NT_FBIT (1<<17) /* Frame Bit */
433 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
434 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
435 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
436 #define D_NT_ISNT (1<<13) /* Configure interface as NT */
437 #define D_NT_FT (1<<12) /* Fixed Timing */
438 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
439 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */
440 #define D_NT_ACT (1<<9) /* Activate Interface */
441 #define D_NT_MFE (1<<8) /* Multiframe Enable */
442 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
443 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
444 #define D_NT_FACT (1<<1) /* Force Activation */
445 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
446
447 /* Codec Setup */
448 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
449 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
450 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
451
452 /* Test */
453 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
454 #define D_TEST_SIZE(v) ((v)<<11) /* */
455 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
456 #define D_TEST_PROC 0x6 /* Microprocessor test */
457 #define D_TEST_SER 0x7 /* Serial-Controller test */
458 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
459 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
460 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
461 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
462 #define D_TEST_DUMP 0xe /* ROM Dump */
463
464 /* CHI Data Mode */
465 #define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */
466 #define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */
467 #define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */
468 #define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */
469 #define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */
470 #define D_CDM_REN (1 << 0) /* Receive Highway Enable */
471
472 /* The Interrupts */
473 #define D_INTR_BRDY 1 /* Buffer Ready for processing */
474 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
475 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
476 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
477 #define D_INTR_EOL 5 /* End of List */
478 #define D_INTR_CMDI 6 /* Command has bean read */
479 #define D_INTR_XCMP 8 /* Transmission of frame complete */
480 #define D_INTR_SBRI 9 /* BRI status change info */
481 #define D_INTR_FXDT 10 /* Fixed data change */
482 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
483 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
484 #define D_INTR_DBYT 12 /* Dropped by frame slip */
485 #define D_INTR_RBYT 13 /* Repeated by frame slip */
486 #define D_INTR_LINT 14 /* Lost Interrupt */
487 #define D_INTR_UNDR 15 /* DMA underrun */
488
489 #define D_INTR_TE 32
490 #define D_INTR_NT 34
491 #define D_INTR_CHI 36
492 #define D_INTR_CMD 38
493
494 #define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
495 #define D_INTR_GETCODE(v) (((v) >> 20) & 0xf)
496 #define D_INTR_GETCMD(v) (((v) >> 16) & 0xf)
497 #define D_INTR_GETVAL(v) ((v) & 0xffff)
498 #define D_INTR_GETRVAL(v) ((v) & 0xfffff)
499
500 #define D_P_0 0 /* TE receive anchor */
501 #define D_P_1 1 /* TE transmit anchor */
502 #define D_P_2 2 /* NT transmit anchor */
503 #define D_P_3 3 /* NT receive anchor */
504 #define D_P_4 4 /* CHI send data */
505 #define D_P_5 5 /* CHI receive data */
506 #define D_P_6 6 /* */
507 #define D_P_7 7 /* */
508 #define D_P_8 8 /* */
509 #define D_P_9 9 /* */
510 #define D_P_10 10 /* */
511 #define D_P_11 11 /* */
512 #define D_P_12 12 /* */
513 #define D_P_13 13 /* */
514 #define D_P_14 14 /* */
515 #define D_P_15 15 /* */
516 #define D_P_16 16 /* CHI anchor pipe */
517 #define D_P_17 17 /* CHI send */
518 #define D_P_18 18 /* CHI receive */
519 #define D_P_19 19 /* CHI receive */
520 #define D_P_20 20 /* CHI receive */
521 #define D_P_21 21 /* */
522 #define D_P_22 22 /* */
523 #define D_P_23 23 /* */
524 #define D_P_24 24 /* */
525 #define D_P_25 25 /* */
526 #define D_P_26 26 /* */
527 #define D_P_27 27 /* */
528 #define D_P_28 28 /* */
529 #define D_P_29 29 /* */
530 #define D_P_30 30 /* */
531 #define D_P_31 31 /* */
532
533 /* Transmit descriptor defines */
534 #define DBRI_TD_F (1 << 31) /* End of Frame */
535 #define DBRI_TD_D (1 << 30) /* Do not append CRC */
536 #define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */
537 #define DBRI_TD_B (1 << 15) /* Final interrupt */
538 #define DBRI_TD_M (1 << 14) /* Marker interrupt */
539 #define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */
540 #define DBRI_TD_FCNT(v) (v) /* Flag Count */
541 #define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */
542 #define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */
543 #define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */
544 #define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */
545 /* Maximum buffer size per TD: almost 8KB */
546 #define DBRI_TD_MAXCNT ((1 << 13) - 4)
547
548 /* Receive descriptor defines */
549 #define DBRI_RD_F (1 << 31) /* End of Frame */
550 #define DBRI_RD_C (1 << 30) /* Completed buffer */
551 #define DBRI_RD_B (1 << 15) /* Final interrupt */
552 #define DBRI_RD_M (1 << 14) /* Marker interrupt */
553 #define DBRI_RD_BCNT(v) (v) /* Buffer size */
554 #define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */
555 #define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */
556 #define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */
557 #define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */
558 #define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */
559 #define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */
560
561 /* stream_info[] access */
562 /* Translate the ALSA direction into the array index */
563 #define DBRI_STREAMNO(substream) \
564 (substream->stream == \
565 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)
566
567 /* Return a pointer to dbri_streaminfo */
568 #define DBRI_STREAM(dbri, substream) \
569 &dbri->stream_info[DBRI_STREAMNO(substream)]
570
571 /*
572 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
573 * So we have to reverse the bits. Note: not all bit lengths are supported
574 */
575 static __u32 reverse_bytes(__u32 b, int len)
576 {
577 switch (len) {
578 case 32:
579 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
580 case 16:
581 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
582 case 8:
583 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
584 case 4:
585 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
586 case 2:
587 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
588 case 1:
589 case 0:
590 break;
591 default:
592 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
593 };
594
595 return b;
596 }
597
598 /*
599 ****************************************************************************
600 ************** DBRI initialization and command synchronization *************
601 ****************************************************************************
602
603 Commands are sent to the DBRI by building a list of them in memory,
604 then writing the address of the first list item to DBRI register 8.
605 The list is terminated with a WAIT command, which generates a
606 CPU interrupt to signal completion.
607
608 Since the DBRI can run in parallel with the CPU, several means of
609 synchronization present themselves. The method implemented here uses
610 the dbri_cmdwait() to wait for execution of batch of sent commands.
611
612 A circular command buffer is used here. A new command is being added
613 while another can be executed. The scheme works by adding two WAIT commands
614 after each sent batch of commands. When the next batch is prepared it is
615 added after the WAIT commands then the WAITs are replaced with single JUMP
616 command to the new batch. The the DBRI is forced to reread the last WAIT
617 command (replaced by the JUMP by then). If the DBRI is still executing
618 previous commands the request to reread the WAIT command is ignored.
619
620 Every time a routine wants to write commands to the DBRI, it must
621 first call dbri_cmdlock() and get pointer to a free space in
622 dbri->dma->cmd buffer. After this, the commands can be written to
623 the buffer, and dbri_cmdsend() is called with the final pointer value
624 to send them to the DBRI.
625
626 */
627
628 #define MAXLOOPS 20
629 /*
630 * Wait for the current command string to execute
631 */
632 static void dbri_cmdwait(struct snd_dbri *dbri)
633 {
634 int maxloops = MAXLOOPS;
635 unsigned long flags;
636
637 /* Delay if previous commands are still being processed */
638 spin_lock_irqsave(&dbri->lock, flags);
639 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
640 spin_unlock_irqrestore(&dbri->lock, flags);
641 msleep_interruptible(1);
642 spin_lock_irqsave(&dbri->lock, flags);
643 }
644 spin_unlock_irqrestore(&dbri->lock, flags);
645
646 if (maxloops == 0)
647 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
648 else
649 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
650 MAXLOOPS - maxloops - 1);
651 }
652 /*
653 * Lock the command queue and return pointer to space for len cmd words
654 * It locks the cmdlock spinlock.
655 */
656 static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
657 {
658 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
659 len += 2;
660 spin_lock(&dbri->cmdlock);
661 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
662 return dbri->cmdptr + 2;
663 else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma)
664 return dbri->dma->cmd;
665 else
666 printk(KERN_ERR "DBRI: no space for commands.");
667
668 return NULL;
669 }
670
671 /*
672 * Send prepared cmd string. It works by writing a JUMP cmd into
673 * the last WAIT cmd and force DBRI to reread the cmd.
674 * The JUMP cmd points to the new cmd string.
675 * It also releases the cmdlock spinlock.
676 *
677 * Lock must be held before calling this.
678 */
679 static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
680 {
681 s32 tmp, addr;
682 static int wait_id = 0;
683
684 wait_id++;
685 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */
686 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
687 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
688
689 /* Replace the last command with JUMP */
690 addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32);
691 *(dbri->cmdptr+1) = addr;
692 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
693
694 #ifdef DBRI_DEBUG
695 if (cmd > dbri->cmdptr) {
696 s32 *ptr;
697
698 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
699 dprintk(D_CMD, "cmd: %lx:%08x\n",
700 (unsigned long)ptr, *ptr);
701 } else {
702 s32 *ptr = dbri->cmdptr;
703
704 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
705 ptr++;
706 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
707 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
708 dprintk(D_CMD, "cmd: %lx:%08x\n",
709 (unsigned long)ptr, *ptr);
710 }
711 #endif
712
713 /* Reread the last command */
714 tmp = sbus_readl(dbri->regs + REG0);
715 tmp |= D_P;
716 sbus_writel(tmp, dbri->regs + REG0);
717
718 dbri->cmdptr = cmd;
719 spin_unlock(&dbri->cmdlock);
720 }
721
722 /* Lock must be held when calling this */
723 static void dbri_reset(struct snd_dbri *dbri)
724 {
725 int i;
726 u32 tmp;
727
728 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
729 sbus_readl(dbri->regs + REG0),
730 sbus_readl(dbri->regs + REG2),
731 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
732
733 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
734 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
735 udelay(10);
736
737 /* A brute approach - DBRI falls back to working burst size by itself
738 * On SS20 D_S does not work, so do not try so high. */
739 tmp = sbus_readl(dbri->regs + REG0);
740 tmp |= D_G | D_E;
741 tmp &= ~D_S;
742 sbus_writel(tmp, dbri->regs + REG0);
743 }
744
745 /* Lock must not be held before calling this */
746 static void __devinit dbri_initialize(struct snd_dbri *dbri)
747 {
748 s32 *cmd;
749 u32 dma_addr;
750 unsigned long flags;
751 int n;
752
753 spin_lock_irqsave(&dbri->lock, flags);
754
755 dbri_reset(dbri);
756
757 /* Initialize pipes */
758 for (n = 0; n < DBRI_NO_PIPES; n++)
759 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
760
761 spin_lock_init(&dbri->cmdlock);
762 /*
763 * Initialize the interrupt ring buffer.
764 */
765 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
766 dbri->dma->intr[0] = dma_addr;
767 dbri->dbri_irqp = 1;
768 /*
769 * Set up the interrupt queue
770 */
771 spin_lock(&dbri->cmdlock);
772 cmd = dbri->cmdptr = dbri->dma->cmd;
773 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
774 *(cmd++) = dma_addr;
775 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
776 dbri->cmdptr = cmd;
777 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
778 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
779 dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0);
780 sbus_writel(dma_addr, dbri->regs + REG8);
781 spin_unlock(&dbri->cmdlock);
782
783 spin_unlock_irqrestore(&dbri->lock, flags);
784 dbri_cmdwait(dbri);
785 }
786
787 /*
788 ****************************************************************************
789 ************************** DBRI data pipe management ***********************
790 ****************************************************************************
791
792 While DBRI control functions use the command and interrupt buffers, the
793 main data path takes the form of data pipes, which can be short (command
794 and interrupt driven), or long (attached to DMA buffers). These functions
795 provide a rudimentary means of setting up and managing the DBRI's pipes,
796 but the calling functions have to make sure they respect the pipes' linked
797 list ordering, among other things. The transmit and receive functions
798 here interface closely with the transmit and receive interrupt code.
799
800 */
801 static inline int pipe_active(struct snd_dbri *dbri, int pipe)
802 {
803 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
804 }
805
806 /* reset_pipe(dbri, pipe)
807 *
808 * Called on an in-use pipe to clear anything being transmitted or received
809 * Lock must be held before calling this.
810 */
811 static void reset_pipe(struct snd_dbri *dbri, int pipe)
812 {
813 int sdp;
814 int desc;
815 s32 *cmd;
816
817 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
818 printk(KERN_ERR "DBRI: reset_pipe called with "
819 "illegal pipe number\n");
820 return;
821 }
822
823 sdp = dbri->pipes[pipe].sdp;
824 if (sdp == 0) {
825 printk(KERN_ERR "DBRI: reset_pipe called "
826 "on uninitialized pipe\n");
827 return;
828 }
829
830 cmd = dbri_cmdlock(dbri, 3);
831 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
832 *(cmd++) = 0;
833 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
834 dbri_cmdsend(dbri, cmd, 3);
835
836 desc = dbri->pipes[pipe].first_desc;
837 if (desc >= 0)
838 do {
839 dbri->dma->desc[desc].ba = 0;
840 dbri->dma->desc[desc].nda = 0;
841 desc = dbri->next_desc[desc];
842 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
843
844 dbri->pipes[pipe].desc = -1;
845 dbri->pipes[pipe].first_desc = -1;
846 }
847
848 /*
849 * Lock must be held before calling this.
850 */
851 static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
852 {
853 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
854 printk(KERN_ERR "DBRI: setup_pipe called "
855 "with illegal pipe number\n");
856 return;
857 }
858
859 if ((sdp & 0xf800) != sdp) {
860 printk(KERN_ERR "DBRI: setup_pipe called "
861 "with strange SDP value\n");
862 /* sdp &= 0xf800; */
863 }
864
865 /* If this is a fixed receive pipe, arrange for an interrupt
866 * every time its data changes
867 */
868 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
869 sdp |= D_SDP_CHANGE;
870
871 sdp |= D_PIPE(pipe);
872 dbri->pipes[pipe].sdp = sdp;
873 dbri->pipes[pipe].desc = -1;
874 dbri->pipes[pipe].first_desc = -1;
875
876 reset_pipe(dbri, pipe);
877 }
878
879 /*
880 * Lock must be held before calling this.
881 */
882 static void link_time_slot(struct snd_dbri *dbri, int pipe,
883 int prevpipe, int nextpipe,
884 int length, int cycle)
885 {
886 s32 *cmd;
887 int val;
888
889 if (pipe < 0 || pipe > DBRI_MAX_PIPE
890 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
891 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
892 printk(KERN_ERR
893 "DBRI: link_time_slot called with illegal pipe number\n");
894 return;
895 }
896
897 if (dbri->pipes[pipe].sdp == 0
898 || dbri->pipes[prevpipe].sdp == 0
899 || dbri->pipes[nextpipe].sdp == 0) {
900 printk(KERN_ERR "DBRI: link_time_slot called "
901 "on uninitialized pipe\n");
902 return;
903 }
904
905 dbri->pipes[prevpipe].nextpipe = pipe;
906 dbri->pipes[pipe].nextpipe = nextpipe;
907 dbri->pipes[pipe].length = length;
908
909 cmd = dbri_cmdlock(dbri, 4);
910
911 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
912 /* Deal with CHI special case:
913 * "If transmission on edges 0 or 1 is desired, then cycle n
914 * (where n = # of bit times per frame...) must be used."
915 * - DBRI data sheet, page 11
916 */
917 if (prevpipe == 16 && cycle == 0)
918 cycle = dbri->chi_bpf;
919
920 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
921 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
922 *(cmd++) = 0;
923 *(cmd++) =
924 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
925 } else {
926 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
927 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
928 *(cmd++) =
929 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
930 *(cmd++) = 0;
931 }
932 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
933
934 dbri_cmdsend(dbri, cmd, 4);
935 }
936
937 #if 0
938 /*
939 * Lock must be held before calling this.
940 */
941 static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
942 enum in_or_out direction, int prevpipe,
943 int nextpipe)
944 {
945 s32 *cmd;
946 int val;
947
948 if (pipe < 0 || pipe > DBRI_MAX_PIPE
949 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
950 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
951 printk(KERN_ERR
952 "DBRI: unlink_time_slot called with illegal pipe number\n");
953 return;
954 }
955
956 cmd = dbri_cmdlock(dbri, 4);
957
958 if (direction == PIPEinput) {
959 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
960 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
961 *(cmd++) = D_TS_NEXT(nextpipe);
962 *(cmd++) = 0;
963 } else {
964 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
965 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
966 *(cmd++) = 0;
967 *(cmd++) = D_TS_NEXT(nextpipe);
968 }
969 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
970
971 dbri_cmdsend(dbri, cmd, 4);
972 }
973 #endif
974
975 /* xmit_fixed() / recv_fixed()
976 *
977 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
978 * expected to change much, and which we don't need to buffer.
979 * The DBRI only interrupts us when the data changes (receive pipes),
980 * or only changes the data when this function is called (transmit pipes).
981 * Only short pipes (numbers 16-31) can be used in fixed data mode.
982 *
983 * These function operate on a 32-bit field, no matter how large
984 * the actual time slot is. The interrupt handler takes care of bit
985 * ordering and alignment. An 8-bit time slot will always end up
986 * in the low-order 8 bits, filled either MSB-first or LSB-first,
987 * depending on the settings passed to setup_pipe().
988 *
989 * Lock must not be held before calling it.
990 */
991 static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
992 {
993 s32 *cmd;
994 unsigned long flags;
995
996 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
997 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
998 return;
999 }
1000
1001 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
1002 printk(KERN_ERR "DBRI: xmit_fixed: "
1003 "Uninitialized pipe %d\n", pipe);
1004 return;
1005 }
1006
1007 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1008 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
1009 return;
1010 }
1011
1012 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1013 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n",
1014 pipe);
1015 return;
1016 }
1017
1018 /* DBRI short pipes always transmit LSB first */
1019
1020 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1021 data = reverse_bytes(data, dbri->pipes[pipe].length);
1022
1023 cmd = dbri_cmdlock(dbri, 3);
1024
1025 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1026 *(cmd++) = data;
1027 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1028
1029 spin_lock_irqsave(&dbri->lock, flags);
1030 dbri_cmdsend(dbri, cmd, 3);
1031 spin_unlock_irqrestore(&dbri->lock, flags);
1032 dbri_cmdwait(dbri);
1033
1034 }
1035
1036 static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
1037 {
1038 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
1039 printk(KERN_ERR "DBRI: recv_fixed called with "
1040 "illegal pipe number\n");
1041 return;
1042 }
1043
1044 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1045 printk(KERN_ERR "DBRI: recv_fixed called on "
1046 "non-fixed pipe %d\n", pipe);
1047 return;
1048 }
1049
1050 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1051 printk(KERN_ERR "DBRI: recv_fixed called on "
1052 "transmit pipe %d\n", pipe);
1053 return;
1054 }
1055
1056 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1057 }
1058
1059 /* setup_descs()
1060 *
1061 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1062 * with a DMA buffer.
1063 *
1064 * Only pipe numbers 0-15 can be used in this mode.
1065 *
1066 * This function takes a stream number pointing to a data buffer,
1067 * and work by building chains of descriptors which identify the
1068 * data buffers. Buffers too large for a single descriptor will
1069 * be spread across multiple descriptors.
1070 *
1071 * All descriptors create a ring buffer.
1072 *
1073 * Lock must be held before calling this.
1074 */
1075 static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
1076 {
1077 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1078 __u32 dvma_buffer;
1079 int desc;
1080 int len;
1081 int first_desc = -1;
1082 int last_desc = -1;
1083
1084 if (info->pipe < 0 || info->pipe > 15) {
1085 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1086 return -2;
1087 }
1088
1089 if (dbri->pipes[info->pipe].sdp == 0) {
1090 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1091 info->pipe);
1092 return -2;
1093 }
1094
1095 dvma_buffer = info->dvma_buffer;
1096 len = info->size;
1097
1098 if (streamno == DBRI_PLAY) {
1099 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1100 printk(KERN_ERR "DBRI: setup_descs: "
1101 "Called on receive pipe %d\n", info->pipe);
1102 return -2;
1103 }
1104 } else {
1105 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1106 printk(KERN_ERR
1107 "DBRI: setup_descs: Called on transmit pipe %d\n",
1108 info->pipe);
1109 return -2;
1110 }
1111 /* Should be able to queue multiple buffers
1112 * to receive on a pipe
1113 */
1114 if (pipe_active(dbri, info->pipe)) {
1115 printk(KERN_ERR "DBRI: recv_on_pipe: "
1116 "Called on active pipe %d\n", info->pipe);
1117 return -2;
1118 }
1119
1120 /* Make sure buffer size is multiple of four */
1121 len &= ~3;
1122 }
1123
1124 /* Free descriptors if pipe has any */
1125 desc = dbri->pipes[info->pipe].first_desc;
1126 if (desc >= 0)
1127 do {
1128 dbri->dma->desc[desc].ba = 0;
1129 dbri->dma->desc[desc].nda = 0;
1130 desc = dbri->next_desc[desc];
1131 } while (desc != -1 &&
1132 desc != dbri->pipes[info->pipe].first_desc);
1133
1134 dbri->pipes[info->pipe].desc = -1;
1135 dbri->pipes[info->pipe].first_desc = -1;
1136
1137 desc = 0;
1138 while (len > 0) {
1139 int mylen;
1140
1141 for (; desc < DBRI_NO_DESCS; desc++) {
1142 if (!dbri->dma->desc[desc].ba)
1143 break;
1144 }
1145
1146 if (desc == DBRI_NO_DESCS) {
1147 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1148 return -1;
1149 }
1150
1151 if (len > DBRI_TD_MAXCNT)
1152 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1153 else
1154 mylen = len;
1155
1156 if (mylen > period)
1157 mylen = period;
1158
1159 dbri->next_desc[desc] = -1;
1160 dbri->dma->desc[desc].ba = dvma_buffer;
1161 dbri->dma->desc[desc].nda = 0;
1162
1163 if (streamno == DBRI_PLAY) {
1164 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1165 dbri->dma->desc[desc].word4 = 0;
1166 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
1167 } else {
1168 dbri->dma->desc[desc].word1 = 0;
1169 dbri->dma->desc[desc].word4 =
1170 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1171 }
1172
1173 if (first_desc == -1)
1174 first_desc = desc;
1175 else {
1176 dbri->next_desc[last_desc] = desc;
1177 dbri->dma->desc[last_desc].nda =
1178 dbri->dma_dvma + dbri_dma_off(desc, desc);
1179 }
1180
1181 last_desc = desc;
1182 dvma_buffer += mylen;
1183 len -= mylen;
1184 }
1185
1186 if (first_desc == -1 || last_desc == -1) {
1187 printk(KERN_ERR "DBRI: setup_descs: "
1188 " Not enough descriptors available\n");
1189 return -1;
1190 }
1191
1192 dbri->dma->desc[last_desc].nda =
1193 dbri->dma_dvma + dbri_dma_off(desc, first_desc);
1194 dbri->next_desc[last_desc] = first_desc;
1195 dbri->pipes[info->pipe].first_desc = first_desc;
1196 dbri->pipes[info->pipe].desc = first_desc;
1197
1198 #ifdef DBRI_DEBUG
1199 for (desc = first_desc; desc != -1;) {
1200 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1201 desc,
1202 dbri->dma->desc[desc].word1,
1203 dbri->dma->desc[desc].ba,
1204 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1205 desc = dbri->next_desc[desc];
1206 if (desc == first_desc)
1207 break;
1208 }
1209 #endif
1210 return 0;
1211 }
1212
1213 /*
1214 ****************************************************************************
1215 ************************** DBRI - CHI interface ****************************
1216 ****************************************************************************
1217
1218 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1219 multiplexed serial interface which the DBRI can operate in either master
1220 (give clock/frame sync) or slave (take clock/frame sync) mode.
1221
1222 */
1223
1224 enum master_or_slave { CHImaster, CHIslave };
1225
1226 /*
1227 * Lock must not be held before calling it.
1228 */
1229 static void reset_chi(struct snd_dbri *dbri,
1230 enum master_or_slave master_or_slave,
1231 int bits_per_frame)
1232 {
1233 s32 *cmd;
1234 int val;
1235
1236 /* Set CHI Anchor: Pipe 16 */
1237
1238 cmd = dbri_cmdlock(dbri, 4);
1239 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
1240 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1241 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1242 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1243 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1244 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1245 dbri_cmdsend(dbri, cmd, 4);
1246
1247 dbri->pipes[16].sdp = 1;
1248 dbri->pipes[16].nextpipe = 16;
1249
1250 cmd = dbri_cmdlock(dbri, 4);
1251
1252 if (master_or_slave == CHIslave) {
1253 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1254 *
1255 * CHICM = 0 (slave mode, 8 kHz frame rate)
1256 * IR = give immediate CHI status interrupt
1257 * EN = give CHI status interrupt upon change
1258 */
1259 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1260 } else {
1261 /* Setup DBRI for CHI Master - generate clock, FS
1262 *
1263 * BPF = bits per 8 kHz frame
1264 * 12.288 MHz / CHICM_divisor = clock rate
1265 * FD = 1 - drive CHIFS on rising edge of CHICK
1266 */
1267 int clockrate = bits_per_frame * 8;
1268 int divisor = 12288 / clockrate;
1269
1270 if (divisor > 255 || divisor * clockrate != 12288)
1271 printk(KERN_ERR "DBRI: illegal bits_per_frame "
1272 "in setup_chi\n");
1273
1274 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1275 | D_CHI_BPF(bits_per_frame));
1276 }
1277
1278 dbri->chi_bpf = bits_per_frame;
1279
1280 /* CHI Data Mode
1281 *
1282 * RCE = 0 - receive on falling edge of CHICK
1283 * XCE = 1 - transmit on rising edge of CHICK
1284 * XEN = 1 - enable transmitter
1285 * REN = 1 - enable receiver
1286 */
1287
1288 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1289 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1290 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1291
1292 dbri_cmdsend(dbri, cmd, 4);
1293 }
1294
1295 /*
1296 ****************************************************************************
1297 *********************** CS4215 audio codec management **********************
1298 ****************************************************************************
1299
1300 In the standard SPARC audio configuration, the CS4215 codec is attached
1301 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1302
1303 * Lock must not be held before calling it.
1304
1305 */
1306 static __devinit void cs4215_setup_pipes(struct snd_dbri *dbri)
1307 {
1308 unsigned long flags;
1309
1310 spin_lock_irqsave(&dbri->lock, flags);
1311 /*
1312 * Data mode:
1313 * Pipe 4: Send timeslots 1-4 (audio data)
1314 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1315 * Pipe 6: Receive timeslots 1-4 (audio data)
1316 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1317 * interrupt, and the rest of the data (slot 5 and 8) is
1318 * not relevant for us (only for doublechecking).
1319 *
1320 * Control mode:
1321 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1322 * Pipe 18: Receive timeslot 1 (clb).
1323 * Pipe 19: Receive timeslot 7 (version).
1324 */
1325
1326 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1327 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1328 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1329 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1330
1331 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1332 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1333 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1334 spin_unlock_irqrestore(&dbri->lock, flags);
1335
1336 dbri_cmdwait(dbri);
1337 }
1338
1339 static __devinit int cs4215_init_data(struct cs4215 *mm)
1340 {
1341 /*
1342 * No action, memory resetting only.
1343 *
1344 * Data Time Slot 5-8
1345 * Speaker,Line and Headphone enable. Gain set to the half.
1346 * Input is mike.
1347 */
1348 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1349 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1350 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1351 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1352
1353 /*
1354 * Control Time Slot 1-4
1355 * 0: Default I/O voltage scale
1356 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1357 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1358 * 3: Tests disabled
1359 */
1360 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1361 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1362 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1363 mm->ctrl[3] = 0;
1364
1365 mm->status = 0;
1366 mm->version = 0xff;
1367 mm->precision = 8; /* For ULAW */
1368 mm->channels = 1;
1369
1370 return 0;
1371 }
1372
1373 static void cs4215_setdata(struct snd_dbri *dbri, int muted)
1374 {
1375 if (muted) {
1376 dbri->mm.data[0] |= 63;
1377 dbri->mm.data[1] |= 63;
1378 dbri->mm.data[2] &= ~15;
1379 dbri->mm.data[3] &= ~15;
1380 } else {
1381 /* Start by setting the playback attenuation. */
1382 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1383 int left_gain = info->left_gain & 0x3f;
1384 int right_gain = info->right_gain & 0x3f;
1385
1386 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1387 dbri->mm.data[1] &= ~0x3f;
1388 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1389 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1390
1391 /* Now set the recording gain. */
1392 info = &dbri->stream_info[DBRI_REC];
1393 left_gain = info->left_gain & 0xf;
1394 right_gain = info->right_gain & 0xf;
1395 dbri->mm.data[2] |= CS4215_LG(left_gain);
1396 dbri->mm.data[3] |= CS4215_RG(right_gain);
1397 }
1398
1399 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1400 }
1401
1402 /*
1403 * Set the CS4215 to data mode.
1404 */
1405 static void cs4215_open(struct snd_dbri *dbri)
1406 {
1407 int data_width;
1408 u32 tmp;
1409 unsigned long flags;
1410
1411 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1412 dbri->mm.channels, dbri->mm.precision);
1413
1414 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1415 * to make sure this takes. This avoids clicking noises.
1416 */
1417
1418 cs4215_setdata(dbri, 1);
1419 udelay(125);
1420
1421 /*
1422 * Data mode:
1423 * Pipe 4: Send timeslots 1-4 (audio data)
1424 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1425 * Pipe 6: Receive timeslots 1-4 (audio data)
1426 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1427 * interrupt, and the rest of the data (slot 5 and 8) is
1428 * not relevant for us (only for doublechecking).
1429 *
1430 * Just like in control mode, the time slots are all offset by eight
1431 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1432 * even if it's the CHI master. Don't ask me...
1433 */
1434 spin_lock_irqsave(&dbri->lock, flags);
1435 tmp = sbus_readl(dbri->regs + REG0);
1436 tmp &= ~(D_C); /* Disable CHI */
1437 sbus_writel(tmp, dbri->regs + REG0);
1438
1439 /* Switch CS4215 to data mode - set PIO3 to 1 */
1440 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1441 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1442
1443 reset_chi(dbri, CHIslave, 128);
1444
1445 /* Note: this next doesn't work for 8-bit stereo, because the two
1446 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1447 * (See CS4215 datasheet Fig 15)
1448 *
1449 * DBRI non-contiguous mode would be required to make this work.
1450 */
1451 data_width = dbri->mm.channels * dbri->mm.precision;
1452
1453 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1454 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1455 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1456 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1457
1458 /* FIXME: enable CHI after _setdata? */
1459 tmp = sbus_readl(dbri->regs + REG0);
1460 tmp |= D_C; /* Enable CHI */
1461 sbus_writel(tmp, dbri->regs + REG0);
1462 spin_unlock_irqrestore(&dbri->lock, flags);
1463
1464 cs4215_setdata(dbri, 0);
1465 }
1466
1467 /*
1468 * Send the control information (i.e. audio format)
1469 */
1470 static int cs4215_setctrl(struct snd_dbri *dbri)
1471 {
1472 int i, val;
1473 u32 tmp;
1474 unsigned long flags;
1475
1476 /* FIXME - let the CPU do something useful during these delays */
1477
1478 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1479 * to make sure this takes. This avoids clicking noises.
1480 */
1481 cs4215_setdata(dbri, 1);
1482 udelay(125);
1483
1484 /*
1485 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1486 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1487 */
1488 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1489 sbus_writel(val, dbri->regs + REG2);
1490 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1491 udelay(34);
1492
1493 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1494 * operate as CHI master, supplying clocking and frame synchronization.
1495 *
1496 * In Data mode, however, the CS4215 must be CHI master to insure
1497 * that its data stream is synchronous with its codec.
1498 *
1499 * The upshot of all this? We start by putting the DBRI into master
1500 * mode, program the CS4215 in Control mode, then switch the CS4215
1501 * into Data mode and put the DBRI into slave mode. Various timing
1502 * requirements must be observed along the way.
1503 *
1504 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1505 * others?), the addressing of the CS4215's time slots is
1506 * offset by eight bits, so we add eight to all the "cycle"
1507 * values in the Define Time Slot (DTS) commands. This is
1508 * done in hardware by a TI 248 that delays the DBRI->4215
1509 * frame sync signal by eight clock cycles. Anybody know why?
1510 */
1511 spin_lock_irqsave(&dbri->lock, flags);
1512 tmp = sbus_readl(dbri->regs + REG0);
1513 tmp &= ~D_C; /* Disable CHI */
1514 sbus_writel(tmp, dbri->regs + REG0);
1515
1516 reset_chi(dbri, CHImaster, 128);
1517
1518 /*
1519 * Control mode:
1520 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
1521 * Pipe 18: Receive timeslot 1 (clb).
1522 * Pipe 19: Receive timeslot 7 (version).
1523 */
1524
1525 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1526 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1527 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1528 spin_unlock_irqrestore(&dbri->lock, flags);
1529
1530 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1531 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1532 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1533
1534 spin_lock_irqsave(&dbri->lock, flags);
1535 tmp = sbus_readl(dbri->regs + REG0);
1536 tmp |= D_C; /* Enable CHI */
1537 sbus_writel(tmp, dbri->regs + REG0);
1538 spin_unlock_irqrestore(&dbri->lock, flags);
1539
1540 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1541 msleep_interruptible(1);
1542
1543 if (i == 0) {
1544 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1545 dbri->mm.status);
1546 return -1;
1547 }
1548
1549 /* Disable changes to our copy of the version number, as we are about
1550 * to leave control mode.
1551 */
1552 recv_fixed(dbri, 19, NULL);
1553
1554 /* Terminate CS4215 control mode - data sheet says
1555 * "Set CLB=1 and send two more frames of valid control info"
1556 */
1557 dbri->mm.ctrl[0] |= CS4215_CLB;
1558 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1559
1560 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1561 udelay(250);
1562
1563 cs4215_setdata(dbri, 0);
1564
1565 return 0;
1566 }
1567
1568 /*
1569 * Setup the codec with the sampling rate, audio format and number of
1570 * channels.
1571 * As part of the process we resend the settings for the data
1572 * timeslots as well.
1573 */
1574 static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
1575 snd_pcm_format_t format, unsigned int channels)
1576 {
1577 int freq_idx;
1578 int ret = 0;
1579
1580 /* Lookup index for this rate */
1581 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1582 if (CS4215_FREQ[freq_idx].freq == rate)
1583 break;
1584 }
1585 if (CS4215_FREQ[freq_idx].freq != rate) {
1586 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1587 return -1;
1588 }
1589
1590 switch (format) {
1591 case SNDRV_PCM_FORMAT_MU_LAW:
1592 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1593 dbri->mm.precision = 8;
1594 break;
1595 case SNDRV_PCM_FORMAT_A_LAW:
1596 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1597 dbri->mm.precision = 8;
1598 break;
1599 case SNDRV_PCM_FORMAT_U8:
1600 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1601 dbri->mm.precision = 8;
1602 break;
1603 case SNDRV_PCM_FORMAT_S16_BE:
1604 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1605 dbri->mm.precision = 16;
1606 break;
1607 default:
1608 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1609 return -1;
1610 }
1611
1612 /* Add rate parameters */
1613 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1614 dbri->mm.ctrl[2] = CS4215_XCLK |
1615 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1616
1617 dbri->mm.channels = channels;
1618 if (channels == 2)
1619 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1620
1621 ret = cs4215_setctrl(dbri);
1622 if (ret == 0)
1623 cs4215_open(dbri); /* set codec to data mode */
1624
1625 return ret;
1626 }
1627
1628 /*
1629 *
1630 */
1631 static __devinit int cs4215_init(struct snd_dbri *dbri)
1632 {
1633 u32 reg2 = sbus_readl(dbri->regs + REG2);
1634 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1635
1636 /* Look for the cs4215 chips */
1637 if (reg2 & D_PIO2) {
1638 dprintk(D_MM, "Onboard CS4215 detected\n");
1639 dbri->mm.onboard = 1;
1640 }
1641 if (reg2 & D_PIO0) {
1642 dprintk(D_MM, "Speakerbox detected\n");
1643 dbri->mm.onboard = 0;
1644
1645 if (reg2 & D_PIO2) {
1646 printk(KERN_INFO "DBRI: Using speakerbox / "
1647 "ignoring onboard mmcodec.\n");
1648 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1649 }
1650 }
1651
1652 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1653 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1654 return -EIO;
1655 }
1656
1657 cs4215_setup_pipes(dbri);
1658 cs4215_init_data(&dbri->mm);
1659
1660 /* Enable capture of the status & version timeslots. */
1661 recv_fixed(dbri, 18, &dbri->mm.status);
1662 recv_fixed(dbri, 19, &dbri->mm.version);
1663
1664 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1665 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1666 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1667 dbri->mm.offset);
1668 return -EIO;
1669 }
1670 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1671
1672 return 0;
1673 }
1674
1675 /*
1676 ****************************************************************************
1677 *************************** DBRI interrupt handler *************************
1678 ****************************************************************************
1679
1680 The DBRI communicates with the CPU mainly via a circular interrupt
1681 buffer. When an interrupt is signaled, the CPU walks through the
1682 buffer and calls dbri_process_one_interrupt() for each interrupt word.
1683 Complicated interrupts are handled by dedicated functions (which
1684 appear first in this file). Any pending interrupts can be serviced by
1685 calling dbri_process_interrupt_buffer(), which works even if the CPU's
1686 interrupts are disabled.
1687
1688 */
1689
1690 /* xmit_descs()
1691 *
1692 * Starts transmitting the current TD's for recording/playing.
1693 * For playback, ALSA has filled the DMA memory with new data (we hope).
1694 */
1695 static void xmit_descs(struct snd_dbri *dbri)
1696 {
1697 struct dbri_streaminfo *info;
1698 s32 *cmd;
1699 unsigned long flags;
1700 int first_td;
1701
1702 if (dbri == NULL)
1703 return; /* Disabled */
1704
1705 info = &dbri->stream_info[DBRI_REC];
1706 spin_lock_irqsave(&dbri->lock, flags);
1707
1708 if (info->pipe >= 0) {
1709 first_td = dbri->pipes[info->pipe].first_desc;
1710
1711 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1712
1713 /* Stream could be closed by the time we run. */
1714 if (first_td >= 0) {
1715 cmd = dbri_cmdlock(dbri, 2);
1716 *(cmd++) = DBRI_CMD(D_SDP, 0,
1717 dbri->pipes[info->pipe].sdp
1718 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1719 *(cmd++) = dbri->dma_dvma +
1720 dbri_dma_off(desc, first_td);
1721 dbri_cmdsend(dbri, cmd, 2);
1722
1723 /* Reset our admin of the pipe. */
1724 dbri->pipes[info->pipe].desc = first_td;
1725 }
1726 }
1727
1728 info = &dbri->stream_info[DBRI_PLAY];
1729
1730 if (info->pipe >= 0) {
1731 first_td = dbri->pipes[info->pipe].first_desc;
1732
1733 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1734
1735 /* Stream could be closed by the time we run. */
1736 if (first_td >= 0) {
1737 cmd = dbri_cmdlock(dbri, 2);
1738 *(cmd++) = DBRI_CMD(D_SDP, 0,
1739 dbri->pipes[info->pipe].sdp
1740 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1741 *(cmd++) = dbri->dma_dvma +
1742 dbri_dma_off(desc, first_td);
1743 dbri_cmdsend(dbri, cmd, 2);
1744
1745 /* Reset our admin of the pipe. */
1746 dbri->pipes[info->pipe].desc = first_td;
1747 }
1748 }
1749
1750 spin_unlock_irqrestore(&dbri->lock, flags);
1751 }
1752
1753 /* transmission_complete_intr()
1754 *
1755 * Called by main interrupt handler when DBRI signals transmission complete
1756 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1757 *
1758 * Walks through the pipe's list of transmit buffer descriptors and marks
1759 * them as available. Stops when the first descriptor is found without
1760 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1761 *
1762 * The DMA buffers are not released. They form a ring buffer and
1763 * they are filled by ALSA while others are transmitted by DMA.
1764 *
1765 */
1766
1767 static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
1768 {
1769 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1770 int td = dbri->pipes[pipe].desc;
1771 int status;
1772
1773 while (td >= 0) {
1774 if (td >= DBRI_NO_DESCS) {
1775 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1776 return;
1777 }
1778
1779 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1780 if (!(status & DBRI_TD_TBC))
1781 break;
1782
1783 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1784
1785 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1786 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1787
1788 td = dbri->next_desc[td];
1789 dbri->pipes[pipe].desc = td;
1790 }
1791
1792 /* Notify ALSA */
1793 spin_unlock(&dbri->lock);
1794 snd_pcm_period_elapsed(info->substream);
1795 spin_lock(&dbri->lock);
1796 }
1797
1798 static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
1799 {
1800 struct dbri_streaminfo *info;
1801 int rd = dbri->pipes[pipe].desc;
1802 s32 status;
1803
1804 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1805 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1806 return;
1807 }
1808
1809 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1810 status = dbri->dma->desc[rd].word1;
1811 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1812
1813 info = &dbri->stream_info[DBRI_REC];
1814 info->offset += DBRI_RD_CNT(status);
1815
1816 /* FIXME: Check status */
1817
1818 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1819 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1820
1821 /* Notify ALSA */
1822 spin_unlock(&dbri->lock);
1823 snd_pcm_period_elapsed(info->substream);
1824 spin_lock(&dbri->lock);
1825 }
1826
1827 static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
1828 {
1829 int val = D_INTR_GETVAL(x);
1830 int channel = D_INTR_GETCHAN(x);
1831 int command = D_INTR_GETCMD(x);
1832 int code = D_INTR_GETCODE(x);
1833 #ifdef DBRI_DEBUG
1834 int rval = D_INTR_GETRVAL(x);
1835 #endif
1836
1837 if (channel == D_INTR_CMD) {
1838 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1839 cmds[command], val);
1840 } else {
1841 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1842 channel, code, rval);
1843 }
1844
1845 switch (code) {
1846 case D_INTR_CMDI:
1847 if (command != D_WAIT)
1848 printk(KERN_ERR "DBRI: Command read interrupt\n");
1849 break;
1850 case D_INTR_BRDY:
1851 reception_complete_intr(dbri, channel);
1852 break;
1853 case D_INTR_XCMP:
1854 case D_INTR_MINT:
1855 transmission_complete_intr(dbri, channel);
1856 break;
1857 case D_INTR_UNDR:
1858 /* UNDR - Transmission underrun
1859 * resend SDP command with clear pipe bit (C) set
1860 */
1861 {
1862 /* FIXME: do something useful in case of underrun */
1863 printk(KERN_ERR "DBRI: Underrun error\n");
1864 #if 0
1865 s32 *cmd;
1866 int pipe = channel;
1867 int td = dbri->pipes[pipe].desc;
1868
1869 dbri->dma->desc[td].word4 = 0;
1870 cmd = dbri_cmdlock(dbri, NoGetLock);
1871 *(cmd++) = DBRI_CMD(D_SDP, 0,
1872 dbri->pipes[pipe].sdp
1873 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1874 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1875 dbri_cmdsend(dbri, cmd);
1876 #endif
1877 }
1878 break;
1879 case D_INTR_FXDT:
1880 /* FXDT - Fixed data change */
1881 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1882 val = reverse_bytes(val, dbri->pipes[channel].length);
1883
1884 if (dbri->pipes[channel].recv_fixed_ptr)
1885 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1886 break;
1887 default:
1888 if (channel != D_INTR_CMD)
1889 printk(KERN_WARNING
1890 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1891 }
1892 }
1893
1894 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1895 * buffer until it finds a zero word (indicating nothing more to do
1896 * right now). Non-zero words require processing and are handed off
1897 * to dbri_process_one_interrupt AFTER advancing the pointer.
1898 */
1899 static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
1900 {
1901 s32 x;
1902
1903 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1904 dbri->dma->intr[dbri->dbri_irqp] = 0;
1905 dbri->dbri_irqp++;
1906 if (dbri->dbri_irqp == DBRI_INT_BLK)
1907 dbri->dbri_irqp = 1;
1908
1909 dbri_process_one_interrupt(dbri, x);
1910 }
1911 }
1912
1913 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
1914 {
1915 struct snd_dbri *dbri = dev_id;
1916 static int errcnt = 0;
1917 int x;
1918
1919 if (dbri == NULL)
1920 return IRQ_NONE;
1921 spin_lock(&dbri->lock);
1922
1923 /*
1924 * Read it, so the interrupt goes away.
1925 */
1926 x = sbus_readl(dbri->regs + REG1);
1927
1928 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1929 u32 tmp;
1930
1931 if (x & D_MRR)
1932 printk(KERN_ERR
1933 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1934 x);
1935 if (x & D_MLE)
1936 printk(KERN_ERR
1937 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1938 x);
1939 if (x & D_LBG)
1940 printk(KERN_ERR
1941 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1942 if (x & D_MBE)
1943 printk(KERN_ERR
1944 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1945
1946 /* Some of these SBus errors cause the chip's SBus circuitry
1947 * to be disabled, so just re-enable and try to keep going.
1948 *
1949 * The only one I've seen is MRR, which will be triggered
1950 * if you let a transmit pipe underrun, then try to CDP it.
1951 *
1952 * If these things persist, we reset the chip.
1953 */
1954 if ((++errcnt) % 10 == 0) {
1955 dprintk(D_INT, "Interrupt errors exceeded.\n");
1956 dbri_reset(dbri);
1957 } else {
1958 tmp = sbus_readl(dbri->regs + REG0);
1959 tmp &= ~(D_D);
1960 sbus_writel(tmp, dbri->regs + REG0);
1961 }
1962 }
1963
1964 dbri_process_interrupt_buffer(dbri);
1965
1966 spin_unlock(&dbri->lock);
1967
1968 return IRQ_HANDLED;
1969 }
1970
1971 /****************************************************************************
1972 PCM Interface
1973 ****************************************************************************/
1974 static struct snd_pcm_hardware snd_dbri_pcm_hw = {
1975 .info = SNDRV_PCM_INFO_MMAP |
1976 SNDRV_PCM_INFO_INTERLEAVED |
1977 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1978 SNDRV_PCM_INFO_MMAP_VALID,
1979 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1980 SNDRV_PCM_FMTBIT_A_LAW |
1981 SNDRV_PCM_FMTBIT_U8 |
1982 SNDRV_PCM_FMTBIT_S16_BE,
1983 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
1984 .rate_min = 5512,
1985 .rate_max = 48000,
1986 .channels_min = 1,
1987 .channels_max = 2,
1988 .buffer_bytes_max = 64 * 1024,
1989 .period_bytes_min = 1,
1990 .period_bytes_max = DBRI_TD_MAXCNT,
1991 .periods_min = 1,
1992 .periods_max = 1024,
1993 };
1994
1995 static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
1996 struct snd_pcm_hw_rule *rule)
1997 {
1998 struct snd_interval *c = hw_param_interval(params,
1999 SNDRV_PCM_HW_PARAM_CHANNELS);
2000 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2001 struct snd_mask fmt;
2002
2003 snd_mask_any(&fmt);
2004 if (c->min > 1) {
2005 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
2006 return snd_mask_refine(f, &fmt);
2007 }
2008 return 0;
2009 }
2010
2011 static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
2012 struct snd_pcm_hw_rule *rule)
2013 {
2014 struct snd_interval *c = hw_param_interval(params,
2015 SNDRV_PCM_HW_PARAM_CHANNELS);
2016 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2017 struct snd_interval ch;
2018
2019 snd_interval_any(&ch);
2020 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
2021 ch.min = 1;
2022 ch.max = 1;
2023 ch.integer = 1;
2024 return snd_interval_refine(c, &ch);
2025 }
2026 return 0;
2027 }
2028
2029 static int snd_dbri_open(struct snd_pcm_substream *substream)
2030 {
2031 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2032 struct snd_pcm_runtime *runtime = substream->runtime;
2033 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2034 unsigned long flags;
2035
2036 dprintk(D_USR, "open audio output.\n");
2037 runtime->hw = snd_dbri_pcm_hw;
2038
2039 spin_lock_irqsave(&dbri->lock, flags);
2040 info->substream = substream;
2041 info->offset = 0;
2042 info->dvma_buffer = 0;
2043 info->pipe = -1;
2044 spin_unlock_irqrestore(&dbri->lock, flags);
2045
2046 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
2047 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
2048 -1);
2049 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2050 snd_hw_rule_channels, NULL,
2051 SNDRV_PCM_HW_PARAM_CHANNELS,
2052 -1);
2053
2054 cs4215_open(dbri);
2055
2056 return 0;
2057 }
2058
2059 static int snd_dbri_close(struct snd_pcm_substream *substream)
2060 {
2061 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2062 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2063
2064 dprintk(D_USR, "close audio output.\n");
2065 info->substream = NULL;
2066 info->offset = 0;
2067
2068 return 0;
2069 }
2070
2071 static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2072 struct snd_pcm_hw_params *hw_params)
2073 {
2074 struct snd_pcm_runtime *runtime = substream->runtime;
2075 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2076 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2077 int direction;
2078 int ret;
2079
2080 /* set sampling rate, audio format and number of channels */
2081 ret = cs4215_prepare(dbri, params_rate(hw_params),
2082 params_format(hw_params),
2083 params_channels(hw_params));
2084 if (ret != 0)
2085 return ret;
2086
2087 if ((ret = snd_pcm_lib_malloc_pages(substream,
2088 params_buffer_bytes(hw_params))) < 0) {
2089 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2090 return ret;
2091 }
2092
2093 /* hw_params can get called multiple times. Only map the DMA once.
2094 */
2095 if (info->dvma_buffer == 0) {
2096 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2097 direction = SBUS_DMA_TODEVICE;
2098 else
2099 direction = SBUS_DMA_FROMDEVICE;
2100
2101 info->dvma_buffer = sbus_map_single(dbri->sdev,
2102 runtime->dma_area,
2103 params_buffer_bytes(hw_params),
2104 direction);
2105 }
2106
2107 direction = params_buffer_bytes(hw_params);
2108 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2109 direction, info->dvma_buffer);
2110 return 0;
2111 }
2112
2113 static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2114 {
2115 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2116 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2117 int direction;
2118
2119 dprintk(D_USR, "hw_free.\n");
2120
2121 /* hw_free can get called multiple times. Only unmap the DMA once.
2122 */
2123 if (info->dvma_buffer) {
2124 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2125 direction = SBUS_DMA_TODEVICE;
2126 else
2127 direction = SBUS_DMA_FROMDEVICE;
2128
2129 sbus_unmap_single(dbri->sdev, info->dvma_buffer,
2130 substream->runtime->buffer_size, direction);
2131 info->dvma_buffer = 0;
2132 }
2133 if (info->pipe != -1) {
2134 reset_pipe(dbri, info->pipe);
2135 info->pipe = -1;
2136 }
2137
2138 return snd_pcm_lib_free_pages(substream);
2139 }
2140
2141 static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2142 {
2143 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2144 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2145 int ret;
2146
2147 info->size = snd_pcm_lib_buffer_bytes(substream);
2148 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2149 info->pipe = 4; /* Send pipe */
2150 else
2151 info->pipe = 6; /* Receive pipe */
2152
2153 spin_lock_irq(&dbri->lock);
2154 info->offset = 0;
2155
2156 /* Setup the all the transmit/receive descriptors to cover the
2157 * whole DMA buffer.
2158 */
2159 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2160 snd_pcm_lib_period_bytes(substream));
2161
2162 spin_unlock_irq(&dbri->lock);
2163
2164 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2165 return ret;
2166 }
2167
2168 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2169 {
2170 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2171 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2172 int ret = 0;
2173
2174 switch (cmd) {
2175 case SNDRV_PCM_TRIGGER_START:
2176 dprintk(D_USR, "start audio, period is %d bytes\n",
2177 (int)snd_pcm_lib_period_bytes(substream));
2178 /* Re-submit the TDs. */
2179 xmit_descs(dbri);
2180 break;
2181 case SNDRV_PCM_TRIGGER_STOP:
2182 dprintk(D_USR, "stop audio.\n");
2183 reset_pipe(dbri, info->pipe);
2184 break;
2185 default:
2186 ret = -EINVAL;
2187 }
2188
2189 return ret;
2190 }
2191
2192 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2193 {
2194 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2195 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2196 snd_pcm_uframes_t ret;
2197
2198 ret = bytes_to_frames(substream->runtime, info->offset)
2199 % substream->runtime->buffer_size;
2200 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2201 ret, substream->runtime->buffer_size);
2202 return ret;
2203 }
2204
2205 static struct snd_pcm_ops snd_dbri_ops = {
2206 .open = snd_dbri_open,
2207 .close = snd_dbri_close,
2208 .ioctl = snd_pcm_lib_ioctl,
2209 .hw_params = snd_dbri_hw_params,
2210 .hw_free = snd_dbri_hw_free,
2211 .prepare = snd_dbri_prepare,
2212 .trigger = snd_dbri_trigger,
2213 .pointer = snd_dbri_pointer,
2214 };
2215
2216 static int __devinit snd_dbri_pcm(struct snd_card *card)
2217 {
2218 struct snd_pcm *pcm;
2219 int err;
2220
2221 if ((err = snd_pcm_new(card,
2222 /* ID */ "sun_dbri",
2223 /* device */ 0,
2224 /* playback count */ 1,
2225 /* capture count */ 1, &pcm)) < 0)
2226 return err;
2227 snd_assert(pcm != NULL, return -EINVAL);
2228
2229 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2230 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2231
2232 pcm->private_data = card->private_data;
2233 pcm->info_flags = 0;
2234 strcpy(pcm->name, card->shortname);
2235
2236 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2237 SNDRV_DMA_TYPE_CONTINUOUS,
2238 snd_dma_continuous_data(GFP_KERNEL),
2239 64 * 1024, 64 * 1024)) < 0)
2240 return err;
2241
2242 return 0;
2243 }
2244
2245 /*****************************************************************************
2246 Mixer interface
2247 *****************************************************************************/
2248
2249 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2250 struct snd_ctl_elem_info *uinfo)
2251 {
2252 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2253 uinfo->count = 2;
2254 uinfo->value.integer.min = 0;
2255 if (kcontrol->private_value == DBRI_PLAY)
2256 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2257 else
2258 uinfo->value.integer.max = DBRI_MAX_GAIN;
2259 return 0;
2260 }
2261
2262 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2263 struct snd_ctl_elem_value *ucontrol)
2264 {
2265 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2266 struct dbri_streaminfo *info;
2267 snd_assert(dbri != NULL, return -EINVAL);
2268 info = &dbri->stream_info[kcontrol->private_value];
2269 snd_assert(info != NULL, return -EINVAL);
2270
2271 ucontrol->value.integer.value[0] = info->left_gain;
2272 ucontrol->value.integer.value[1] = info->right_gain;
2273 return 0;
2274 }
2275
2276 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2277 struct snd_ctl_elem_value *ucontrol)
2278 {
2279 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2280 struct dbri_streaminfo *info =
2281 &dbri->stream_info[kcontrol->private_value];
2282 int changed = 0;
2283
2284 if (info->left_gain != ucontrol->value.integer.value[0]) {
2285 info->left_gain = ucontrol->value.integer.value[0];
2286 changed = 1;
2287 }
2288 if (info->right_gain != ucontrol->value.integer.value[1]) {
2289 info->right_gain = ucontrol->value.integer.value[1];
2290 changed = 1;
2291 }
2292 if (changed) {
2293 /* First mute outputs, and wait 1/8000 sec (125 us)
2294 * to make sure this takes. This avoids clicking noises.
2295 */
2296 cs4215_setdata(dbri, 1);
2297 udelay(125);
2298 cs4215_setdata(dbri, 0);
2299 }
2300 return changed;
2301 }
2302
2303 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2304 struct snd_ctl_elem_info *uinfo)
2305 {
2306 int mask = (kcontrol->private_value >> 16) & 0xff;
2307
2308 uinfo->type = (mask == 1) ?
2309 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2310 uinfo->count = 1;
2311 uinfo->value.integer.min = 0;
2312 uinfo->value.integer.max = mask;
2313 return 0;
2314 }
2315
2316 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2317 struct snd_ctl_elem_value *ucontrol)
2318 {
2319 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2320 int elem = kcontrol->private_value & 0xff;
2321 int shift = (kcontrol->private_value >> 8) & 0xff;
2322 int mask = (kcontrol->private_value >> 16) & 0xff;
2323 int invert = (kcontrol->private_value >> 24) & 1;
2324 snd_assert(dbri != NULL, return -EINVAL);
2325
2326 if (elem < 4)
2327 ucontrol->value.integer.value[0] =
2328 (dbri->mm.data[elem] >> shift) & mask;
2329 else
2330 ucontrol->value.integer.value[0] =
2331 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2332
2333 if (invert == 1)
2334 ucontrol->value.integer.value[0] =
2335 mask - ucontrol->value.integer.value[0];
2336 return 0;
2337 }
2338
2339 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2340 struct snd_ctl_elem_value *ucontrol)
2341 {
2342 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2343 int elem = kcontrol->private_value & 0xff;
2344 int shift = (kcontrol->private_value >> 8) & 0xff;
2345 int mask = (kcontrol->private_value >> 16) & 0xff;
2346 int invert = (kcontrol->private_value >> 24) & 1;
2347 int changed = 0;
2348 unsigned short val;
2349 snd_assert(dbri != NULL, return -EINVAL);
2350
2351 val = (ucontrol->value.integer.value[0] & mask);
2352 if (invert == 1)
2353 val = mask - val;
2354 val <<= shift;
2355
2356 if (elem < 4) {
2357 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2358 ~(mask << shift)) | val;
2359 changed = (val != dbri->mm.data[elem]);
2360 } else {
2361 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2362 ~(mask << shift)) | val;
2363 changed = (val != dbri->mm.ctrl[elem - 4]);
2364 }
2365
2366 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2367 "mixer-value=%ld, mm-value=0x%x\n",
2368 mask, changed, ucontrol->value.integer.value[0],
2369 dbri->mm.data[elem & 3]);
2370
2371 if (changed) {
2372 /* First mute outputs, and wait 1/8000 sec (125 us)
2373 * to make sure this takes. This avoids clicking noises.
2374 */
2375 cs4215_setdata(dbri, 1);
2376 udelay(125);
2377 cs4215_setdata(dbri, 0);
2378 }
2379 return changed;
2380 }
2381
2382 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2383 timeslots. Shift is the bit offset in the timeslot, mask defines the
2384 number of bits. invert is a boolean for use with attenuation.
2385 */
2386 #define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2387 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
2388 .info = snd_cs4215_info_single, \
2389 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2390 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \
2391 ((invert) << 24) },
2392
2393 static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
2394 {
2395 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2396 .name = "Playback Volume",
2397 .info = snd_cs4215_info_volume,
2398 .get = snd_cs4215_get_volume,
2399 .put = snd_cs4215_put_volume,
2400 .private_value = DBRI_PLAY,
2401 },
2402 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2403 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2404 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2405 {
2406 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2407 .name = "Capture Volume",
2408 .info = snd_cs4215_info_volume,
2409 .get = snd_cs4215_get_volume,
2410 .put = snd_cs4215_put_volume,
2411 .private_value = DBRI_REC,
2412 },
2413 /* FIXME: mic/line switch */
2414 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2415 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2416 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2417 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2418 };
2419
2420 static int __devinit snd_dbri_mixer(struct snd_card *card)
2421 {
2422 int idx, err;
2423 struct snd_dbri *dbri;
2424
2425 snd_assert(card != NULL && card->private_data != NULL, return -EINVAL);
2426 dbri = card->private_data;
2427
2428 strcpy(card->mixername, card->shortname);
2429
2430 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
2431 err = snd_ctl_add(card,
2432 snd_ctl_new1(&dbri_controls[idx], dbri));
2433 if (err < 0)
2434 return err;
2435 }
2436
2437 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2438 dbri->stream_info[idx].left_gain = 0;
2439 dbri->stream_info[idx].right_gain = 0;
2440 }
2441
2442 return 0;
2443 }
2444
2445 /****************************************************************************
2446 /proc interface
2447 ****************************************************************************/
2448 static void dbri_regs_read(struct snd_info_entry *entry,
2449 struct snd_info_buffer *buffer)
2450 {
2451 struct snd_dbri *dbri = entry->private_data;
2452
2453 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2454 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2455 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2456 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2457 }
2458
2459 #ifdef DBRI_DEBUG
2460 static void dbri_debug_read(struct snd_info_entry *entry,
2461 struct snd_info_buffer *buffer)
2462 {
2463 struct snd_dbri *dbri = entry->private_data;
2464 int pipe;
2465 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2466
2467 for (pipe = 0; pipe < 32; pipe++) {
2468 if (pipe_active(dbri, pipe)) {
2469 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2470 snd_iprintf(buffer,
2471 "Pipe %d: %s SDP=0x%x desc=%d, "
2472 "len=%d next %d\n",
2473 pipe,
2474 (pptr->sdp & D_SDP_TO_SER) ? "output" :
2475 "input",
2476 pptr->sdp, pptr->desc,
2477 pptr->length, pptr->nextpipe);
2478 }
2479 }
2480 }
2481 #endif
2482
2483 void __devinit snd_dbri_proc(struct snd_card *card)
2484 {
2485 struct snd_dbri *dbri = card->private_data;
2486 struct snd_info_entry *entry;
2487
2488 if (!snd_card_proc_new(card, "regs", &entry))
2489 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
2490
2491 #ifdef DBRI_DEBUG
2492 if (!snd_card_proc_new(card, "debug", &entry)) {
2493 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
2494 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2495 }
2496 #endif
2497 }
2498
2499 /*
2500 ****************************************************************************
2501 **************************** Initialization ********************************
2502 ****************************************************************************
2503 */
2504 static void snd_dbri_free(struct snd_dbri *dbri);
2505
2506 static int __devinit snd_dbri_create(struct snd_card *card,
2507 struct sbus_dev *sdev,
2508 int irq, int dev)
2509 {
2510 struct snd_dbri *dbri = card->private_data;
2511 int err;
2512
2513 spin_lock_init(&dbri->lock);
2514 dbri->sdev = sdev;
2515 dbri->irq = irq;
2516
2517 dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma),
2518 &dbri->dma_dvma);
2519 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2520
2521 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2522 dbri->dma, dbri->dma_dvma);
2523
2524 /* Map the registers into memory. */
2525 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2526 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2527 dbri->regs_size, "DBRI Registers");
2528 if (!dbri->regs) {
2529 printk(KERN_ERR "DBRI: could not allocate registers\n");
2530 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2531 (void *)dbri->dma, dbri->dma_dvma);
2532 return -EIO;
2533 }
2534
2535 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2536 "DBRI audio", dbri);
2537 if (err) {
2538 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2539 sbus_iounmap(dbri->regs, dbri->regs_size);
2540 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2541 (void *)dbri->dma, dbri->dma_dvma);
2542 return err;
2543 }
2544
2545 /* Do low level initialization of the DBRI and CS4215 chips */
2546 dbri_initialize(dbri);
2547 err = cs4215_init(dbri);
2548 if (err) {
2549 snd_dbri_free(dbri);
2550 return err;
2551 }
2552
2553 return 0;
2554 }
2555
2556 static void snd_dbri_free(struct snd_dbri *dbri)
2557 {
2558 dprintk(D_GEN, "snd_dbri_free\n");
2559 dbri_reset(dbri);
2560
2561 if (dbri->irq)
2562 free_irq(dbri->irq, dbri);
2563
2564 if (dbri->regs)
2565 sbus_iounmap(dbri->regs, dbri->regs_size);
2566
2567 if (dbri->dma)
2568 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
2569 (void *)dbri->dma, dbri->dma_dvma);
2570 }
2571
2572 static int __devinit dbri_probe(struct of_device *of_dev,
2573 const struct of_device_id *match)
2574 {
2575 struct sbus_dev *sdev = to_sbus_device(&of_dev->dev);
2576 struct snd_dbri *dbri;
2577 int irq;
2578 struct resource *rp;
2579 struct snd_card *card;
2580 static int dev = 0;
2581 int err;
2582
2583 dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n",
2584 sdev->prom_name, sdev->slot);
2585
2586 if (dev >= SNDRV_CARDS)
2587 return -ENODEV;
2588 if (!enable[dev]) {
2589 dev++;
2590 return -ENOENT;
2591 }
2592
2593 irq = sdev->irqs[0];
2594 if (irq <= 0) {
2595 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev);
2596 return -ENODEV;
2597 }
2598
2599 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2600 sizeof(struct snd_dbri));
2601 if (card == NULL)
2602 return -ENOMEM;
2603
2604 strcpy(card->driver, "DBRI");
2605 strcpy(card->shortname, "Sun DBRI");
2606 rp = &sdev->resource[0];
2607 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
2608 card->shortname,
2609 rp->flags & 0xffL, (unsigned long long)rp->start, irq);
2610
2611 err = snd_dbri_create(card, sdev, irq, dev);
2612 if (err < 0) {
2613 snd_card_free(card);
2614 return err;
2615 }
2616
2617 dbri = card->private_data;
2618 err = snd_dbri_pcm(card);
2619 if (err < 0)
2620 goto _err;
2621
2622 err = snd_dbri_mixer(card);
2623 if (err < 0)
2624 goto _err;
2625
2626 /* /proc file handling */
2627 snd_dbri_proc(card);
2628 dev_set_drvdata(&of_dev->dev, card);
2629
2630 err = snd_card_register(card);
2631 if (err < 0)
2632 goto _err;
2633
2634 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2635 dev, dbri->regs,
2636 dbri->irq, sdev->prom_name[9], dbri->mm.version);
2637 dev++;
2638
2639 return 0;
2640
2641 _err:
2642 snd_dbri_free(dbri);
2643 snd_card_free(card);
2644 return err;
2645 }
2646
2647 static int __devexit dbri_remove(struct of_device *dev)
2648 {
2649 struct snd_card *card = dev_get_drvdata(&dev->dev);
2650
2651 snd_dbri_free(card->private_data);
2652 snd_card_free(card);
2653
2654 dev_set_drvdata(&dev->dev, NULL);
2655
2656 return 0;
2657 }
2658
2659 static struct of_device_id dbri_match[] = {
2660 {
2661 .name = "SUNW,DBRIe",
2662 },
2663 {
2664 .name = "SUNW,DBRIf",
2665 },
2666 {},
2667 };
2668
2669 MODULE_DEVICE_TABLE(of, dbri_match);
2670
2671 static struct of_platform_driver dbri_sbus_driver = {
2672 .name = "dbri",
2673 .match_table = dbri_match,
2674 .probe = dbri_probe,
2675 .remove = __devexit_p(dbri_remove),
2676 };
2677
2678 /* Probe for the dbri chip and then attach the driver. */
2679 static int __init dbri_init(void)
2680 {
2681 return of_register_driver(&dbri_sbus_driver, &sbus_bus_type);
2682 }
2683
2684 static void __exit dbri_exit(void)
2685 {
2686 of_unregister_driver(&dbri_sbus_driver);
2687 }
2688
2689 module_init(dbri_init);
2690 module_exit(dbri_exit);
WRT350N Kernel Patches