[PATCH] IB uverbs: memory pinning implementation
[wrt350n-kernel.git] / include / asm-s390 / smp.h
blobdd50e57a928f2a6fa37e29b5cca503075221971c
1 /*
2 * include/asm-s390/smp.h
4 * S390 version
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
7 * Martin Schwidefsky (schwidefsky@de.ibm.com)
8 * Heiko Carstens (heiko.carstens@de.ibm.com)
9 */
10 #ifndef __ASM_SMP_H
11 #define __ASM_SMP_H
13 #include <linux/config.h>
14 #include <linux/threads.h>
15 #include <linux/cpumask.h>
16 #include <linux/bitops.h>
18 #if defined(__KERNEL__) && defined(CONFIG_SMP) && !defined(__ASSEMBLY__)
20 #include <asm/lowcore.h>
21 #include <asm/sigp.h>
24 s390 specific smp.c headers
26 typedef struct
28 int intresting;
29 sigp_ccode ccode;
30 __u32 status;
31 __u16 cpu;
32 } sigp_info;
34 extern int smp_call_function_on(void (*func) (void *info), void *info,
35 int nonatomic, int wait, int cpu);
36 #define NO_PROC_ID 0xFF /* No processor magic marker */
39 * This magic constant controls our willingness to transfer
40 * a process across CPUs. Such a transfer incurs misses on the L1
41 * cache, and on a P6 or P5 with multiple L2 caches L2 hits. My
42 * gut feeling is this will vary by board in value. For a board
43 * with separate L2 cache it probably depends also on the RSS, and
44 * for a board with shared L2 cache it ought to decay fast as other
45 * processes are run.
48 #define PROC_CHANGE_PENALTY 20 /* Schedule penalty */
50 #define raw_smp_processor_id() (S390_lowcore.cpu_data.cpu_nr)
52 extern int smp_get_cpu(cpumask_t cpu_map);
53 extern void smp_put_cpu(int cpu);
55 extern __inline__ __u16 hard_smp_processor_id(void)
57 __u16 cpu_address;
59 __asm__ ("stap %0\n" : "=m" (cpu_address));
60 return cpu_address;
64 * returns 1 if cpu is in stopped/check stopped state or not operational
65 * returns 0 otherwise
67 static inline int
68 smp_cpu_not_running(int cpu)
70 __u32 status;
72 switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
73 case sigp_order_code_accepted:
74 case sigp_status_stored:
75 /* Check for stopped and check stop state */
76 if (status & 0x50)
77 return 1;
78 break;
79 case sigp_not_operational:
80 return 1;
81 default:
82 break;
84 return 0;
87 #define cpu_logical_map(cpu) (cpu)
89 extern int __cpu_disable (void);
90 extern void __cpu_die (unsigned int cpu);
91 extern void cpu_die (void) __attribute__ ((noreturn));
92 extern int __cpu_up (unsigned int cpu);
94 #endif
96 #ifndef CONFIG_SMP
97 static inline int
98 smp_call_function_on(void (*func) (void *info), void *info,
99 int nonatomic, int wait, int cpu)
101 func(info);
102 return 0;
104 #define smp_get_cpu(cpu) ({ 0; })
105 #define smp_put_cpu(cpu) ({ 0; })
106 #endif
108 #endif