?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] tgafb: switch to framebuffer_alloc()
[wrt350n-kernel.git] / drivers / video / tgafb.c
blob0a00a6cc7c2b9cf4d9463ed6e1a9df22d2b5464b
1 /*
2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
3 *
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/fb.h>
24 #include <linux/pci.h>
25 #include <linux/selection.h>
26 #include <linux/bitrev.h>
27 #include <asm/io.h>
28 #include <video/tgafb.h>
29
30 /*
31 * Local functions.
32 */
33
34 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
35 static int tgafb_set_par(struct fb_info *);
36 static void tgafb_set_pll(struct tga_par *, int);
37 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
38 unsigned, struct fb_info *);
39 static int tgafb_blank(int, struct fb_info *);
40 static void tgafb_init_fix(struct fb_info *);
41
42 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
43 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
44 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
45
46 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
47 static void tgafb_pci_unregister(struct pci_dev *);
48
49 static const char *mode_option = "640x480@60";
50
51
52 /*
53 * Frame buffer operations
54 */
55
56 static struct fb_ops tgafb_ops = {
57 .owner = THIS_MODULE,
58 .fb_check_var = tgafb_check_var,
59 .fb_set_par = tgafb_set_par,
60 .fb_setcolreg = tgafb_setcolreg,
61 .fb_blank = tgafb_blank,
62 .fb_fillrect = tgafb_fillrect,
63 .fb_copyarea = tgafb_copyarea,
64 .fb_imageblit = tgafb_imageblit,
65 };
66
67
68 /*
69 * PCI registration operations
70 */
71
72 static struct pci_device_id const tgafb_pci_table[] = {
73 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, PCI_ANY_ID, PCI_ANY_ID,
74 0, 0, 0 }
75 };
76
77 static struct pci_driver tgafb_driver = {
78 .name = "tgafb",
79 .id_table = tgafb_pci_table,
80 .probe = tgafb_pci_register,
81 .remove = __devexit_p(tgafb_pci_unregister),
82 };
83
84
85 /**
86 * tgafb_check_var - Optional function. Validates a var passed in.
87 * @var: frame buffer variable screen structure
88 * @info: frame buffer structure that represents a single frame buffer
89 */
90 static int
91 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
92 {
93 struct tga_par *par = (struct tga_par *)info->par;
94
95 if (par->tga_type == TGA_TYPE_8PLANE) {
96 if (var->bits_per_pixel != 8)
97 return -EINVAL;
98 } else {
99 if (var->bits_per_pixel != 32)
100 return -EINVAL;
101 }
102
103 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
104 return -EINVAL;
105 if (var->nonstd)
106 return -EINVAL;
107 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
108 return -EINVAL;
109 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
110 return -EINVAL;
111
112 /* Some of the acceleration routines assume the line width is
113 a multiple of 64 bytes. */
114 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
115 return -EINVAL;
116
117 return 0;
118 }
119
120 /**
121 * tgafb_set_par - Optional function. Alters the hardware state.
122 * @info: frame buffer structure that represents a single frame buffer
123 */
124 static int
125 tgafb_set_par(struct fb_info *info)
126 {
127 static unsigned int const deep_presets[4] = {
128 0x00014000,
129 0x0001440d,
130 0xffffffff,
131 0x0001441d
132 };
133 static unsigned int const rasterop_presets[4] = {
134 0x00000003,
135 0x00000303,
136 0xffffffff,
137 0x00000303
138 };
139 static unsigned int const mode_presets[4] = {
140 0x00002000,
141 0x00002300,
142 0xffffffff,
143 0x00002300
144 };
145 static unsigned int const base_addr_presets[4] = {
146 0x00000000,
147 0x00000001,
148 0xffffffff,
149 0x00000001
150 };
151
152 struct tga_par *par = (struct tga_par *) info->par;
153 u32 htimings, vtimings, pll_freq;
154 u8 tga_type;
155 int i, j;
156
157 /* Encode video timings. */
158 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
159 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
160 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
161 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
162 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
163 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
164 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
165 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
166 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
167
168 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
169 htimings |= TGA_HORIZ_POLARITY;
170 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
171 vtimings |= TGA_VERT_POLARITY;
172
173 par->htimings = htimings;
174 par->vtimings = vtimings;
175
176 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
177
178 /* Store other useful values in par. */
179 par->xres = info->var.xres;
180 par->yres = info->var.yres;
181 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
182 par->bits_per_pixel = info->var.bits_per_pixel;
183
184 tga_type = par->tga_type;
185
186 /* First, disable video. */
187 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
188
189 /* Write the DEEP register. */
190 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
191 continue;
192 mb();
193 TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG);
194 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
195 continue;
196 mb();
197
198 /* Write some more registers. */
199 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
200 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
201 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
202
203 /* Calculate & write the PLL. */
204 tgafb_set_pll(par, pll_freq);
205
206 /* Write some more registers. */
207 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
208 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
209
210 /* Init video timing regs. */
211 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
212 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
213
214 /* Initalise RAMDAC. */
215 if (tga_type == TGA_TYPE_8PLANE) {
216
217 /* Init BT485 RAMDAC registers. */
218 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
219 BT485_CMD_0);
220 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
221 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
222 BT485_WRITE(par, 0x40, BT485_CMD_1);
223 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
224 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
225
226 /* Fill palette registers. */
227 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
228 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
229
230 for (i = 0; i < 16; i++) {
231 j = color_table[i];
232 TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
233 TGA_RAMDAC_REG);
234 TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
235 TGA_RAMDAC_REG);
236 TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
237 TGA_RAMDAC_REG);
238 }
239 for (i = 0; i < 240*3; i += 4) {
240 TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8),
241 TGA_RAMDAC_REG);
242 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
243 TGA_RAMDAC_REG);
244 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
245 TGA_RAMDAC_REG);
246 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
247 TGA_RAMDAC_REG);
248 }
249
250 } else { /* 24-plane or 24plusZ */
251
252 /* Init BT463 registers. */
253 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
254 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
255 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
256 (par->sync_on_green ? 0x80 : 0x40));
257
258 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
259 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
260 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
261 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
262
263 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
264 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
265 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
266 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
267
268 /* Fill the palette. */
269 BT463_LOAD_ADDR(par, 0x0000);
270 TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG);
271
272 for (i = 0; i < 16; i++) {
273 j = color_table[i];
274 TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10),
275 TGA_RAMDAC_REG);
276 TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10),
277 TGA_RAMDAC_REG);
278 TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
279 TGA_RAMDAC_REG);
280 }
281 for (i = 0; i < 512*3; i += 4) {
282 TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10),
283 TGA_RAMDAC_REG);
284 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
285 TGA_RAMDAC_REG);
286 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
287 TGA_RAMDAC_REG);
288 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
289 TGA_RAMDAC_REG);
290 }
291
292 /* Fill window type table after start of vertical retrace. */
293 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
294 continue;
295 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
296 mb();
297 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
298 continue;
299 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
300
301 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
302 TGA_WRITE_REG(par, BT463_REG_ACC<<2, TGA_RAMDAC_SETUP_REG);
303
304 for (i = 0; i < 16; i++) {
305 TGA_WRITE_REG(par, 0x00|(BT463_REG_ACC<<10),
306 TGA_RAMDAC_REG);
307 TGA_WRITE_REG(par, 0x01|(BT463_REG_ACC<<10),
308 TGA_RAMDAC_REG);
309 TGA_WRITE_REG(par, 0x80|(BT463_REG_ACC<<10),
310 TGA_RAMDAC_REG);
311 }
312
313 }
314
315 /* Finally, enable video scan (and pray for the monitor... :-) */
316 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
317
318 return 0;
319 }
320
321 #define DIFFCHECK(X) \
322 do { \
323 if (m <= 0x3f) { \
324 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
325 if (delta < 0) \
326 delta = -delta; \
327 if (delta < min_diff) \
328 min_diff = delta, vm = m, va = a, vr = r; \
329 } \
330 } while (0)
331
332 static void
333 tgafb_set_pll(struct tga_par *par, int f)
334 {
335 int n, shift, base, min_diff, target;
336 int r,a,m,vm = 34, va = 1, vr = 30;
337
338 for (r = 0 ; r < 12 ; r++)
339 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
340
341 if (f > TGA_PLL_MAX_FREQ)
342 f = TGA_PLL_MAX_FREQ;
343
344 if (f >= TGA_PLL_MAX_FREQ / 2)
345 shift = 0;
346 else if (f >= TGA_PLL_MAX_FREQ / 4)
347 shift = 1;
348 else
349 shift = 2;
350
351 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
352 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
353
354 for (r = 0 ; r < 10 ; r++)
355 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
356
357 if (f <= 120000) {
358 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
359 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
360 }
361 else if (f <= 200000) {
362 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
363 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
364 }
365 else {
366 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
367 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
368 }
369
370 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
371 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
372 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
373 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
374 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
375 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
376
377 target = (f << shift) / TGA_PLL_BASE_FREQ;
378 min_diff = TGA_PLL_MAX_FREQ;
379
380 r = 7 / target;
381 if (!r) r = 1;
382
383 base = target * r;
384 while (base < 449) {
385 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
386 m = ((n + 3) / 7) - 1;
387 a = 0;
388 DIFFCHECK((m + 1) * 7);
389 m++;
390 DIFFCHECK((m + 1) * 7);
391 m = (n / 6) - 1;
392 if ((a = n % 6))
393 DIFFCHECK(n);
394 }
395 r++;
396 base += target;
397 }
398
399 vr--;
400
401 for (r = 0; r < 8; r++)
402 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
403 for (r = 0; r < 8 ; r++)
404 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
405 for (r = 0; r < 7 ; r++)
406 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
407 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
408 }
409
410
411 /**
412 * tgafb_setcolreg - Optional function. Sets a color register.
413 * @regno: boolean, 0 copy local, 1 get_user() function
414 * @red: frame buffer colormap structure
415 * @green: The green value which can be up to 16 bits wide
416 * @blue: The blue value which can be up to 16 bits wide.
417 * @transp: If supported the alpha value which can be up to 16 bits wide.
418 * @info: frame buffer info structure
419 */
420 static int
421 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
422 unsigned transp, struct fb_info *info)
423 {
424 struct tga_par *par = (struct tga_par *) info->par;
425
426 if (regno > 255)
427 return 1;
428 red >>= 8;
429 green >>= 8;
430 blue >>= 8;
431
432 if (par->tga_type == TGA_TYPE_8PLANE) {
433 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
434 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
435 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
436 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
437 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
438 } else if (regno < 16) {
439 u32 value = (red << 16) | (green << 8) | blue;
440 ((u32 *)info->pseudo_palette)[regno] = value;
441 }
442
443 return 0;
444 }
445
446
447 /**
448 * tgafb_blank - Optional function. Blanks the display.
449 * @blank_mode: the blank mode we want.
450 * @info: frame buffer structure that represents a single frame buffer
451 */
452 static int
453 tgafb_blank(int blank, struct fb_info *info)
454 {
455 struct tga_par *par = (struct tga_par *) info->par;
456 u32 vhcr, vvcr, vvvr;
457 unsigned long flags;
458
459 local_irq_save(flags);
460
461 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
462 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
463 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
464 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
465
466 switch (blank) {
467 case FB_BLANK_UNBLANK: /* Unblanking */
468 if (par->vesa_blanked) {
469 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
470 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
471 par->vesa_blanked = 0;
472 }
473 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
474 break;
475
476 case FB_BLANK_NORMAL: /* Normal blanking */
477 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
478 TGA_VALID_REG);
479 break;
480
481 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
482 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
483 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
484 par->vesa_blanked = 1;
485 break;
486
487 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
488 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
489 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
490 par->vesa_blanked = 1;
491 break;
492
493 case FB_BLANK_POWERDOWN: /* Poweroff */
494 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
495 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
496 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
497 par->vesa_blanked = 1;
498 break;
499 }
500
501 local_irq_restore(flags);
502 return 0;
503 }
504
505
506 /*
507 * Acceleration.
508 */
509
510 /**
511 * tgafb_imageblit - REQUIRED function. Can use generic routines if
512 * non acclerated hardware and packed pixel based.
513 * Copies a image from system memory to the screen.
514 *
515 * @info: frame buffer structure that represents a single frame buffer
516 * @image: structure defining the image.
517 */
518 static void
519 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
520 {
521 struct tga_par *par = (struct tga_par *) info->par;
522 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
523 unsigned long rincr, line_length, shift, pos, is8bpp;
524 unsigned long i, j;
525 const unsigned char *data;
526 void __iomem *regs_base;
527 void __iomem *fb_base;
528
529 dx = image->dx;
530 dy = image->dy;
531 width = image->width;
532 height = image->height;
533 vxres = info->var.xres_virtual;
534 vyres = info->var.yres_virtual;
535 line_length = info->fix.line_length;
536 rincr = (width + 7) / 8;
537
538 /* Crop the image to the screen. */
539 if (dx > vxres || dy > vyres)
540 return;
541 if (dx + width > vxres)
542 width = vxres - dx;
543 if (dy + height > vyres)
544 height = vyres - dy;
545
546 /* For copies that aren't pixel expansion, there's little we
547 can do better than the generic code. */
548 /* ??? There is a DMA write mode; I wonder if that could be
549 made to pull the data from the image buffer... */
550 if (image->depth > 1) {
551 cfb_imageblit(info, image);
552 return;
553 }
554
555 regs_base = par->tga_regs_base;
556 fb_base = par->tga_fb_base;
557 is8bpp = info->var.bits_per_pixel == 8;
558
559 /* Expand the color values to fill 32-bits. */
560 /* ??? Would be nice to notice colour changes elsewhere, so
561 that we can do this only when necessary. */
562 fgcolor = image->fg_color;
563 bgcolor = image->bg_color;
564 if (is8bpp) {
565 fgcolor |= fgcolor << 8;
566 fgcolor |= fgcolor << 16;
567 bgcolor |= bgcolor << 8;
568 bgcolor |= bgcolor << 16;
569 } else {
570 if (fgcolor < 16)
571 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
572 if (bgcolor < 16)
573 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
574 }
575 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
576 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
577
578 /* Acquire proper alignment; set up the PIXELMASK register
579 so that we only write the proper character cell. */
580 pos = dy * line_length;
581 if (is8bpp) {
582 pos += dx;
583 shift = pos & 3;
584 pos &= -4;
585 } else {
586 pos += dx * 4;
587 shift = (pos & 7) >> 2;
588 pos &= -8;
589 }
590
591 data = (const unsigned char *) image->data;
592
593 /* Enable opaque stipple mode. */
594 __raw_writel((is8bpp
595 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
596 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
597 regs_base + TGA_MODE_REG);
598
599 if (width + shift <= 32) {
600 unsigned long bwidth;
601
602 /* Handle common case of imaging a single character, in
603 a font less than 32 pixels wide. */
604
605 pixelmask = (1 << width) - 1;
606 pixelmask <<= shift;
607 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
608 wmb();
609
610 bwidth = (width + 7) / 8;
611
612 for (i = 0; i < height; ++i) {
613 u32 mask = 0;
614
615 /* The image data is bit big endian; we need
616 little endian. */
617 for (j = 0; j < bwidth; ++j)
618 mask |= bitrev8(data[j]) << (j * 8);
619
620 __raw_writel(mask << shift, fb_base + pos);
621
622 pos += line_length;
623 data += rincr;
624 }
625 wmb();
626 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
627 } else if (shift == 0) {
628 unsigned long pos0 = pos;
629 const unsigned char *data0 = data;
630 unsigned long bincr = (is8bpp ? 8 : 8*4);
631 unsigned long bwidth;
632
633 /* Handle another common case in which accel_putcs
634 generates a large bitmap, which happens to be aligned.
635 Allow the tail to be misaligned. This case is
636 interesting because we've not got to hold partial
637 bytes across the words being written. */
638
639 wmb();
640
641 bwidth = (width / 8) & -4;
642 for (i = 0; i < height; ++i) {
643 for (j = 0; j < bwidth; j += 4) {
644 u32 mask = 0;
645 mask |= bitrev8(data[j+0]) << (0 * 8);
646 mask |= bitrev8(data[j+1]) << (1 * 8);
647 mask |= bitrev8(data[j+2]) << (2 * 8);
648 mask |= bitrev8(data[j+3]) << (3 * 8);
649 __raw_writel(mask, fb_base + pos + j*bincr);
650 }
651 pos += line_length;
652 data += rincr;
653 }
654 wmb();
655
656 pixelmask = (1ul << (width & 31)) - 1;
657 if (pixelmask) {
658 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
659 wmb();
660
661 pos = pos0 + bwidth*bincr;
662 data = data0 + bwidth;
663 bwidth = ((width & 31) + 7) / 8;
664
665 for (i = 0; i < height; ++i) {
666 u32 mask = 0;
667 for (j = 0; j < bwidth; ++j)
668 mask |= bitrev8(data[j]) << (j * 8);
669 __raw_writel(mask, fb_base + pos);
670 pos += line_length;
671 data += rincr;
672 }
673 wmb();
674 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
675 }
676 } else {
677 unsigned long pos0 = pos;
678 const unsigned char *data0 = data;
679 unsigned long bincr = (is8bpp ? 8 : 8*4);
680 unsigned long bwidth;
681
682 /* Finally, handle the generic case of misaligned start.
683 Here we split the write into 16-bit spans. This allows
684 us to use only one pixel mask, instead of four as would
685 be required by writing 24-bit spans. */
686
687 pixelmask = 0xffff << shift;
688 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
689 wmb();
690
691 bwidth = (width / 8) & -2;
692 for (i = 0; i < height; ++i) {
693 for (j = 0; j < bwidth; j += 2) {
694 u32 mask = 0;
695 mask |= bitrev8(data[j+0]) << (0 * 8);
696 mask |= bitrev8(data[j+1]) << (1 * 8);
697 mask <<= shift;
698 __raw_writel(mask, fb_base + pos + j*bincr);
699 }
700 pos += line_length;
701 data += rincr;
702 }
703 wmb();
704
705 pixelmask = ((1ul << (width & 15)) - 1) << shift;
706 if (pixelmask) {
707 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
708 wmb();
709
710 pos = pos0 + bwidth*bincr;
711 data = data0 + bwidth;
712 bwidth = (width & 15) > 8;
713
714 for (i = 0; i < height; ++i) {
715 u32 mask = bitrev8(data[0]);
716 if (bwidth)
717 mask |= bitrev8(data[1]) << 8;
718 mask <<= shift;
719 __raw_writel(mask, fb_base + pos);
720 pos += line_length;
721 data += rincr;
722 }
723 wmb();
724 }
725 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
726 }
727
728 /* Disable opaque stipple mode. */
729 __raw_writel((is8bpp
730 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
731 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
732 regs_base + TGA_MODE_REG);
733 }
734
735 /**
736 * tgafb_fillrect - REQUIRED function. Can use generic routines if
737 * non acclerated hardware and packed pixel based.
738 * Draws a rectangle on the screen.
739 *
740 * @info: frame buffer structure that represents a single frame buffer
741 * @rect: structure defining the rectagle and operation.
742 */
743 static void
744 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
745 {
746 struct tga_par *par = (struct tga_par *) info->par;
747 int is8bpp = info->var.bits_per_pixel == 8;
748 u32 dx, dy, width, height, vxres, vyres, color;
749 unsigned long pos, align, line_length, i, j;
750 void __iomem *regs_base;
751 void __iomem *fb_base;
752
753 dx = rect->dx;
754 dy = rect->dy;
755 width = rect->width;
756 height = rect->height;
757 vxres = info->var.xres_virtual;
758 vyres = info->var.yres_virtual;
759 line_length = info->fix.line_length;
760 regs_base = par->tga_regs_base;
761 fb_base = par->tga_fb_base;
762
763 /* Crop the rectangle to the screen. */
764 if (dx > vxres || dy > vyres || !width || !height)
765 return;
766 if (dx + width > vxres)
767 width = vxres - dx;
768 if (dy + height > vyres)
769 height = vyres - dy;
770
771 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
772
773 /* ??? We could implement ROP_XOR with opaque fill mode
774 and a RasterOp setting of GXxor, but as far as I can
775 tell, this mode is not actually used in the kernel.
776 Thus I am ignoring it for now. */
777 if (rect->rop != ROP_COPY) {
778 cfb_fillrect(info, rect);
779 return;
780 }
781
782 /* Expand the color value to fill 8 pixels. */
783 color = rect->color;
784 if (is8bpp) {
785 color |= color << 8;
786 color |= color << 16;
787 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
788 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
789 } else {
790 if (color < 16)
791 color = ((u32 *)info->pseudo_palette)[color];
792 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
793 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
794 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
795 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
796 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
797 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
798 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
799 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
800 }
801
802 /* The DATA register holds the fill mask for block fill mode.
803 Since we're not stippling, this is all ones. */
804 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
805
806 /* Enable block fill mode. */
807 __raw_writel((is8bpp
808 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
809 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
810 regs_base + TGA_MODE_REG);
811 wmb();
812
813 /* We can fill 2k pixels per operation. Notice blocks that fit
814 the width of the screen so that we can take advantage of this
815 and fill more than one line per write. */
816 if (width == line_length)
817 width *= height, height = 1;
818
819 /* The write into the frame buffer must be aligned to 4 bytes,
820 but we are allowed to encode the offset within the word in
821 the data word written. */
822 align = (pos & 3) << 16;
823 pos &= -4;
824
825 if (width <= 2048) {
826 u32 data;
827
828 data = (width - 1) | align;
829
830 for (i = 0; i < height; ++i) {
831 __raw_writel(data, fb_base + pos);
832 pos += line_length;
833 }
834 } else {
835 unsigned long Bpp = (is8bpp ? 1 : 4);
836 unsigned long nwidth = width & -2048;
837 u32 fdata, ldata;
838
839 fdata = (2048 - 1) | align;
840 ldata = ((width & 2047) - 1) | align;
841
842 for (i = 0; i < height; ++i) {
843 for (j = 0; j < nwidth; j += 2048)
844 __raw_writel(fdata, fb_base + pos + j*Bpp);
845 if (j < width)
846 __raw_writel(ldata, fb_base + pos + j*Bpp);
847 pos += line_length;
848 }
849 }
850 wmb();
851
852 /* Disable block fill mode. */
853 __raw_writel((is8bpp
854 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
855 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
856 regs_base + TGA_MODE_REG);
857 }
858
859 /**
860 * tgafb_copyarea - REQUIRED function. Can use generic routines if
861 * non acclerated hardware and packed pixel based.
862 * Copies on area of the screen to another area.
863 *
864 * @info: frame buffer structure that represents a single frame buffer
865 * @area: structure defining the source and destination.
866 */
867
868 /* Handle the special case of copying entire lines, e.g. during scrolling.
869 We can avoid a lot of needless computation in this case. In the 8bpp
870 case we need to use the COPY64 registers instead of mask writes into
871 the frame buffer to achieve maximum performance. */
872
873 static inline void
874 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
875 u32 height, u32 width)
876 {
877 struct tga_par *par = (struct tga_par *) info->par;
878 void __iomem *tga_regs = par->tga_regs_base;
879 unsigned long dpos, spos, i, n64;
880
881 /* Set up the MODE and PIXELSHIFT registers. */
882 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
883 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
884 wmb();
885
886 n64 = (height * width) / 64;
887
888 if (dy < sy) {
889 spos = (sy + height) * width;
890 dpos = (dy + height) * width;
891
892 for (i = 0; i < n64; ++i) {
893 spos -= 64;
894 dpos -= 64;
895 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
896 wmb();
897 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
898 wmb();
899 }
900 } else {
901 spos = sy * width;
902 dpos = dy * width;
903
904 for (i = 0; i < n64; ++i) {
905 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
906 wmb();
907 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
908 wmb();
909 spos += 64;
910 dpos += 64;
911 }
912 }
913
914 /* Reset the MODE register to normal. */
915 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
916 }
917
918 static inline void
919 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
920 u32 height, u32 width)
921 {
922 struct tga_par *par = (struct tga_par *) info->par;
923 void __iomem *tga_regs = par->tga_regs_base;
924 void __iomem *tga_fb = par->tga_fb_base;
925 void __iomem *src;
926 void __iomem *dst;
927 unsigned long i, n16;
928
929 /* Set up the MODE and PIXELSHIFT registers. */
930 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
931 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
932 wmb();
933
934 n16 = (height * width) / 16;
935
936 if (dy < sy) {
937 src = tga_fb + (sy + height) * width * 4;
938 dst = tga_fb + (dy + height) * width * 4;
939
940 for (i = 0; i < n16; ++i) {
941 src -= 64;
942 dst -= 64;
943 __raw_writel(0xffff, src);
944 wmb();
945 __raw_writel(0xffff, dst);
946 wmb();
947 }
948 } else {
949 src = tga_fb + sy * width * 4;
950 dst = tga_fb + dy * width * 4;
951
952 for (i = 0; i < n16; ++i) {
953 __raw_writel(0xffff, src);
954 wmb();
955 __raw_writel(0xffff, dst);
956 wmb();
957 src += 64;
958 dst += 64;
959 }
960 }
961
962 /* Reset the MODE register to normal. */
963 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
964 }
965
966 /* The general case of forward copy in 8bpp mode. */
967 static inline void
968 copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
969 u32 height, u32 width, u32 line_length)
970 {
971 struct tga_par *par = (struct tga_par *) info->par;
972 unsigned long i, copied, left;
973 unsigned long dpos, spos, dalign, salign, yincr;
974 u32 smask_first, dmask_first, dmask_last;
975 int pixel_shift, need_prime, need_second;
976 unsigned long n64, n32, xincr_first;
977 void __iomem *tga_regs;
978 void __iomem *tga_fb;
979
980 yincr = line_length;
981 if (dy > sy) {
982 dy += height - 1;
983 sy += height - 1;
984 yincr = -yincr;
985 }
986
987 /* Compute the offsets and alignments in the frame buffer.
988 More than anything else, these control how we do copies. */
989 dpos = dy * line_length + dx;
990 spos = sy * line_length + sx;
991 dalign = dpos & 7;
992 salign = spos & 7;
993 dpos &= -8;
994 spos &= -8;
995
996 /* Compute the value for the PIXELSHIFT register. This controls
997 both non-co-aligned source and destination and copy direction. */
998 if (dalign >= salign)
999 pixel_shift = dalign - salign;
1000 else
1001 pixel_shift = 8 - (salign - dalign);
1002
1003 /* Figure out if we need an additional priming step for the
1004 residue register. */
1005 need_prime = (salign > dalign);
1006 if (need_prime)
1007 dpos -= 8;
1008
1009 /* Begin by copying the leading unaligned destination. Copy enough
1010 to make the next destination address 32-byte aligned. */
1011 copied = 32 - (dalign + (dpos & 31));
1012 if (copied == 32)
1013 copied = 0;
1014 xincr_first = (copied + 7) & -8;
1015 smask_first = dmask_first = (1ul << copied) - 1;
1016 smask_first <<= salign;
1017 dmask_first <<= dalign + need_prime*8;
1018 if (need_prime && copied > 24)
1019 copied -= 8;
1020 left = width - copied;
1021
1022 /* Care for small copies. */
1023 if (copied > width) {
1024 u32 t;
1025 t = (1ul << width) - 1;
1026 t <<= dalign + need_prime*8;
1027 dmask_first &= t;
1028 left = 0;
1029 }
1030
1031 /* Attempt to use 64-byte copies. This is only possible if the
1032 source and destination are co-aligned at 64 bytes. */
1033 n64 = need_second = 0;
1034 if ((dpos & 63) == (spos & 63)
1035 && (height == 1 || line_length % 64 == 0)) {
1036 /* We may need a 32-byte copy to ensure 64 byte alignment. */
1037 need_second = (dpos + xincr_first) & 63;
1038 if ((need_second & 32) != need_second)
1039 printk(KERN_ERR "tgafb: need_second wrong\n");
1040 if (left >= need_second + 64) {
1041 left -= need_second;
1042 n64 = left / 64;
1043 left %= 64;
1044 } else
1045 need_second = 0;
1046 }
1047
1048 /* Copy trailing full 32-byte sections. This will be the main
1049 loop if the 64 byte loop can't be used. */
1050 n32 = left / 32;
1051 left %= 32;
1052
1053 /* Copy the trailing unaligned destination. */
1054 dmask_last = (1ul << left) - 1;
1055
1056 tga_regs = par->tga_regs_base;
1057 tga_fb = par->tga_fb_base;
1058
1059 /* Set up the MODE and PIXELSHIFT registers. */
1060 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1061 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG);
1062 wmb();
1063
1064 for (i = 0; i < height; ++i) {
1065 unsigned long j;
1066 void __iomem *sfb;
1067 void __iomem *dfb;
1068
1069 sfb = tga_fb + spos;
1070 dfb = tga_fb + dpos;
1071 if (dmask_first) {
1072 __raw_writel(smask_first, sfb);
1073 wmb();
1074 __raw_writel(dmask_first, dfb);
1075 wmb();
1076 sfb += xincr_first;
1077 dfb += xincr_first;
1078 }
1079
1080 if (need_second) {
1081 __raw_writel(0xffffffff, sfb);
1082 wmb();
1083 __raw_writel(0xffffffff, dfb);
1084 wmb();
1085 sfb += 32;
1086 dfb += 32;
1087 }
1088
1089 if (n64 && (((unsigned long)sfb | (unsigned long)dfb) & 63))
1090 printk(KERN_ERR
1091 "tgafb: misaligned copy64 (s:%p, d:%p)\n",
1092 sfb, dfb);
1093
1094 for (j = 0; j < n64; ++j) {
1095 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1096 wmb();
1097 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1098 wmb();
1099 sfb += 64;
1100 dfb += 64;
1101 }
1102
1103 for (j = 0; j < n32; ++j) {
1104 __raw_writel(0xffffffff, sfb);
1105 wmb();
1106 __raw_writel(0xffffffff, dfb);
1107 wmb();
1108 sfb += 32;
1109 dfb += 32;
1110 }
1111
1112 if (dmask_last) {
1113 __raw_writel(0xffffffff, sfb);
1114 wmb();
1115 __raw_writel(dmask_last, dfb);
1116 wmb();
1117 }
1118
1119 spos += yincr;
1120 dpos += yincr;
1121 }
1122
1123 /* Reset the MODE register to normal. */
1124 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1125 }
1126
1127 /* The (almost) general case of backward copy in 8bpp mode. */
1128 static inline void
1129 copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1130 u32 height, u32 width, u32 line_length,
1131 const struct fb_copyarea *area)
1132 {
1133 struct tga_par *par = (struct tga_par *) info->par;
1134 unsigned long i, left, yincr;
1135 unsigned long depos, sepos, dealign, sealign;
1136 u32 mask_first, mask_last;
1137 unsigned long n32;
1138 void __iomem *tga_regs;
1139 void __iomem *tga_fb;
1140
1141 yincr = line_length;
1142 if (dy > sy) {
1143 dy += height - 1;
1144 sy += height - 1;
1145 yincr = -yincr;
1146 }
1147
1148 /* Compute the offsets and alignments in the frame buffer.
1149 More than anything else, these control how we do copies. */
1150 depos = dy * line_length + dx + width;
1151 sepos = sy * line_length + sx + width;
1152 dealign = depos & 7;
1153 sealign = sepos & 7;
1154
1155 /* ??? The documentation appears to be incorrect (or very
1156 misleading) wrt how pixel shifting works in backward copy
1157 mode, i.e. when PIXELSHIFT is negative. I give up for now.
1158 Do handle the common case of co-aligned backward copies,
1159 but frob everything else back on generic code. */
1160 if (dealign != sealign) {
1161 cfb_copyarea(info, area);
1162 return;
1163 }
1164
1165 /* We begin the copy with the trailing pixels of the
1166 unaligned destination. */
1167 mask_first = (1ul << dealign) - 1;
1168 left = width - dealign;
1169
1170 /* Care for small copies. */
1171 if (dealign > width) {
1172 mask_first ^= (1ul << (dealign - width)) - 1;
1173 left = 0;
1174 }
1175
1176 /* Next copy full words at a time. */
1177 n32 = left / 32;
1178 left %= 32;
1179
1180 /* Finally copy the unaligned head of the span. */
1181 mask_last = -1 << (32 - left);
1182
1183 tga_regs = par->tga_regs_base;
1184 tga_fb = par->tga_fb_base;
1185
1186 /* Set up the MODE and PIXELSHIFT registers. */
1187 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1188 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1189 wmb();
1190
1191 for (i = 0; i < height; ++i) {
1192 unsigned long j;
1193 void __iomem *sfb;
1194 void __iomem *dfb;
1195
1196 sfb = tga_fb + sepos;
1197 dfb = tga_fb + depos;
1198 if (mask_first) {
1199 __raw_writel(mask_first, sfb);
1200 wmb();
1201 __raw_writel(mask_first, dfb);
1202 wmb();
1203 }
1204
1205 for (j = 0; j < n32; ++j) {
1206 sfb -= 32;
1207 dfb -= 32;
1208 __raw_writel(0xffffffff, sfb);
1209 wmb();
1210 __raw_writel(0xffffffff, dfb);
1211 wmb();
1212 }
1213
1214 if (mask_last) {
1215 sfb -= 32;
1216 dfb -= 32;
1217 __raw_writel(mask_last, sfb);
1218 wmb();
1219 __raw_writel(mask_last, dfb);
1220 wmb();
1221 }
1222
1223 sepos += yincr;
1224 depos += yincr;
1225 }
1226
1227 /* Reset the MODE register to normal. */
1228 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1229 }
1230
1231 static void
1232 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1233 {
1234 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1235 unsigned long line_length, bpp;
1236
1237 dx = area->dx;
1238 dy = area->dy;
1239 width = area->width;
1240 height = area->height;
1241 sx = area->sx;
1242 sy = area->sy;
1243 vxres = info->var.xres_virtual;
1244 vyres = info->var.yres_virtual;
1245 line_length = info->fix.line_length;
1246
1247 /* The top left corners must be in the virtual screen. */
1248 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1249 return;
1250
1251 /* Clip the destination. */
1252 if (dx + width > vxres)
1253 width = vxres - dx;
1254 if (dy + height > vyres)
1255 height = vyres - dy;
1256
1257 /* The source must be completely inside the virtual screen. */
1258 if (sx + width > vxres || sy + height > vyres)
1259 return;
1260
1261 bpp = info->var.bits_per_pixel;
1262
1263 /* Detect copies of the entire line. */
1264 if (width * (bpp >> 3) == line_length) {
1265 if (bpp == 8)
1266 copyarea_line_8bpp(info, dy, sy, height, width);
1267 else
1268 copyarea_line_32bpp(info, dy, sy, height, width);
1269 }
1270
1271 /* ??? The documentation is unclear to me exactly how the pixelshift
1272 register works in 32bpp mode. Since I don't have hardware to test,
1273 give up for now and fall back on the generic routines. */
1274 else if (bpp == 32)
1275 cfb_copyarea(info, area);
1276
1277 /* Detect overlapping source and destination that requires
1278 a backward copy. */
1279 else if (dy == sy && dx > sx && dx < sx + width)
1280 copyarea_backward_8bpp(info, dx, dy, sx, sy, height,
1281 width, line_length, area);
1282 else
1283 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height,
1284 width, line_length);
1285 }
1286
1287
1288 /*
1289 * Initialisation
1290 */
1291
1292 static void
1293 tgafb_init_fix(struct fb_info *info)
1294 {
1295 struct tga_par *par = (struct tga_par *)info->par;
1296 u8 tga_type = par->tga_type;
1297 const char *tga_type_name;
1298
1299 switch (tga_type) {
1300 case TGA_TYPE_8PLANE:
1301 tga_type_name = "Digital ZLXp-E1";
1302 break;
1303 case TGA_TYPE_24PLANE:
1304 tga_type_name = "Digital ZLXp-E2";
1305 break;
1306 case TGA_TYPE_24PLUSZ:
1307 tga_type_name = "Digital ZLXp-E3";
1308 break;
1309 default:
1310 tga_type_name = "Unknown";
1311 break;
1312 }
1313
1314 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1315
1316 info->fix.type = FB_TYPE_PACKED_PIXELS;
1317 info->fix.type_aux = 0;
1318 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1319 ? FB_VISUAL_PSEUDOCOLOR
1320 : FB_VISUAL_TRUECOLOR);
1321
1322 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
1323 info->fix.smem_start = (size_t) par->tga_fb_base;
1324 info->fix.smem_len = info->fix.line_length * par->yres;
1325 info->fix.mmio_start = (size_t) par->tga_regs_base;
1326 info->fix.mmio_len = 512;
1327
1328 info->fix.xpanstep = 0;
1329 info->fix.ypanstep = 0;
1330 info->fix.ywrapstep = 0;
1331
1332 info->fix.accel = FB_ACCEL_DEC_TGA;
1333 }
1334
1335 static __devinit int
1336 tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
1337 {
1338 static unsigned int const fb_offset_presets[4] = {
1339 TGA_8PLANE_FB_OFFSET,
1340 TGA_24PLANE_FB_OFFSET,
1341 0xffffffff,
1342 TGA_24PLUSZ_FB_OFFSET
1343 };
1344
1345 void __iomem *mem_base;
1346 unsigned long bar0_start, bar0_len;
1347 struct fb_info *info;
1348 struct tga_par *par;
1349 u8 tga_type;
1350 int ret;
1351
1352 /* Enable device in PCI config. */
1353 if (pci_enable_device(pdev)) {
1354 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1355 return -ENODEV;
1356 }
1357
1358 /* Allocate the fb and par structures. */
1359 info = framebuffer_alloc(sizeof(struct tga_par), &pdev->dev);
1360 if (!info) {
1361 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1362 return -ENOMEM;
1363 }
1364
1365 par = info->par;
1366 pci_set_drvdata(pdev, info);
1367
1368 /* Request the mem regions. */
1369 bar0_start = pci_resource_start(pdev, 0);
1370 bar0_len = pci_resource_len(pdev, 0);
1371 ret = -ENODEV;
1372 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1373 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1374 goto err0;
1375 }
1376
1377 /* Map the framebuffer. */
1378 mem_base = ioremap(bar0_start, bar0_len);
1379 if (!mem_base) {
1380 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1381 goto err1;
1382 }
1383
1384 /* Grab info about the card. */
1385 tga_type = (readl(mem_base) >> 12) & 0x0f;
1386 par->pdev = pdev;
1387 par->tga_mem_base = mem_base;
1388 par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
1389 par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
1390 par->tga_type = tga_type;
1391 pci_read_config_byte(pdev, PCI_REVISION_ID, &par->tga_chip_rev);
1392
1393 /* Setup framebuffer. */
1394 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1395 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1396 info->fbops = &tgafb_ops;
1397 info->screen_base = par->tga_fb_base;
1398 info->pseudo_palette = (void *)(par + 1);
1399
1400 /* This should give a reasonable default video mode. */
1401
1402 ret = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL,
1403 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1404 if (ret == 0 || ret == 4) {
1405 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1406 ret = -EINVAL;
1407 goto err1;
1408 }
1409
1410 if (fb_alloc_cmap(&info->cmap, 256, 0)) {
1411 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1412 ret = -ENOMEM;
1413 goto err1;
1414 }
1415
1416 tgafb_set_par(info);
1417 tgafb_init_fix(info);
1418
1419 if (register_framebuffer(info) < 0) {
1420 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1421 ret = -EINVAL;
1422 goto err1;
1423 }
1424
1425 printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1426 par->tga_chip_rev);
1427 printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
1428 pdev->bus->number, PCI_SLOT(pdev->devfn),
1429 PCI_FUNC(pdev->devfn));
1430 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
1431 info->node, info->fix.id, bar0_start);
1432
1433 return 0;
1434
1435 err1:
1436 if (mem_base)
1437 iounmap(mem_base);
1438 release_mem_region(bar0_start, bar0_len);
1439 err0:
1440 framebuffer_release(info);
1441 return ret;
1442 }
1443
1444 static void __exit
1445 tgafb_pci_unregister(struct pci_dev *pdev)
1446 {
1447 struct fb_info *info = pci_get_drvdata(pdev);
1448 struct tga_par *par = info->par;
1449
1450 if (!info)
1451 return;
1452 unregister_framebuffer(info);
1453 fb_dealloc_cmap(&info->cmap);
1454 iounmap(par->tga_mem_base);
1455 release_mem_region(pci_resource_start(pdev, 0),
1456 pci_resource_len(pdev, 0));
1457 framebuffer_release(info);
1458 }
1459
1460 #ifdef MODULE
1461 static void __exit
1462 tgafb_exit(void)
1463 {
1464 pci_unregister_driver(&tgafb_driver);
1465 }
1466 #endif /* MODULE */
1467
1468 #ifndef MODULE
1469 int __init
1470 tgafb_setup(char *arg)
1471 {
1472 char *this_opt;
1473
1474 if (arg && *arg) {
1475 while ((this_opt = strsep(&arg, ","))) {
1476 if (!*this_opt)
1477 continue;
1478 if (!strncmp(this_opt, "mode:", 5))
1479 mode_option = this_opt+5;
1480 else
1481 printk(KERN_ERR
1482 "tgafb: unknown parameter %s\n",
1483 this_opt);
1484 }
1485 }
1486
1487 return 0;
1488 }
1489 #endif /* !MODULE */
1490
1491 int __init
1492 tgafb_init(void)
1493 {
1494 #ifndef MODULE
1495 char *option = NULL;
1496
1497 if (fb_get_options("tgafb", &option))
1498 return -ENODEV;
1499 tgafb_setup(option);
1500 #endif
1501 return pci_register_driver(&tgafb_driver);
1502 }
1503
1504 /*
1505 * Modularisation
1506 */
1507
1508 module_init(tgafb_init);
1509
1510 #ifdef MODULE
1511 module_exit(tgafb_exit);
1512 #endif
1513
1514 MODULE_DESCRIPTION("framebuffer driver for TGA chipset");
1515 MODULE_LICENSE("GPL");
WRT350N Kernel Patches