x86: fix bogus KERN_ALERT on oops
[wrt350n-kernel.git] / arch / mips / tx4938 / toshiba_rbtx4938 / irq.c
blobf00185017e80bea947267998b1ecdf15579e1e27
1 /*
2 * linux/arch/mips/tx4938/toshiba_rbtx4938/irq.c
4 * Toshiba RBTX4938 specific interrupt handlers
5 * Copyright (C) 2000-2001 Toshiba Corporation
7 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
12 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
16 IRQ Device
18 16 TX4938-CP0/00 Software 0
19 17 TX4938-CP0/01 Software 1
20 18 TX4938-CP0/02 Cascade TX4938-CP0
21 19 TX4938-CP0/03 Multiplexed -- do not use
22 20 TX4938-CP0/04 Multiplexed -- do not use
23 21 TX4938-CP0/05 Multiplexed -- do not use
24 22 TX4938-CP0/06 Multiplexed -- do not use
25 23 TX4938-CP0/07 CPU TIMER
27 24 TX4938-PIC/00
28 25 TX4938-PIC/01
29 26 TX4938-PIC/02 Cascade RBTX4938-IOC
30 27 TX4938-PIC/03 RBTX4938 RTL-8019AS Ethernet
31 28 TX4938-PIC/04
32 29 TX4938-PIC/05 TX4938 ETH1
33 30 TX4938-PIC/06 TX4938 ETH0
34 31 TX4938-PIC/07
35 32 TX4938-PIC/08 TX4938 SIO 0
36 33 TX4938-PIC/09 TX4938 SIO 1
37 34 TX4938-PIC/10 TX4938 DMA0
38 35 TX4938-PIC/11 TX4938 DMA1
39 36 TX4938-PIC/12 TX4938 DMA2
40 37 TX4938-PIC/13 TX4938 DMA3
41 38 TX4938-PIC/14
42 39 TX4938-PIC/15
43 40 TX4938-PIC/16 TX4938 PCIC
44 41 TX4938-PIC/17 TX4938 TMR0
45 42 TX4938-PIC/18 TX4938 TMR1
46 43 TX4938-PIC/19 TX4938 TMR2
47 44 TX4938-PIC/20
48 45 TX4938-PIC/21
49 46 TX4938-PIC/22 TX4938 PCIERR
50 47 TX4938-PIC/23
51 48 TX4938-PIC/24
52 49 TX4938-PIC/25
53 50 TX4938-PIC/26
54 51 TX4938-PIC/27
55 52 TX4938-PIC/28
56 53 TX4938-PIC/29
57 54 TX4938-PIC/30
58 55 TX4938-PIC/31 TX4938 SPI
60 56 RBTX4938-IOC/00 PCI-D
61 57 RBTX4938-IOC/01 PCI-C
62 58 RBTX4938-IOC/02 PCI-B
63 59 RBTX4938-IOC/03 PCI-A
64 60 RBTX4938-IOC/04 RTC
65 61 RBTX4938-IOC/05 ATA
66 62 RBTX4938-IOC/06 MODEM
67 63 RBTX4938-IOC/07 SWINT
69 #include <linux/init.h>
70 #include <linux/kernel.h>
71 #include <linux/types.h>
72 #include <linux/mm.h>
73 #include <linux/swap.h>
74 #include <linux/ioport.h>
75 #include <linux/sched.h>
76 #include <linux/interrupt.h>
77 #include <linux/pci.h>
78 #include <linux/timex.h>
79 #include <asm/bootinfo.h>
80 #include <asm/page.h>
81 #include <asm/io.h>
82 #include <asm/irq.h>
83 #include <asm/processor.h>
84 #include <asm/reboot.h>
85 #include <asm/time.h>
86 #include <asm/wbflush.h>
87 #include <linux/bootmem.h>
88 #include <asm/tx4938/rbtx4938.h>
90 static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
91 static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
93 #define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
94 static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
95 .name = TOSHIBA_RBTX4938_IOC_NAME,
96 .ack = toshiba_rbtx4938_irq_ioc_disable,
97 .mask = toshiba_rbtx4938_irq_ioc_disable,
98 .mask_ack = toshiba_rbtx4938_irq_ioc_disable,
99 .unmask = toshiba_rbtx4938_irq_ioc_enable,
102 #define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
103 #define TOSHIBA_RBTX4938_IOC_INTR_STAT 0xb7f0200a
106 toshiba_rbtx4938_irq_nested(int sw_irq)
108 u8 level3;
110 level3 = reg_rd08(TOSHIBA_RBTX4938_IOC_INTR_STAT) & 0xff;
111 if (level3) {
112 /* must use fls so onboard ATA has priority */
113 sw_irq = TOSHIBA_RBTX4938_IRQ_IOC_BEG + fls(level3) - 1;
116 wbflush();
117 return sw_irq;
120 static struct irqaction toshiba_rbtx4938_irq_ioc_action = {
121 .handler = no_action,
122 .flags = 0,
123 .mask = CPU_MASK_NONE,
124 .name = TOSHIBA_RBTX4938_IOC_NAME,
127 /**********************************************************************************/
128 /* Functions for ioc */
129 /**********************************************************************************/
130 static void __init
131 toshiba_rbtx4938_irq_ioc_init(void)
133 int i;
135 for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG;
136 i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++)
137 set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
138 handle_level_irq);
140 setup_irq(RBTX4938_IRQ_IOCINT,
141 &toshiba_rbtx4938_irq_ioc_action);
144 static void
145 toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
147 volatile unsigned char v;
149 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
150 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
151 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
152 mmiowb();
153 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
156 static void
157 toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
159 volatile unsigned char v;
161 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
162 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
163 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
164 mmiowb();
165 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
168 void __init arch_init_irq(void)
170 extern void tx4938_irq_init(void);
172 /* Now, interrupt control disabled, */
173 /* all IRC interrupts are masked, */
174 /* all IRC interrupt mode are Low Active. */
176 /* mask all IOC interrupts */
177 *rbtx4938_imask_ptr = 0;
179 /* clear SoftInt interrupts */
180 *rbtx4938_softint_ptr = 0;
181 tx4938_irq_init();
182 toshiba_rbtx4938_irq_ioc_init();
183 /* Onboard 10M Ether: High Active */
184 set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
186 wbflush();