| blob | fcd333c391ec15c285b1c23e370b5c24cf289c0d |
1 /*
2 * MPC8323E EMDS Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 / {
13 model = "MPC8323EMDS";
14 compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
15 #address-cells = <1>;
16 #size-cells = <1>;
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
22 PowerPC,8323@0 {
23 device_type = "cpu";
24 reg = <0>;
25 d-cache-line-size = <20>; // 32 bytes
26 i-cache-line-size = <20>; // 32 bytes
27 d-cache-size = <4000>; // L1, 16K
28 i-cache-size = <4000>; // L1, 16K
29 timebase-frequency = <0>;
30 bus-frequency = <0>;
31 clock-frequency = <0>;
32 };
33 };
35 memory {
36 device_type = "memory";
37 reg = <00000000 08000000>;
38 };
40 bcsr@f8000000 {
41 device_type = "board-control";
42 reg = <f8000000 8000>;
43 };
45 soc8323@e0000000 {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 device_type = "soc";
49 ranges = <0 e0000000 00100000>;
50 reg = <e0000000 00000200>;
51 bus-frequency = <7DE2900>;
53 wdt@200 {
54 device_type = "watchdog";
55 compatible = "mpc83xx_wdt";
56 reg = <200 100>;
57 };
59 i2c@3000 {
60 device_type = "i2c";
61 compatible = "fsl-i2c";
62 reg = <3000 100>;
63 interrupts = <e 8>;
64 interrupt-parent = < &ipic >;
65 dfsrr;
66 };
68 serial@4500 {
69 device_type = "serial";
70 compatible = "ns16550";
71 reg = <4500 100>;
72 clock-frequency = <0>;
73 interrupts = <9 8>;
74 interrupt-parent = < &ipic >;
75 };
77 serial@4600 {
78 device_type = "serial";
79 compatible = "ns16550";
80 reg = <4600 100>;
81 clock-frequency = <0>;
82 interrupts = <a 8>;
83 interrupt-parent = < &ipic >;
84 };
86 crypto@30000 {
87 device_type = "crypto";
88 model = "SEC2";
89 compatible = "talitos";
90 reg = <30000 7000>;
91 interrupts = <b 8>;
92 interrupt-parent = < &ipic >;
93 /* Rev. 2.2 */
94 num-channels = <1>;
95 channel-fifo-len = <18>;
96 exec-units-mask = <0000004c>;
97 descriptor-types-mask = <0122003f>;
98 };
100 ipic: pic@700 {
101 interrupt-controller;
102 #address-cells = <0>;
103 #interrupt-cells = <2>;
104 reg = <700 100>;
105 device_type = "ipic";
106 };
108 par_io@1400 {
109 reg = <1400 100>;
110 device_type = "par_io";
111 num-ports = <7>;
113 pio3: ucc_pin@03 {
114 pio-map = <
115 /* port pin dir open_drain assignment has_irq */
116 3 4 3 0 2 0 /* MDIO */
117 3 5 1 0 2 0 /* MDC */
118 0 d 2 0 1 0 /* RX_CLK (CLK9) */
119 3 18 2 0 1 0 /* TX_CLK (CLK10) */
120 1 1 1 0 1 0 /* TxD1 */
121 1 0 1 0 1 0 /* TxD0 */
122 1 1 1 0 1 0 /* TxD1 */
123 1 2 1 0 1 0 /* TxD2 */
124 1 3 1 0 1 0 /* TxD3 */
125 1 4 2 0 1 0 /* RxD0 */
126 1 5 2 0 1 0 /* RxD1 */
127 1 6 2 0 1 0 /* RxD2 */
128 1 7 2 0 1 0 /* RxD3 */
129 1 8 2 0 1 0 /* RX_ER */
130 1 9 1 0 1 0 /* TX_ER */
131 1 a 2 0 1 0 /* RX_DV */
132 1 b 2 0 1 0 /* COL */
133 1 c 1 0 1 0 /* TX_EN */
134 1 d 2 0 1 0>;/* CRS */
135 };
136 pio4: ucc_pin@04 {
137 pio-map = <
138 /* port pin dir open_drain assignment has_irq */
139 3 1f 2 0 1 0 /* RX_CLK (CLK7) */
140 3 6 2 0 1 0 /* TX_CLK (CLK8) */
141 1 12 1 0 1 0 /* TxD0 */
142 1 13 1 0 1 0 /* TxD1 */
143 1 14 1 0 1 0 /* TxD2 */
144 1 15 1 0 1 0 /* TxD3 */
145 1 16 2 0 1 0 /* RxD0 */
146 1 17 2 0 1 0 /* RxD1 */
147 1 18 2 0 1 0 /* RxD2 */
148 1 19 2 0 1 0 /* RxD3 */
149 1 1a 2 0 1 0 /* RX_ER */
150 1 1b 1 0 1 0 /* TX_ER */
151 1 1c 2 0 1 0 /* RX_DV */
152 1 1d 2 0 1 0 /* COL */
153 1 1e 1 0 1 0 /* TX_EN */
154 1 1f 2 0 1 0>;/* CRS */
155 };
156 };
157 };
159 qe@e0100000 {
160 #address-cells = <1>;
161 #size-cells = <1>;
162 device_type = "qe";
163 model = "QE";
164 ranges = <0 e0100000 00100000>;
165 reg = <e0100000 480>;
166 brg-frequency = <0>;
167 bus-frequency = <BCD3D80>;
169 muram@10000 {
170 device_type = "muram";
171 ranges = <0 00010000 00004000>;
173 data-only@0 {
174 reg = <0 4000>;
175 };
176 };
178 spi@4c0 {
179 device_type = "spi";
180 compatible = "fsl_spi";
181 reg = <4c0 40>;
182 interrupts = <2>;
183 interrupt-parent = < &qeic >;
184 mode = "cpu";
185 };
187 spi@500 {
188 device_type = "spi";
189 compatible = "fsl_spi";
190 reg = <500 40>;
191 interrupts = <1>;
192 interrupt-parent = < &qeic >;
193 mode = "cpu";
194 };
196 usb@6c0 {
197 device_type = "usb";
198 compatible = "qe_udc";
199 reg = <6c0 40 8B00 100>;
200 interrupts = <b>;
201 interrupt-parent = < &qeic >;
202 mode = "slave";
203 };
205 ucc@2200 {
206 device_type = "network";
207 compatible = "ucc_geth";
208 model = "UCC";
209 device-id = <3>;
210 reg = <2200 200>;
211 interrupts = <22>;
212 interrupt-parent = < &qeic >;
213 /*
214 * mac-address is deprecated and will be removed
215 * in 2.6.25. Only recent versions of
216 * U-Boot support local-mac-address, however.
217 */
218 mac-address = [ 00 00 00 00 00 00 ];
219 local-mac-address = [ 00 00 00 00 00 00 ];
220 rx-clock = <19>;
221 tx-clock = <1a>;
222 phy-handle = < &phy3 >;
223 pio-handle = < &pio3 >;
224 };
226 ucc@3200 {
227 device_type = "network";
228 compatible = "ucc_geth";
229 model = "UCC";
230 device-id = <4>;
231 reg = <3000 200>;
232 interrupts = <23>;
233 interrupt-parent = < &qeic >;
234 /*
235 * mac-address is deprecated and will be removed
236 * in 2.6.25. Only recent versions of
237 * U-Boot support local-mac-address, however.
238 */
239 mac-address = [ 00 00 00 00 00 00 ];
240 local-mac-address = [ 00 00 00 00 00 00 ];
241 rx-clock = <17>;
242 tx-clock = <18>;
243 phy-handle = < &phy4 >;
244 pio-handle = < &pio4 >;
245 };
247 mdio@2320 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 reg = <2320 18>;
251 device_type = "mdio";
252 compatible = "ucc_geth_phy";
254 phy3: ethernet-phy@03 {
255 interrupt-parent = < &ipic >;
256 interrupts = <11 8>;
257 reg = <3>;
258 device_type = "ethernet-phy";
259 };
260 phy4: ethernet-phy@04 {
261 interrupt-parent = < &ipic >;
262 interrupts = <12 8>;
263 reg = <4>;
264 device_type = "ethernet-phy";
265 };
266 };
268 qeic: qeic@80 {
269 interrupt-controller;
270 device_type = "qeic";
271 #address-cells = <0>;
272 #interrupt-cells = <1>;
273 reg = <80 80>;
274 big-endian;
275 interrupts = <20 8 21 8>; //high:32 low:33
276 interrupt-parent = < &ipic >;
277 };
278 };
280 pci@e0008500 {
281 interrupt-map-mask = <f800 0 0 7>;
282 interrupt-map = <
283 /* IDSEL 0x11 AD17 */
284 8800 0 0 1 &ipic 14 8
285 8800 0 0 2 &ipic 15 8
286 8800 0 0 3 &ipic 16 8
287 8800 0 0 4 &ipic 17 8
289 /* IDSEL 0x12 AD18 */
290 9000 0 0 1 &ipic 16 8
291 9000 0 0 2 &ipic 17 8
292 9000 0 0 3 &ipic 14 8
293 9000 0 0 4 &ipic 15 8
295 /* IDSEL 0x13 AD19 */
296 9800 0 0 1 &ipic 17 8
297 9800 0 0 2 &ipic 14 8
298 9800 0 0 3 &ipic 15 8
299 9800 0 0 4 &ipic 16 8
301 /* IDSEL 0x15 AD21*/
302 a800 0 0 1 &ipic 14 8
303 a800 0 0 2 &ipic 15 8
304 a800 0 0 3 &ipic 16 8
305 a800 0 0 4 &ipic 17 8
307 /* IDSEL 0x16 AD22*/
308 b000 0 0 1 &ipic 17 8
309 b000 0 0 2 &ipic 14 8
310 b000 0 0 3 &ipic 15 8
311 b000 0 0 4 &ipic 16 8
313 /* IDSEL 0x17 AD23*/
314 b800 0 0 1 &ipic 16 8
315 b800 0 0 2 &ipic 17 8
316 b800 0 0 3 &ipic 14 8
317 b800 0 0 4 &ipic 15 8
319 /* IDSEL 0x18 AD24*/
320 c000 0 0 1 &ipic 15 8
321 c000 0 0 2 &ipic 16 8
322 c000 0 0 3 &ipic 17 8
323 c000 0 0 4 &ipic 14 8>;
324 interrupt-parent = < &ipic >;
325 interrupts = <42 8>;
326 bus-range = <0 0>;
327 ranges = <02000000 0 90000000 90000000 0 10000000
328 42000000 0 80000000 80000000 0 10000000
329 01000000 0 00000000 d0000000 0 00100000>;
330 clock-frequency = <0>;
331 #interrupt-cells = <1>;
332 #size-cells = <2>;
333 #address-cells = <3>;
334 reg = <e0008500 100>;
335 compatible = "fsl,mpc8349-pci";
336 device_type = "pci";
337 };
338 };