| blob | 69ca5025d9723cc143b2e0e711c4ba50d6f0304f |
1 /*
2 * MPC8548 CDS Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
13 / {
14 model = "MPC8548CDS";
15 compatible = "MPC8548CDS", "MPC85xxCDS";
16 #address-cells = <1>;
17 #size-cells = <1>;
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
23 PowerPC,8548@0 {
24 device_type = "cpu";
25 reg = <0>;
26 d-cache-line-size = <20>; // 32 bytes
27 i-cache-line-size = <20>; // 32 bytes
28 d-cache-size = <8000>; // L1, 32K
29 i-cache-size = <8000>; // L1, 32K
30 timebase-frequency = <0>; // 33 MHz, from uboot
31 bus-frequency = <0>; // 166 MHz
32 clock-frequency = <0>; // 825 MHz, from uboot
33 };
34 };
36 memory {
37 device_type = "memory";
38 reg = <00000000 08000000>; // 128M at 0x0
39 };
41 soc8548@e0000000 {
42 #address-cells = <1>;
43 #size-cells = <1>;
44 device_type = "soc";
45 ranges = <00000000 e0000000 00100000>;
46 reg = <e0000000 00001000>; // CCSRBAR
47 bus-frequency = <0>;
49 memory-controller@2000 {
50 compatible = "fsl,8548-memory-controller";
51 reg = <2000 1000>;
52 interrupt-parent = <&mpic>;
53 interrupts = <12 2>;
54 };
56 l2-cache-controller@20000 {
57 compatible = "fsl,8548-l2-cache-controller";
58 reg = <20000 1000>;
59 cache-line-size = <20>; // 32 bytes
60 cache-size = <80000>; // L2, 512K
61 interrupt-parent = <&mpic>;
62 interrupts = <10 2>;
63 };
65 i2c@3000 {
66 device_type = "i2c";
67 compatible = "fsl-i2c";
68 reg = <3000 100>;
69 interrupts = <2b 2>;
70 interrupt-parent = <&mpic>;
71 dfsrr;
72 };
74 mdio@24520 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 device_type = "mdio";
78 compatible = "gianfar";
79 reg = <24520 20>;
80 phy0: ethernet-phy@0 {
81 interrupt-parent = <&mpic>;
82 interrupts = <5 1>;
83 reg = <0>;
84 device_type = "ethernet-phy";
85 };
86 phy1: ethernet-phy@1 {
87 interrupt-parent = <&mpic>;
88 interrupts = <5 1>;
89 reg = <1>;
90 device_type = "ethernet-phy";
91 };
92 phy2: ethernet-phy@2 {
93 interrupt-parent = <&mpic>;
94 interrupts = <5 1>;
95 reg = <2>;
96 device_type = "ethernet-phy";
97 };
98 phy3: ethernet-phy@3 {
99 interrupt-parent = <&mpic>;
100 interrupts = <5 1>;
101 reg = <3>;
102 device_type = "ethernet-phy";
103 };
104 };
106 ethernet@24000 {
107 #address-cells = <1>;
108 #size-cells = <0>;
109 device_type = "network";
110 model = "eTSEC";
111 compatible = "gianfar";
112 reg = <24000 1000>;
113 local-mac-address = [ 00 00 00 00 00 00 ];
114 interrupts = <1d 2 1e 2 22 2>;
115 interrupt-parent = <&mpic>;
116 phy-handle = <&phy0>;
117 };
119 ethernet@25000 {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 device_type = "network";
123 model = "eTSEC";
124 compatible = "gianfar";
125 reg = <25000 1000>;
126 local-mac-address = [ 00 00 00 00 00 00 ];
127 interrupts = <23 2 24 2 28 2>;
128 interrupt-parent = <&mpic>;
129 phy-handle = <&phy1>;
130 };
132 /* eTSEC 3/4 are currently broken
133 ethernet@26000 {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 device_type = "network";
137 model = "eTSEC";
138 compatible = "gianfar";
139 reg = <26000 1000>;
140 local-mac-address = [ 00 00 00 00 00 00 ];
141 interrupts = <1f 2 20 2 21 2>;
142 interrupt-parent = <&mpic>;
143 phy-handle = <&phy2>;
144 };
146 ethernet@27000 {
147 #address-cells = <1>;
148 #size-cells = <0>;
149 device_type = "network";
150 model = "eTSEC";
151 compatible = "gianfar";
152 reg = <27000 1000>;
153 local-mac-address = [ 00 00 00 00 00 00 ];
154 interrupts = <25 2 26 2 27 2>;
155 interrupt-parent = <&mpic>;
156 phy-handle = <&phy3>;
157 };
158 */
160 serial@4500 {
161 device_type = "serial";
162 compatible = "ns16550";
163 reg = <4500 100>; // reg base, size
164 clock-frequency = <0>; // should we fill in in uboot?
165 interrupts = <2a 2>;
166 interrupt-parent = <&mpic>;
167 };
169 serial@4600 {
170 device_type = "serial";
171 compatible = "ns16550";
172 reg = <4600 100>; // reg base, size
173 clock-frequency = <0>; // should we fill in in uboot?
174 interrupts = <2a 2>;
175 interrupt-parent = <&mpic>;
176 };
178 global-utilities@e0000 { //global utilities reg
179 compatible = "fsl,mpc8548-guts";
180 reg = <e0000 1000>;
181 fsl,has-rstcr;
182 };
184 mpic: pic@40000 {
185 clock-frequency = <0>;
186 interrupt-controller;
187 #address-cells = <0>;
188 #interrupt-cells = <2>;
189 reg = <40000 40000>;
190 compatible = "chrp,open-pic";
191 device_type = "open-pic";
192 big-endian;
193 };
194 };
196 pci@e0008000 {
197 interrupt-map-mask = <f800 0 0 7>;
198 interrupt-map = <
199 /* IDSEL 0x4 (PCIX Slot 2) */
200 02000 0 0 1 &mpic 0 1
201 02000 0 0 2 &mpic 1 1
202 02000 0 0 3 &mpic 2 1
203 02000 0 0 4 &mpic 3 1
205 /* IDSEL 0x5 (PCIX Slot 3) */
206 02800 0 0 1 &mpic 1 1
207 02800 0 0 2 &mpic 2 1
208 02800 0 0 3 &mpic 3 1
209 02800 0 0 4 &mpic 0 1
211 /* IDSEL 0x6 (PCIX Slot 4) */
212 03000 0 0 1 &mpic 2 1
213 03000 0 0 2 &mpic 3 1
214 03000 0 0 3 &mpic 0 1
215 03000 0 0 4 &mpic 1 1
217 /* IDSEL 0x8 (PCIX Slot 5) */
218 04000 0 0 1 &mpic 0 1
219 04000 0 0 2 &mpic 1 1
220 04000 0 0 3 &mpic 2 1
221 04000 0 0 4 &mpic 3 1
223 /* IDSEL 0xC (Tsi310 bridge) */
224 06000 0 0 1 &mpic 0 1
225 06000 0 0 2 &mpic 1 1
226 06000 0 0 3 &mpic 2 1
227 06000 0 0 4 &mpic 3 1
229 /* IDSEL 0x14 (Slot 2) */
230 0a000 0 0 1 &mpic 0 1
231 0a000 0 0 2 &mpic 1 1
232 0a000 0 0 3 &mpic 2 1
233 0a000 0 0 4 &mpic 3 1
235 /* IDSEL 0x15 (Slot 3) */
236 0a800 0 0 1 &mpic 1 1
237 0a800 0 0 2 &mpic 2 1
238 0a800 0 0 3 &mpic 3 1
239 0a800 0 0 4 &mpic 0 1
241 /* IDSEL 0x16 (Slot 4) */
242 0b000 0 0 1 &mpic 2 1
243 0b000 0 0 2 &mpic 3 1
244 0b000 0 0 3 &mpic 0 1
245 0b000 0 0 4 &mpic 1 1
247 /* IDSEL 0x18 (Slot 5) */
248 0c000 0 0 1 &mpic 0 1
249 0c000 0 0 2 &mpic 1 1
250 0c000 0 0 3 &mpic 2 1
251 0c000 0 0 4 &mpic 3 1
253 /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
254 0E000 0 0 1 &mpic 0 1
255 0E000 0 0 2 &mpic 1 1
256 0E000 0 0 3 &mpic 2 1
257 0E000 0 0 4 &mpic 3 1>;
259 interrupt-parent = <&mpic>;
260 interrupts = <18 2>;
261 bus-range = <0 0>;
262 ranges = <02000000 0 80000000 80000000 0 10000000
263 01000000 0 00000000 e2000000 0 00800000>;
264 clock-frequency = <3f940aa>;
265 #interrupt-cells = <1>;
266 #size-cells = <2>;
267 #address-cells = <3>;
268 reg = <e0008000 1000>;
269 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
270 device_type = "pci";
272 pci_bridge@1c {
273 interrupt-map-mask = <f800 0 0 7>;
274 interrupt-map = <
276 /* IDSEL 0x00 (PrPMC Site) */
277 0000 0 0 1 &mpic 0 1
278 0000 0 0 2 &mpic 1 1
279 0000 0 0 3 &mpic 2 1
280 0000 0 0 4 &mpic 3 1
282 /* IDSEL 0x04 (VIA chip) */
283 2000 0 0 1 &mpic 0 1
284 2000 0 0 2 &mpic 1 1
285 2000 0 0 3 &mpic 2 1
286 2000 0 0 4 &mpic 3 1
288 /* IDSEL 0x05 (8139) */
289 2800 0 0 1 &mpic 1 1
291 /* IDSEL 0x06 (Slot 6) */
292 3000 0 0 1 &mpic 2 1
293 3000 0 0 2 &mpic 3 1
294 3000 0 0 3 &mpic 0 1
295 3000 0 0 4 &mpic 1 1
297 /* IDESL 0x07 (Slot 7) */
298 3800 0 0 1 &mpic 3 1
299 3800 0 0 2 &mpic 0 1
300 3800 0 0 3 &mpic 1 1
301 3800 0 0 4 &mpic 2 1>;
303 reg = <e000 0 0 0 0>;
304 #interrupt-cells = <1>;
305 #size-cells = <2>;
306 #address-cells = <3>;
307 ranges = <02000000 0 80000000
308 02000000 0 80000000
309 0 20000000
310 01000000 0 00000000
311 01000000 0 00000000
312 0 00080000>;
313 clock-frequency = <1fca055>;
315 isa@4 {
316 device_type = "isa";
317 #interrupt-cells = <2>;
318 #size-cells = <1>;
319 #address-cells = <2>;
320 reg = <2000 0 0 0 0>;
321 ranges = <1 0 01000000 0 0 00001000>;
322 interrupt-parent = <&i8259>;
324 i8259: interrupt-controller@20 {
325 interrupt-controller;
326 device_type = "interrupt-controller";
327 reg = <1 20 2
328 1 a0 2
329 1 4d0 2>;
330 #address-cells = <0>;
331 #interrupt-cells = <2>;
332 compatible = "chrp,iic";
333 interrupts = <0 1>;
334 interrupt-parent = <&mpic>;
335 };
337 rtc@70 {
338 compatible = "pnpPNP,b00";
339 reg = <1 70 2>;
340 };
341 };
342 };
343 };
345 pci@e0009000 {
346 interrupt-map-mask = <f800 0 0 7>;
347 interrupt-map = <
349 /* IDSEL 0x15 */
350 a800 0 0 1 &mpic b 1
351 a800 0 0 2 &mpic 1 1
352 a800 0 0 3 &mpic 2 1
353 a800 0 0 4 &mpic 3 1>;
355 interrupt-parent = <&mpic>;
356 interrupts = <19 2>;
357 bus-range = <0 0>;
358 ranges = <02000000 0 90000000 90000000 0 10000000
359 01000000 0 00000000 e2800000 0 00800000>;
360 clock-frequency = <3f940aa>;
361 #interrupt-cells = <1>;
362 #size-cells = <2>;
363 #address-cells = <3>;
364 reg = <e0009000 1000>;
365 compatible = "fsl,mpc8540-pci";
366 device_type = "pci";
367 };
369 pcie@e000a000 {
370 interrupt-map-mask = <f800 0 0 7>;
371 interrupt-map = <
373 /* IDSEL 0x0 (PEX) */
374 00000 0 0 1 &mpic 0 1
375 00000 0 0 2 &mpic 1 1
376 00000 0 0 3 &mpic 2 1
377 00000 0 0 4 &mpic 3 1>;
379 interrupt-parent = <&mpic>;
380 interrupts = <1a 2>;
381 bus-range = <0 ff>;
382 ranges = <02000000 0 a0000000 a0000000 0 20000000
383 01000000 0 00000000 e3000000 0 08000000>;
384 clock-frequency = <1fca055>;
385 #interrupt-cells = <1>;
386 #size-cells = <2>;
387 #address-cells = <3>;
388 reg = <e000a000 1000>;
389 compatible = "fsl,mpc8548-pcie";
390 device_type = "pci";
391 pcie@0 {
392 reg = <0 0 0 0 0>;
393 #size-cells = <2>;
394 #address-cells = <3>;
395 device_type = "pci";
396 ranges = <02000000 0 a0000000
397 02000000 0 a0000000
398 0 20000000
400 01000000 0 00000000
401 01000000 0 00000000
402 0 08000000>;
403 };
404 };
405 };