arch/powerpc/oprofile/op_model_fsl_booke.c

   1 /*
   2  * arch/powerpc/oprofile/op_model_fsl_booke.c
   3  *
   4  * Freescale Book-E oprofile support, based on ppc64 oprofile support
   5  * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
   6  *
   7  * Copyright (c) 2004 Freescale Semiconductor, Inc
   8  *
   9  * Author: Andy Fleming
  10  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version
  15  * 2 of the License, or (at your option) any later version.
  16  */
  17
  18 #include <linux/oprofile.h>
  19 #include <linux/init.h>
  20 #include <linux/smp.h>
  21 #include <asm/ptrace.h>
  22 #include <asm/system.h>
  23 #include <asm/processor.h>
  24 #include <asm/cputable.h>
  25 #include <asm/reg_booke.h>
  26 #include <asm/page.h>
  27 #include <asm/pmc.h>
  28 #include <asm/oprofile_impl.h>
  29
  30 static unsigned long reset_value[OP_MAX_COUNTER];
  31
  32 static int num_counters;
  33 static int oprofile_running;
  34
  35 static inline u32 get_pmlca(int ctr)
  36 {
  37         u32 pmlca;
  38
  39         switch (ctr) {
  40                 case 0:
  41                         pmlca = mfpmr(PMRN_PMLCA0);
  42                         break;
  43                 case 1:
  44                         pmlca = mfpmr(PMRN_PMLCA1);
  45                         break;
  46                 case 2:
  47                         pmlca = mfpmr(PMRN_PMLCA2);
  48                         break;
  49                 case 3:
  50                         pmlca = mfpmr(PMRN_PMLCA3);
  51                         break;
  52                 default:
  53                         panic("Bad ctr number\n");
  54         }
  55
  56         return pmlca;
  57 }
  58
  59 static inline void set_pmlca(int ctr, u32 pmlca)
  60 {
  61         switch (ctr) {
  62                 case 0:
  63                         mtpmr(PMRN_PMLCA0, pmlca);
  64                         break;
  65                 case 1:
  66                         mtpmr(PMRN_PMLCA1, pmlca);
  67                         break;
  68                 case 2:
  69                         mtpmr(PMRN_PMLCA2, pmlca);
  70                         break;
  71                 case 3:
  72                         mtpmr(PMRN_PMLCA3, pmlca);
  73                         break;
  74                 default:
  75                         panic("Bad ctr number\n");
  76         }
  77 }
  78
  79 static inline unsigned int ctr_read(unsigned int i)
  80 {
  81         switch(i) {
  82                 case 0:
  83                         return mfpmr(PMRN_PMC0);
  84                 case 1:
  85                         return mfpmr(PMRN_PMC1);
  86                 case 2:
  87                         return mfpmr(PMRN_PMC2);
  88                 case 3:
  89                         return mfpmr(PMRN_PMC3);
  90                 default:
  91                         return 0;
  92         }
  93 }
  94
  95 static inline void ctr_write(unsigned int i, unsigned int val)
  96 {
  97         switch(i) {
  98                 case 0:
  99                         mtpmr(PMRN_PMC0, val);
 100                         break;
 101                 case 1:
 102                         mtpmr(PMRN_PMC1, val);
 103                         break;
 104                 case 2:
 105                         mtpmr(PMRN_PMC2, val);
 106                         break;
 107                 case 3:
 108                         mtpmr(PMRN_PMC3, val);
 109                         break;
 110                 default:
 111                         break;
 112         }
 113 }
 114
 115
 116 static void init_pmc_stop(int ctr)
 117 {
 118         u32 pmlca = (PMLCA_FC | PMLCA_FCS | PMLCA_FCU |
 119                         PMLCA_FCM1 | PMLCA_FCM0);
 120         u32 pmlcb = 0;
 121
 122         switch (ctr) {
 123                 case 0:
 124                         mtpmr(PMRN_PMLCA0, pmlca);
 125                         mtpmr(PMRN_PMLCB0, pmlcb);
 126                         break;
 127                 case 1:
 128                         mtpmr(PMRN_PMLCA1, pmlca);
 129                         mtpmr(PMRN_PMLCB1, pmlcb);
 130                         break;
 131                 case 2:
 132                         mtpmr(PMRN_PMLCA2, pmlca);
 133                         mtpmr(PMRN_PMLCB2, pmlcb);
 134                         break;
 135                 case 3:
 136                         mtpmr(PMRN_PMLCA3, pmlca);
 137                         mtpmr(PMRN_PMLCB3, pmlcb);
 138                         break;
 139                 default:
 140                         panic("Bad ctr number!\n");
 141         }
 142 }
 143
 144 static void set_pmc_event(int ctr, int event)
 145 {
 146         u32 pmlca;
 147
 148         pmlca = get_pmlca(ctr);
 149
 150         pmlca = (pmlca & ~PMLCA_EVENT_MASK) |
 151                 ((event << PMLCA_EVENT_SHIFT) &
 152                  PMLCA_EVENT_MASK);
 153
 154         set_pmlca(ctr, pmlca);
 155 }
 156
 157 static void set_pmc_user_kernel(int ctr, int user, int kernel)
 158 {
 159         u32 pmlca;
 160
 161         pmlca = get_pmlca(ctr);
 162
 163         if(user)
 164                 pmlca &= ~PMLCA_FCU;
 165         else
 166                 pmlca |= PMLCA_FCU;
 167
 168         if(kernel)
 169                 pmlca &= ~PMLCA_FCS;
 170         else
 171                 pmlca |= PMLCA_FCS;
 172
 173         set_pmlca(ctr, pmlca);
 174 }
 175
 176 static void set_pmc_marked(int ctr, int mark0, int mark1)
 177 {
 178         u32 pmlca = get_pmlca(ctr);
 179
 180         if(mark0)
 181                 pmlca &= ~PMLCA_FCM0;
 182         else
 183                 pmlca |= PMLCA_FCM0;
 184
 185         if(mark1)
 186                 pmlca &= ~PMLCA_FCM1;
 187         else
 188                 pmlca |= PMLCA_FCM1;
 189
 190         set_pmlca(ctr, pmlca);
 191 }
 192
 193 static void pmc_start_ctr(int ctr, int enable)
 194 {
 195         u32 pmlca = get_pmlca(ctr);
 196
 197         pmlca &= ~PMLCA_FC;
 198
 199         if (enable)
 200                 pmlca |= PMLCA_CE;
 201         else
 202                 pmlca &= ~PMLCA_CE;
 203
 204         set_pmlca(ctr, pmlca);
 205 }
 206
 207 static void pmc_start_ctrs(int enable)
 208 {
 209         u32 pmgc0 = mfpmr(PMRN_PMGC0);
 210
 211         pmgc0 &= ~PMGC0_FAC;
 212         pmgc0 |= PMGC0_FCECE;
 213
 214         if (enable)
 215                 pmgc0 |= PMGC0_PMIE;
 216         else
 217                 pmgc0 &= ~PMGC0_PMIE;
 218
 219         mtpmr(PMRN_PMGC0, pmgc0);
 220 }
 221
 222 static void pmc_stop_ctrs(void)
 223 {
 224         u32 pmgc0 = mfpmr(PMRN_PMGC0);
 225
 226         pmgc0 |= PMGC0_FAC;
 227
 228         pmgc0 &= ~(PMGC0_PMIE | PMGC0_FCECE);
 229
 230         mtpmr(PMRN_PMGC0, pmgc0);
 231 }
 232
 233 static void dump_pmcs(void)
 234 {
 235         printk("pmgc0: %x\n", mfpmr(PMRN_PMGC0));
 236         printk("pmc\t\tpmlca\t\tpmlcb\n");
 237         printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC0),
 238                         mfpmr(PMRN_PMLCA0), mfpmr(PMRN_PMLCB0));
 239         printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC1),
 240                         mfpmr(PMRN_PMLCA1), mfpmr(PMRN_PMLCB1));
 241         printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC2),
 242                         mfpmr(PMRN_PMLCA2), mfpmr(PMRN_PMLCB2));
 243         printk("%8x\t%8x\t%8x\n", mfpmr(PMRN_PMC3),
 244                         mfpmr(PMRN_PMLCA3), mfpmr(PMRN_PMLCB3));
 245 }
 246
 247 static int fsl_booke_cpu_setup(struct op_counter_config *ctr)
 248 {
 249         int i;
 250
 251         /* freeze all counters */
 252         pmc_stop_ctrs();
 253
 254         for (i = 0;i < num_counters;i++) {
 255                 init_pmc_stop(i);
 256
 257                 set_pmc_event(i, ctr[i].event);
 258
 259                 set_pmc_user_kernel(i, ctr[i].user, ctr[i].kernel);
 260         }
 261
 262         return 0;
 263 }
 264
 265 static int fsl_booke_reg_setup(struct op_counter_config *ctr,
 266                              struct op_system_config *sys,
 267                              int num_ctrs)
 268 {
 269         int i;
 270
 271         num_counters = num_ctrs;
 272
 273         /* Our counters count up, and "count" refers to
 274          * how much before the next interrupt, and we interrupt
 275          * on overflow.  So we calculate the starting value
 276          * which will give us "count" until overflow.
 277          * Then we set the events on the enabled counters */
 278         for (i = 0; i < num_counters; ++i)
 279                 reset_value[i] = 0x80000000UL - ctr[i].count;
 280
 281         return 0;
 282 }
 283
 284 static int fsl_booke_start(struct op_counter_config *ctr)
 285 {
 286         int i;
 287
 288         mtmsr(mfmsr() | MSR_PMM);
 289
 290         for (i = 0; i < num_counters; ++i) {
 291                 if (ctr[i].enabled) {
 292                         ctr_write(i, reset_value[i]);
 293                         /* Set each enabled counter to only
 294                          * count when the Mark bit is *not* set */
 295                         set_pmc_marked(i, 1, 0);
 296                         pmc_start_ctr(i, 1);
 297                 } else {
 298                         ctr_write(i, 0);
 299
 300                         /* Set the ctr to be stopped */
 301                         pmc_start_ctr(i, 0);
 302                 }
 303         }
 304
 305         /* Clear the freeze bit, and enable the interrupt.
 306          * The counters won't actually start until the rfi clears
 307          * the PMM bit */
 308         pmc_start_ctrs(1);
 309
 310         oprofile_running = 1;
 311
 312         pr_debug("start on cpu %d, pmgc0 %x\n", smp_processor_id(),
 313                         mfpmr(PMRN_PMGC0));
 314
 315         return 0;
 316 }
 317
 318 static void fsl_booke_stop(void)
 319 {
 320         /* freeze counters */
 321         pmc_stop_ctrs();
 322
 323         oprofile_running = 0;
 324
 325         pr_debug("stop on cpu %d, pmgc0 %x\n", smp_processor_id(),
 326                         mfpmr(PMRN_PMGC0));
 327
 328         mb();
 329 }
 330
 331
 332 static void fsl_booke_handle_interrupt(struct pt_regs *regs,
 333                                     struct op_counter_config *ctr)
 334 {
 335         unsigned long pc;
 336         int is_kernel;
 337         int val;
 338         int i;
 339
 340         /* set the PMM bit (see comment below) */
 341         mtmsr(mfmsr() | MSR_PMM);
 342
 343         pc = regs->nip;
 344         is_kernel = is_kernel_addr(pc);
 345
 346         for (i = 0; i < num_counters; ++i) {
 347                 val = ctr_read(i);
 348                 if (val < 0) {
 349                         if (oprofile_running && ctr[i].enabled) {
 350                                 oprofile_add_ext_sample(pc, regs, i, is_kernel);
 351                                 ctr_write(i, reset_value[i]);
 352                         } else {
 353                                 ctr_write(i, 0);
 354                         }
 355                 }
 356         }
 357
 358         /* The freeze bit was set by the interrupt. */
 359         /* Clear the freeze bit, and reenable the interrupt.
 360          * The counters won't actually start until the rfi clears
 361          * the PMM bit */
 362         pmc_start_ctrs(1);
 363 }
 364
 365 struct op_powerpc_model op_model_fsl_booke = {
 366         .reg_setup              = fsl_booke_reg_setup,
 367         .cpu_setup              = fsl_booke_cpu_setup,
 368         .start                  = fsl_booke_start,
 369         .stop                   = fsl_booke_stop,
 370         .handle_interrupt       = fsl_booke_handle_interrupt,
 371 };