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x86: implement gbpages support in change_page_attr()
[wrt350n-kernel.git] / include / asm-s390 / bitops.h
blobdba6fecad0be25353c535ddc1ac3feb64341dbcd
1 #ifndef _S390_BITOPS_H
2 #define _S390_BITOPS_H
3
4 /*
5 * include/asm-s390/bitops.h
6 *
7 * S390 version
8 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
9 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
10 *
11 * Derived from "include/asm-i386/bitops.h"
12 * Copyright (C) 1992, Linus Torvalds
13 *
14 */
15
16 #ifdef __KERNEL__
17
18 #ifndef _LINUX_BITOPS_H
19 #error only <linux/bitops.h> can be included directly
20 #endif
21
22 #include <linux/compiler.h>
23
24 /*
25 * 32 bit bitops format:
26 * bit 0 is the LSB of *addr; bit 31 is the MSB of *addr;
27 * bit 32 is the LSB of *(addr+4). That combined with the
28 * big endian byte order on S390 give the following bit
29 * order in memory:
30 * 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10 \
31 * 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00
32 * after that follows the next long with bit numbers
33 * 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30
34 * 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20
35 * The reason for this bit ordering is the fact that
36 * in the architecture independent code bits operations
37 * of the form "flags |= (1 << bitnr)" are used INTERMIXED
38 * with operation of the form "set_bit(bitnr, flags)".
39 *
40 * 64 bit bitops format:
41 * bit 0 is the LSB of *addr; bit 63 is the MSB of *addr;
42 * bit 64 is the LSB of *(addr+8). That combined with the
43 * big endian byte order on S390 give the following bit
44 * order in memory:
45 * 3f 3e 3d 3c 3b 3a 39 38 37 36 35 34 33 32 31 30
46 * 2f 2e 2d 2c 2b 2a 29 28 27 26 25 24 23 22 21 20
47 * 1f 1e 1d 1c 1b 1a 19 18 17 16 15 14 13 12 11 10
48 * 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00
49 * after that follows the next long with bit numbers
50 * 7f 7e 7d 7c 7b 7a 79 78 77 76 75 74 73 72 71 70
51 * 6f 6e 6d 6c 6b 6a 69 68 67 66 65 64 63 62 61 60
52 * 5f 5e 5d 5c 5b 5a 59 58 57 56 55 54 53 52 51 50
53 * 4f 4e 4d 4c 4b 4a 49 48 47 46 45 44 43 42 41 40
54 * The reason for this bit ordering is the fact that
55 * in the architecture independent code bits operations
56 * of the form "flags |= (1 << bitnr)" are used INTERMIXED
57 * with operation of the form "set_bit(bitnr, flags)".
58 */
59
60 /* bitmap tables from arch/S390/kernel/bitmap.S */
61 extern const char _oi_bitmap[];
62 extern const char _ni_bitmap[];
63 extern const char _zb_findmap[];
64 extern const char _sb_findmap[];
65
66 #ifndef __s390x__
67
68 #define __BITOPS_ALIGN 3
69 #define __BITOPS_WORDSIZE 32
70 #define __BITOPS_OR "or"
71 #define __BITOPS_AND "nr"
72 #define __BITOPS_XOR "xr"
73
74 #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
75
76 #define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
77 asm volatile( \
78 " l %0,%2\n" \
79 "0: lr %1,%0\n" \
80 __op_string " %1,%3\n" \
81 " cs %0,%1,%2\n" \
82 " jl 0b" \
83 : "=&d" (__old), "=&d" (__new), \
84 "=Q" (*(unsigned long *) __addr) \
85 : "d" (__val), "Q" (*(unsigned long *) __addr) \
86 : "cc");
87
88 #else /* __GNUC__ */
89
90 #define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
91 asm volatile( \
92 " l %0,0(%4)\n" \
93 "0: lr %1,%0\n" \
94 __op_string " %1,%3\n" \
95 " cs %0,%1,0(%4)\n" \
96 " jl 0b" \
97 : "=&d" (__old), "=&d" (__new), \
98 "=m" (*(unsigned long *) __addr) \
99 : "d" (__val), "a" (__addr), \
100 "m" (*(unsigned long *) __addr) : "cc");
101
102 #endif /* __GNUC__ */
103
104 #else /* __s390x__ */
105
106 #define __BITOPS_ALIGN 7
107 #define __BITOPS_WORDSIZE 64
108 #define __BITOPS_OR "ogr"
109 #define __BITOPS_AND "ngr"
110 #define __BITOPS_XOR "xgr"
111
112 #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
113
114 #define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
115 asm volatile( \
116 " lg %0,%2\n" \
117 "0: lgr %1,%0\n" \
118 __op_string " %1,%3\n" \
119 " csg %0,%1,%2\n" \
120 " jl 0b" \
121 : "=&d" (__old), "=&d" (__new), \
122 "=Q" (*(unsigned long *) __addr) \
123 : "d" (__val), "Q" (*(unsigned long *) __addr) \
124 : "cc");
125
126 #else /* __GNUC__ */
127
128 #define __BITOPS_LOOP(__old, __new, __addr, __val, __op_string) \
129 asm volatile( \
130 " lg %0,0(%4)\n" \
131 "0: lgr %1,%0\n" \
132 __op_string " %1,%3\n" \
133 " csg %0,%1,0(%4)\n" \
134 " jl 0b" \
135 : "=&d" (__old), "=&d" (__new), \
136 "=m" (*(unsigned long *) __addr) \
137 : "d" (__val), "a" (__addr), \
138 "m" (*(unsigned long *) __addr) : "cc");
139
140
141 #endif /* __GNUC__ */
142
143 #endif /* __s390x__ */
144
145 #define __BITOPS_WORDS(bits) (((bits)+__BITOPS_WORDSIZE-1)/__BITOPS_WORDSIZE)
146 #define __BITOPS_BARRIER() asm volatile("" : : : "memory")
147
148 #ifdef CONFIG_SMP
149 /*
150 * SMP safe set_bit routine based on compare and swap (CS)
151 */
152 static inline void set_bit_cs(unsigned long nr, volatile unsigned long *ptr)
153 {
154 unsigned long addr, old, new, mask;
155
156 addr = (unsigned long) ptr;
157 /* calculate address for CS */
158 addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
159 /* make OR mask */
160 mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
161 /* Do the atomic update. */
162 __BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR);
163 }
164
165 /*
166 * SMP safe clear_bit routine based on compare and swap (CS)
167 */
168 static inline void clear_bit_cs(unsigned long nr, volatile unsigned long *ptr)
169 {
170 unsigned long addr, old, new, mask;
171
172 addr = (unsigned long) ptr;
173 /* calculate address for CS */
174 addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
175 /* make AND mask */
176 mask = ~(1UL << (nr & (__BITOPS_WORDSIZE - 1)));
177 /* Do the atomic update. */
178 __BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND);
179 }
180
181 /*
182 * SMP safe change_bit routine based on compare and swap (CS)
183 */
184 static inline void change_bit_cs(unsigned long nr, volatile unsigned long *ptr)
185 {
186 unsigned long addr, old, new, mask;
187
188 addr = (unsigned long) ptr;
189 /* calculate address for CS */
190 addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
191 /* make XOR mask */
192 mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
193 /* Do the atomic update. */
194 __BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR);
195 }
196
197 /*
198 * SMP safe test_and_set_bit routine based on compare and swap (CS)
199 */
200 static inline int
201 test_and_set_bit_cs(unsigned long nr, volatile unsigned long *ptr)
202 {
203 unsigned long addr, old, new, mask;
204
205 addr = (unsigned long) ptr;
206 /* calculate address for CS */
207 addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
208 /* make OR/test mask */
209 mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
210 /* Do the atomic update. */
211 __BITOPS_LOOP(old, new, addr, mask, __BITOPS_OR);
212 __BITOPS_BARRIER();
213 return (old & mask) != 0;
214 }
215
216 /*
217 * SMP safe test_and_clear_bit routine based on compare and swap (CS)
218 */
219 static inline int
220 test_and_clear_bit_cs(unsigned long nr, volatile unsigned long *ptr)
221 {
222 unsigned long addr, old, new, mask;
223
224 addr = (unsigned long) ptr;
225 /* calculate address for CS */
226 addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
227 /* make AND/test mask */
228 mask = ~(1UL << (nr & (__BITOPS_WORDSIZE - 1)));
229 /* Do the atomic update. */
230 __BITOPS_LOOP(old, new, addr, mask, __BITOPS_AND);
231 __BITOPS_BARRIER();
232 return (old ^ new) != 0;
233 }
234
235 /*
236 * SMP safe test_and_change_bit routine based on compare and swap (CS)
237 */
238 static inline int
239 test_and_change_bit_cs(unsigned long nr, volatile unsigned long *ptr)
240 {
241 unsigned long addr, old, new, mask;
242
243 addr = (unsigned long) ptr;
244 /* calculate address for CS */
245 addr += (nr ^ (nr & (__BITOPS_WORDSIZE - 1))) >> 3;
246 /* make XOR/test mask */
247 mask = 1UL << (nr & (__BITOPS_WORDSIZE - 1));
248 /* Do the atomic update. */
249 __BITOPS_LOOP(old, new, addr, mask, __BITOPS_XOR);
250 __BITOPS_BARRIER();
251 return (old & mask) != 0;
252 }
253 #endif /* CONFIG_SMP */
254
255 /*
256 * fast, non-SMP set_bit routine
257 */
258 static inline void __set_bit(unsigned long nr, volatile unsigned long *ptr)
259 {
260 unsigned long addr;
261
262 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
263 asm volatile(
264 " oc 0(1,%1),0(%2)"
265 : "=m" (*(char *) addr) : "a" (addr),
266 "a" (_oi_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc" );
267 }
268
269 static inline void
270 __constant_set_bit(const unsigned long nr, volatile unsigned long *ptr)
271 {
272 unsigned long addr;
273
274 addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
275 *(unsigned char *) addr |= 1 << (nr & 7);
276 }
277
278 #define set_bit_simple(nr,addr) \
279 (__builtin_constant_p((nr)) ? \
280 __constant_set_bit((nr),(addr)) : \
281 __set_bit((nr),(addr)) )
282
283 /*
284 * fast, non-SMP clear_bit routine
285 */
286 static inline void
287 __clear_bit(unsigned long nr, volatile unsigned long *ptr)
288 {
289 unsigned long addr;
290
291 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
292 asm volatile(
293 " nc 0(1,%1),0(%2)"
294 : "=m" (*(char *) addr) : "a" (addr),
295 "a" (_ni_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc");
296 }
297
298 static inline void
299 __constant_clear_bit(const unsigned long nr, volatile unsigned long *ptr)
300 {
301 unsigned long addr;
302
303 addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
304 *(unsigned char *) addr &= ~(1 << (nr & 7));
305 }
306
307 #define clear_bit_simple(nr,addr) \
308 (__builtin_constant_p((nr)) ? \
309 __constant_clear_bit((nr),(addr)) : \
310 __clear_bit((nr),(addr)) )
311
312 /*
313 * fast, non-SMP change_bit routine
314 */
315 static inline void __change_bit(unsigned long nr, volatile unsigned long *ptr)
316 {
317 unsigned long addr;
318
319 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
320 asm volatile(
321 " xc 0(1,%1),0(%2)"
322 : "=m" (*(char *) addr) : "a" (addr),
323 "a" (_oi_bitmap + (nr & 7)), "m" (*(char *) addr) : "cc" );
324 }
325
326 static inline void
327 __constant_change_bit(const unsigned long nr, volatile unsigned long *ptr)
328 {
329 unsigned long addr;
330
331 addr = ((unsigned long) ptr) + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
332 *(unsigned char *) addr ^= 1 << (nr & 7);
333 }
334
335 #define change_bit_simple(nr,addr) \
336 (__builtin_constant_p((nr)) ? \
337 __constant_change_bit((nr),(addr)) : \
338 __change_bit((nr),(addr)) )
339
340 /*
341 * fast, non-SMP test_and_set_bit routine
342 */
343 static inline int
344 test_and_set_bit_simple(unsigned long nr, volatile unsigned long *ptr)
345 {
346 unsigned long addr;
347 unsigned char ch;
348
349 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
350 ch = *(unsigned char *) addr;
351 asm volatile(
352 " oc 0(1,%1),0(%2)"
353 : "=m" (*(char *) addr)
354 : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
355 "m" (*(char *) addr) : "cc", "memory");
356 return (ch >> (nr & 7)) & 1;
357 }
358 #define __test_and_set_bit(X,Y) test_and_set_bit_simple(X,Y)
359
360 /*
361 * fast, non-SMP test_and_clear_bit routine
362 */
363 static inline int
364 test_and_clear_bit_simple(unsigned long nr, volatile unsigned long *ptr)
365 {
366 unsigned long addr;
367 unsigned char ch;
368
369 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
370 ch = *(unsigned char *) addr;
371 asm volatile(
372 " nc 0(1,%1),0(%2)"
373 : "=m" (*(char *) addr)
374 : "a" (addr), "a" (_ni_bitmap + (nr & 7)),
375 "m" (*(char *) addr) : "cc", "memory");
376 return (ch >> (nr & 7)) & 1;
377 }
378 #define __test_and_clear_bit(X,Y) test_and_clear_bit_simple(X,Y)
379
380 /*
381 * fast, non-SMP test_and_change_bit routine
382 */
383 static inline int
384 test_and_change_bit_simple(unsigned long nr, volatile unsigned long *ptr)
385 {
386 unsigned long addr;
387 unsigned char ch;
388
389 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
390 ch = *(unsigned char *) addr;
391 asm volatile(
392 " xc 0(1,%1),0(%2)"
393 : "=m" (*(char *) addr)
394 : "a" (addr), "a" (_oi_bitmap + (nr & 7)),
395 "m" (*(char *) addr) : "cc", "memory");
396 return (ch >> (nr & 7)) & 1;
397 }
398 #define __test_and_change_bit(X,Y) test_and_change_bit_simple(X,Y)
399
400 #ifdef CONFIG_SMP
401 #define set_bit set_bit_cs
402 #define clear_bit clear_bit_cs
403 #define change_bit change_bit_cs
404 #define test_and_set_bit test_and_set_bit_cs
405 #define test_and_clear_bit test_and_clear_bit_cs
406 #define test_and_change_bit test_and_change_bit_cs
407 #else
408 #define set_bit set_bit_simple
409 #define clear_bit clear_bit_simple
410 #define change_bit change_bit_simple
411 #define test_and_set_bit test_and_set_bit_simple
412 #define test_and_clear_bit test_and_clear_bit_simple
413 #define test_and_change_bit test_and_change_bit_simple
414 #endif
415
416
417 /*
418 * This routine doesn't need to be atomic.
419 */
420
421 static inline int __test_bit(unsigned long nr, const volatile unsigned long *ptr)
422 {
423 unsigned long addr;
424 unsigned char ch;
425
426 addr = (unsigned long) ptr + ((nr ^ (__BITOPS_WORDSIZE - 8)) >> 3);
427 ch = *(volatile unsigned char *) addr;
428 return (ch >> (nr & 7)) & 1;
429 }
430
431 static inline int
432 __constant_test_bit(unsigned long nr, const volatile unsigned long *addr) {
433 return (((volatile char *) addr)
434 [(nr^(__BITOPS_WORDSIZE-8))>>3] & (1<<(nr&7))) != 0;
435 }
436
437 #define test_bit(nr,addr) \
438 (__builtin_constant_p((nr)) ? \
439 __constant_test_bit((nr),(addr)) : \
440 __test_bit((nr),(addr)) )
441
442 /*
443 * ffz = Find First Zero in word. Undefined if no zero exists,
444 * so code should check against ~0UL first..
445 */
446 static inline unsigned long ffz(unsigned long word)
447 {
448 unsigned long bit = 0;
449
450 #ifdef __s390x__
451 if (likely((word & 0xffffffff) == 0xffffffff)) {
452 word >>= 32;
453 bit += 32;
454 }
455 #endif
456 if (likely((word & 0xffff) == 0xffff)) {
457 word >>= 16;
458 bit += 16;
459 }
460 if (likely((word & 0xff) == 0xff)) {
461 word >>= 8;
462 bit += 8;
463 }
464 return bit + _zb_findmap[word & 0xff];
465 }
466
467 /*
468 * __ffs = find first bit in word. Undefined if no bit exists,
469 * so code should check against 0UL first..
470 */
471 static inline unsigned long __ffs (unsigned long word)
472 {
473 unsigned long bit = 0;
474
475 #ifdef __s390x__
476 if (likely((word & 0xffffffff) == 0)) {
477 word >>= 32;
478 bit += 32;
479 }
480 #endif
481 if (likely((word & 0xffff) == 0)) {
482 word >>= 16;
483 bit += 16;
484 }
485 if (likely((word & 0xff) == 0)) {
486 word >>= 8;
487 bit += 8;
488 }
489 return bit + _sb_findmap[word & 0xff];
490 }
491
492 /*
493 * Find-bit routines..
494 */
495
496 #ifndef __s390x__
497
498 static inline int
499 find_first_zero_bit(const unsigned long * addr, unsigned long size)
500 {
501 typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
502 unsigned long cmp, count;
503 unsigned int res;
504
505 if (!size)
506 return 0;
507 asm volatile(
508 " lhi %1,-1\n"
509 " lr %2,%3\n"
510 " slr %0,%0\n"
511 " ahi %2,31\n"
512 " srl %2,5\n"
513 "0: c %1,0(%0,%4)\n"
514 " jne 1f\n"
515 " la %0,4(%0)\n"
516 " brct %2,0b\n"
517 " lr %0,%3\n"
518 " j 4f\n"
519 "1: l %2,0(%0,%4)\n"
520 " sll %0,3\n"
521 " lhi %1,0xff\n"
522 " tml %2,0xffff\n"
523 " jno 2f\n"
524 " ahi %0,16\n"
525 " srl %2,16\n"
526 "2: tml %2,0x00ff\n"
527 " jno 3f\n"
528 " ahi %0,8\n"
529 " srl %2,8\n"
530 "3: nr %2,%1\n"
531 " ic %2,0(%2,%5)\n"
532 " alr %0,%2\n"
533 "4:"
534 : "=&a" (res), "=&d" (cmp), "=&a" (count)
535 : "a" (size), "a" (addr), "a" (&_zb_findmap),
536 "m" (*(addrtype *) addr) : "cc");
537 return (res < size) ? res : size;
538 }
539
540 static inline int
541 find_first_bit(const unsigned long * addr, unsigned long size)
542 {
543 typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
544 unsigned long cmp, count;
545 unsigned int res;
546
547 if (!size)
548 return 0;
549 asm volatile(
550 " slr %1,%1\n"
551 " lr %2,%3\n"
552 " slr %0,%0\n"
553 " ahi %2,31\n"
554 " srl %2,5\n"
555 "0: c %1,0(%0,%4)\n"
556 " jne 1f\n"
557 " la %0,4(%0)\n"
558 " brct %2,0b\n"
559 " lr %0,%3\n"
560 " j 4f\n"
561 "1: l %2,0(%0,%4)\n"
562 " sll %0,3\n"
563 " lhi %1,0xff\n"
564 " tml %2,0xffff\n"
565 " jnz 2f\n"
566 " ahi %0,16\n"
567 " srl %2,16\n"
568 "2: tml %2,0x00ff\n"
569 " jnz 3f\n"
570 " ahi %0,8\n"
571 " srl %2,8\n"
572 "3: nr %2,%1\n"
573 " ic %2,0(%2,%5)\n"
574 " alr %0,%2\n"
575 "4:"
576 : "=&a" (res), "=&d" (cmp), "=&a" (count)
577 : "a" (size), "a" (addr), "a" (&_sb_findmap),
578 "m" (*(addrtype *) addr) : "cc");
579 return (res < size) ? res : size;
580 }
581
582 #else /* __s390x__ */
583
584 static inline unsigned long
585 find_first_zero_bit(const unsigned long * addr, unsigned long size)
586 {
587 typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
588 unsigned long res, cmp, count;
589
590 if (!size)
591 return 0;
592 asm volatile(
593 " lghi %1,-1\n"
594 " lgr %2,%3\n"
595 " slgr %0,%0\n"
596 " aghi %2,63\n"
597 " srlg %2,%2,6\n"
598 "0: cg %1,0(%0,%4)\n"
599 " jne 1f\n"
600 " la %0,8(%0)\n"
601 " brct %2,0b\n"
602 " lgr %0,%3\n"
603 " j 5f\n"
604 "1: lg %2,0(%0,%4)\n"
605 " sllg %0,%0,3\n"
606 " clr %2,%1\n"
607 " jne 2f\n"
608 " aghi %0,32\n"
609 " srlg %2,%2,32\n"
610 "2: lghi %1,0xff\n"
611 " tmll %2,0xffff\n"
612 " jno 3f\n"
613 " aghi %0,16\n"
614 " srl %2,16\n"
615 "3: tmll %2,0x00ff\n"
616 " jno 4f\n"
617 " aghi %0,8\n"
618 " srl %2,8\n"
619 "4: ngr %2,%1\n"
620 " ic %2,0(%2,%5)\n"
621 " algr %0,%2\n"
622 "5:"
623 : "=&a" (res), "=&d" (cmp), "=&a" (count)
624 : "a" (size), "a" (addr), "a" (&_zb_findmap),
625 "m" (*(addrtype *) addr) : "cc");
626 return (res < size) ? res : size;
627 }
628
629 static inline unsigned long
630 find_first_bit(const unsigned long * addr, unsigned long size)
631 {
632 typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
633 unsigned long res, cmp, count;
634
635 if (!size)
636 return 0;
637 asm volatile(
638 " slgr %1,%1\n"
639 " lgr %2,%3\n"
640 " slgr %0,%0\n"
641 " aghi %2,63\n"
642 " srlg %2,%2,6\n"
643 "0: cg %1,0(%0,%4)\n"
644 " jne 1f\n"
645 " aghi %0,8\n"
646 " brct %2,0b\n"
647 " lgr %0,%3\n"
648 " j 5f\n"
649 "1: lg %2,0(%0,%4)\n"
650 " sllg %0,%0,3\n"
651 " clr %2,%1\n"
652 " jne 2f\n"
653 " aghi %0,32\n"
654 " srlg %2,%2,32\n"
655 "2: lghi %1,0xff\n"
656 " tmll %2,0xffff\n"
657 " jnz 3f\n"
658 " aghi %0,16\n"
659 " srl %2,16\n"
660 "3: tmll %2,0x00ff\n"
661 " jnz 4f\n"
662 " aghi %0,8\n"
663 " srl %2,8\n"
664 "4: ngr %2,%1\n"
665 " ic %2,0(%2,%5)\n"
666 " algr %0,%2\n"
667 "5:"
668 : "=&a" (res), "=&d" (cmp), "=&a" (count)
669 : "a" (size), "a" (addr), "a" (&_sb_findmap),
670 "m" (*(addrtype *) addr) : "cc");
671 return (res < size) ? res : size;
672 }
673
674 #endif /* __s390x__ */
675
676 static inline int
677 find_next_zero_bit (const unsigned long * addr, unsigned long size,
678 unsigned long offset)
679 {
680 const unsigned long *p;
681 unsigned long bit, set;
682
683 if (offset >= size)
684 return size;
685 bit = offset & (__BITOPS_WORDSIZE - 1);
686 offset -= bit;
687 size -= offset;
688 p = addr + offset / __BITOPS_WORDSIZE;
689 if (bit) {
690 /*
691 * s390 version of ffz returns __BITOPS_WORDSIZE
692 * if no zero bit is present in the word.
693 */
694 set = ffz(*p >> bit) + bit;
695 if (set >= size)
696 return size + offset;
697 if (set < __BITOPS_WORDSIZE)
698 return set + offset;
699 offset += __BITOPS_WORDSIZE;
700 size -= __BITOPS_WORDSIZE;
701 p++;
702 }
703 return offset + find_first_zero_bit(p, size);
704 }
705
706 static inline int
707 find_next_bit (const unsigned long * addr, unsigned long size,
708 unsigned long offset)
709 {
710 const unsigned long *p;
711 unsigned long bit, set;
712
713 if (offset >= size)
714 return size;
715 bit = offset & (__BITOPS_WORDSIZE - 1);
716 offset -= bit;
717 size -= offset;
718 p = addr + offset / __BITOPS_WORDSIZE;
719 if (bit) {
720 /*
721 * s390 version of __ffs returns __BITOPS_WORDSIZE
722 * if no one bit is present in the word.
723 */
724 set = __ffs(*p & (~0UL << bit));
725 if (set >= size)
726 return size + offset;
727 if (set < __BITOPS_WORDSIZE)
728 return set + offset;
729 offset += __BITOPS_WORDSIZE;
730 size -= __BITOPS_WORDSIZE;
731 p++;
732 }
733 return offset + find_first_bit(p, size);
734 }
735
736 /*
737 * Every architecture must define this function. It's the fastest
738 * way of searching a 140-bit bitmap where the first 100 bits are
739 * unlikely to be set. It's guaranteed that at least one of the 140
740 * bits is cleared.
741 */
742 static inline int sched_find_first_bit(unsigned long *b)
743 {
744 return find_first_bit(b, 140);
745 }
746
747 #include <asm-generic/bitops/ffs.h>
748
749 #include <asm-generic/bitops/fls.h>
750 #include <asm-generic/bitops/fls64.h>
751
752 #include <asm-generic/bitops/hweight.h>
753 #include <asm-generic/bitops/lock.h>
754
755 /*
756 * ATTENTION: intel byte ordering convention for ext2 and minix !!
757 * bit 0 is the LSB of addr; bit 31 is the MSB of addr;
758 * bit 32 is the LSB of (addr+4).
759 * That combined with the little endian byte order of Intel gives the
760 * following bit order in memory:
761 * 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08 \
762 * 23 22 21 20 19 18 17 16 31 30 29 28 27 26 25 24
763 */
764
765 #define ext2_set_bit(nr, addr) \
766 __test_and_set_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
767 #define ext2_set_bit_atomic(lock, nr, addr) \
768 test_and_set_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
769 #define ext2_clear_bit(nr, addr) \
770 __test_and_clear_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
771 #define ext2_clear_bit_atomic(lock, nr, addr) \
772 test_and_clear_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
773 #define ext2_test_bit(nr, addr) \
774 test_bit((nr)^(__BITOPS_WORDSIZE - 8), (unsigned long *)addr)
775 #define ext2_find_next_bit(addr, size, off) \
776 generic_find_next_le_bit((unsigned long *)(addr), (size), (off))
777
778 #ifndef __s390x__
779
780 static inline int
781 ext2_find_first_zero_bit(void *vaddr, unsigned int size)
782 {
783 typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
784 unsigned long cmp, count;
785 unsigned int res;
786
787 if (!size)
788 return 0;
789 asm volatile(
790 " lhi %1,-1\n"
791 " lr %2,%3\n"
792 " ahi %2,31\n"
793 " srl %2,5\n"
794 " slr %0,%0\n"
795 "0: cl %1,0(%0,%4)\n"
796 " jne 1f\n"
797 " ahi %0,4\n"
798 " brct %2,0b\n"
799 " lr %0,%3\n"
800 " j 4f\n"
801 "1: l %2,0(%0,%4)\n"
802 " sll %0,3\n"
803 " ahi %0,24\n"
804 " lhi %1,0xff\n"
805 " tmh %2,0xffff\n"
806 " jo 2f\n"
807 " ahi %0,-16\n"
808 " srl %2,16\n"
809 "2: tml %2,0xff00\n"
810 " jo 3f\n"
811 " ahi %0,-8\n"
812 " srl %2,8\n"
813 "3: nr %2,%1\n"
814 " ic %2,0(%2,%5)\n"
815 " alr %0,%2\n"
816 "4:"
817 : "=&a" (res), "=&d" (cmp), "=&a" (count)
818 : "a" (size), "a" (vaddr), "a" (&_zb_findmap),
819 "m" (*(addrtype *) vaddr) : "cc");
820 return (res < size) ? res : size;
821 }
822
823 #else /* __s390x__ */
824
825 static inline unsigned long
826 ext2_find_first_zero_bit(void *vaddr, unsigned long size)
827 {
828 typedef struct { long _[__BITOPS_WORDS(size)]; } addrtype;
829 unsigned long res, cmp, count;
830
831 if (!size)
832 return 0;
833 asm volatile(
834 " lghi %1,-1\n"
835 " lgr %2,%3\n"
836 " aghi %2,63\n"
837 " srlg %2,%2,6\n"
838 " slgr %0,%0\n"
839 "0: clg %1,0(%0,%4)\n"
840 " jne 1f\n"
841 " aghi %0,8\n"
842 " brct %2,0b\n"
843 " lgr %0,%3\n"
844 " j 5f\n"
845 "1: cl %1,0(%0,%4)\n"
846 " jne 2f\n"
847 " aghi %0,4\n"
848 "2: l %2,0(%0,%4)\n"
849 " sllg %0,%0,3\n"
850 " aghi %0,24\n"
851 " lghi %1,0xff\n"
852 " tmlh %2,0xffff\n"
853 " jo 3f\n"
854 " aghi %0,-16\n"
855 " srl %2,16\n"
856 "3: tmll %2,0xff00\n"
857 " jo 4f\n"
858 " aghi %0,-8\n"
859 " srl %2,8\n"
860 "4: ngr %2,%1\n"
861 " ic %2,0(%2,%5)\n"
862 " algr %0,%2\n"
863 "5:"
864 : "=&a" (res), "=&d" (cmp), "=&a" (count)
865 : "a" (size), "a" (vaddr), "a" (&_zb_findmap),
866 "m" (*(addrtype *) vaddr) : "cc");
867 return (res < size) ? res : size;
868 }
869
870 #endif /* __s390x__ */
871
872 static inline int
873 ext2_find_next_zero_bit(void *vaddr, unsigned long size, unsigned long offset)
874 {
875 unsigned long *addr = vaddr, *p;
876 unsigned long word, bit, set;
877
878 if (offset >= size)
879 return size;
880 bit = offset & (__BITOPS_WORDSIZE - 1);
881 offset -= bit;
882 size -= offset;
883 p = addr + offset / __BITOPS_WORDSIZE;
884 if (bit) {
885 #ifndef __s390x__
886 asm volatile(
887 " ic %0,0(%1)\n"
888 " icm %0,2,1(%1)\n"
889 " icm %0,4,2(%1)\n"
890 " icm %0,8,3(%1)"
891 : "=&a" (word) : "a" (p), "m" (*p) : "cc");
892 #else
893 asm volatile(
894 " lrvg %0,%1"
895 : "=a" (word) : "m" (*p) );
896 #endif
897 /*
898 * s390 version of ffz returns __BITOPS_WORDSIZE
899 * if no zero bit is present in the word.
900 */
901 set = ffz(word >> bit) + bit;
902 if (set >= size)
903 return size + offset;
904 if (set < __BITOPS_WORDSIZE)
905 return set + offset;
906 offset += __BITOPS_WORDSIZE;
907 size -= __BITOPS_WORDSIZE;
908 p++;
909 }
910 return offset + ext2_find_first_zero_bit(p, size);
911 }
912
913 #include <asm-generic/bitops/minix.h>
914
915 #endif /* __KERNEL__ */
916
917 #endif /* _S390_BITOPS_H */
WRT350N Kernel Patches