arch/blackfin/kernel/cplb-mpu/cplbmgr.c

   1 /*
   2  *               Blackfin CPLB exception handling.
   3  *               Copyright 2004-2007 Analog Devices Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, see the file COPYING, or write
  17  * to the Free Software Foundation, Inc.,
  18  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  19  */
  20 #include <linux/module.h>
  21 #include <linux/mm.h>
  22
  23 #include <asm/blackfin.h>
  24 #include <asm/cplbinit.h>
  25 #include <asm/mmu_context.h>
  26
  27 #ifdef CONFIG_BFIN_ICACHE
  28
  29 #define FAULT_RW        (1 << 16)
  30 #define FAULT_USERSUPV  (1 << 17)
  31
  32 int page_mask_nelts;
  33 int page_mask_order;
  34 unsigned long *current_rwx_mask;
  35
  36 int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
  37 int nr_cplb_flush;
  38
  39 static inline void disable_dcplb(void)
  40 {
  41         unsigned long ctrl;
  42         SSYNC();
  43         ctrl = bfin_read_DMEM_CONTROL();
  44         ctrl &= ~ENDCPLB;
  45         bfin_write_DMEM_CONTROL(ctrl);
  46         SSYNC();
  47 }
  48
  49 static inline void enable_dcplb(void)
  50 {
  51         unsigned long ctrl;
  52         SSYNC();
  53         ctrl = bfin_read_DMEM_CONTROL();
  54         ctrl |= ENDCPLB;
  55         bfin_write_DMEM_CONTROL(ctrl);
  56         SSYNC();
  57 }
  58
  59 static inline void disable_icplb(void)
  60 {
  61         unsigned long ctrl;
  62         SSYNC();
  63         ctrl = bfin_read_IMEM_CONTROL();
  64         ctrl &= ~ENICPLB;
  65         bfin_write_IMEM_CONTROL(ctrl);
  66         SSYNC();
  67 }
  68
  69 static inline void enable_icplb(void)
  70 {
  71         unsigned long ctrl;
  72         SSYNC();
  73         ctrl = bfin_read_IMEM_CONTROL();
  74         ctrl |= ENICPLB;
  75         bfin_write_IMEM_CONTROL(ctrl);
  76         SSYNC();
  77 }
  78
  79 /*
  80  * Given the contents of the status register, return the index of the
  81  * CPLB that caused the fault.
  82  */
  83 static inline int faulting_cplb_index(int status)
  84 {
  85         int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
  86         return 30 - signbits;
  87 }
  88
  89 /*
  90  * Given the contents of the status register and the DCPLB_DATA contents,
  91  * return true if a write access should be permitted.
  92  */
  93 static inline int write_permitted(int status, unsigned long data)
  94 {
  95         if (status & FAULT_USERSUPV)
  96                 return !!(data & CPLB_SUPV_WR);
  97         else
  98                 return !!(data & CPLB_USER_WR);
  99 }
 100
 101 /* Counters to implement round-robin replacement.  */
 102 static int icplb_rr_index, dcplb_rr_index;
 103
 104 /*
 105  * Find an ICPLB entry to be evicted and return its index.
 106  */
 107 static int evict_one_icplb(void)
 108 {
 109         int i;
 110         for (i = first_switched_icplb; i < MAX_CPLBS; i++)
 111                 if ((icplb_tbl[i].data & CPLB_VALID) == 0)
 112                         return i;
 113         i = first_switched_icplb + icplb_rr_index;
 114         if (i >= MAX_CPLBS) {
 115                 i -= MAX_CPLBS - first_switched_icplb;
 116                 icplb_rr_index -= MAX_CPLBS - first_switched_icplb;
 117         }
 118         icplb_rr_index++;
 119         return i;
 120 }
 121
 122 static int evict_one_dcplb(void)
 123 {
 124         int i;
 125         for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
 126                 if ((dcplb_tbl[i].data & CPLB_VALID) == 0)
 127                         return i;
 128         i = first_switched_dcplb + dcplb_rr_index;
 129         if (i >= MAX_CPLBS) {
 130                 i -= MAX_CPLBS - first_switched_dcplb;
 131                 dcplb_rr_index -= MAX_CPLBS - first_switched_dcplb;
 132         }
 133         dcplb_rr_index++;
 134         return i;
 135 }
 136
 137 static noinline int dcplb_miss(void)
 138 {
 139         unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
 140         int status = bfin_read_DCPLB_STATUS();
 141         unsigned long *mask;
 142         int idx;
 143         unsigned long d_data;
 144
 145         nr_dcplb_miss++;
 146         if (addr >= _ramend)
 147                 return CPLB_PROT_VIOL;
 148
 149         d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
 150 #ifdef CONFIG_BFIN_DCACHE
 151         d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
 152 #ifdef CONFIG_BLKFIN_WT
 153         d_data |= CPLB_L1_AOW | CPLB_WT;
 154 #endif
 155 #endif
 156         mask = current_rwx_mask;
 157         if (mask) {
 158                 int page = addr >> PAGE_SHIFT;
 159                 int offs = page >> 5;
 160                 int bit = 1 << (page & 31);
 161
 162                 if (mask[offs] & bit)
 163                         d_data |= CPLB_USER_RD;
 164
 165                 mask += page_mask_nelts;
 166                 if (mask[offs] & bit)
 167                         d_data |= CPLB_USER_WR;
 168         }
 169
 170         idx = evict_one_dcplb();
 171
 172         addr &= PAGE_MASK;
 173         dcplb_tbl[idx].addr = addr;
 174         dcplb_tbl[idx].data = d_data;
 175
 176         disable_dcplb();
 177         bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
 178         bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
 179         enable_dcplb();
 180
 181         return 0;
 182 }
 183
 184 static noinline int icplb_miss(void)
 185 {
 186         unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
 187         int status = bfin_read_ICPLB_STATUS();
 188         int idx;
 189         unsigned long i_data;
 190
 191         nr_icplb_miss++;
 192         if (status & FAULT_USERSUPV)
 193                 nr_icplb_supv_miss++;
 194
 195         if (addr >= _ramend)
 196                 return CPLB_PROT_VIOL;
 197
 198         /*
 199          * First, try to find a CPLB that matches this address.  If we
 200          * find one, then the fact that we're in the miss handler means
 201          * that the instruction crosses a page boundary.
 202          */
 203         for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
 204                 if (icplb_tbl[idx].data & CPLB_VALID) {
 205                         unsigned long this_addr = icplb_tbl[idx].addr;
 206                         if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
 207                                 addr += PAGE_SIZE;
 208                                 break;
 209                         }
 210                 }
 211         }
 212
 213         i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
 214 #ifdef CONFIG_BFIN_ICACHE
 215         i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
 216 #endif
 217
 218         /*
 219          * Two cases to distinguish - a supervisor access must necessarily
 220          * be for a module page; we grant it unconditionally (could do better
 221          * here in the future).  Otherwise, check the x bitmap of the current
 222          * process.
 223          */
 224         if (!(status & FAULT_USERSUPV)) {
 225                 unsigned long *mask = current_rwx_mask;
 226
 227                 if (mask) {
 228                         int page = addr >> PAGE_SHIFT;
 229                         int offs = page >> 5;
 230                         int bit = 1 << (page & 31);
 231
 232                         mask += 2 * page_mask_nelts;
 233                         if (mask[offs] & bit)
 234                                 i_data |= CPLB_USER_RD;
 235                 }
 236         }
 237
 238         idx = evict_one_icplb();
 239         addr &= PAGE_MASK;
 240         icplb_tbl[idx].addr = addr;
 241         icplb_tbl[idx].data = i_data;
 242
 243         disable_icplb();
 244         bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
 245         bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
 246         enable_icplb();
 247
 248         return 0;
 249 }
 250
 251 static noinline int dcplb_protection_fault(void)
 252 {
 253         unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
 254         int status = bfin_read_DCPLB_STATUS();
 255
 256         nr_dcplb_prot++;
 257
 258         if (status & FAULT_RW) {
 259                 int idx = faulting_cplb_index(status);
 260                 unsigned long data = dcplb_tbl[idx].data;
 261                 if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
 262                     write_permitted(status, data)) {
 263                         data |= CPLB_DIRTY;
 264                         dcplb_tbl[idx].data = data;
 265                         bfin_write32(DCPLB_DATA0 + idx * 4, data);
 266                         return 0;
 267                 }
 268         }
 269         return CPLB_PROT_VIOL;
 270 }
 271
 272 int cplb_hdr(int seqstat, struct pt_regs *regs)
 273 {
 274         int cause = seqstat & 0x3f;
 275         switch (cause) {
 276         case 0x23:
 277                 return dcplb_protection_fault();
 278         case 0x2C:
 279                 return icplb_miss();
 280         case 0x26:
 281                 return dcplb_miss();
 282         default:
 283             return 1;
 284                 panic_cplb_error(seqstat, regs);
 285         }
 286 }
 287
 288 void flush_switched_cplbs(void)
 289 {
 290         int i;
 291
 292         nr_cplb_flush++;
 293
 294         disable_icplb();
 295         for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
 296                 icplb_tbl[i].data = 0;
 297                 bfin_write32(ICPLB_DATA0 + i * 4, 0);
 298         }
 299         enable_icplb();
 300
 301         disable_dcplb();
 302         for (i = first_mask_dcplb; i < MAX_CPLBS; i++) {
 303                 dcplb_tbl[i].data = 0;
 304                 bfin_write32(DCPLB_DATA0 + i * 4, 0);
 305         }
 306         enable_dcplb();
 307 }
 308
 309 void set_mask_dcplbs(unsigned long *masks)
 310 {
 311         int i;
 312         unsigned long addr = (unsigned long)masks;
 313         unsigned long d_data;
 314         current_rwx_mask = masks;
 315
 316         if (!masks)
 317                 return;
 318
 319         d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
 320 #ifdef CONFIG_BFIN_DCACHE
 321         d_data |= CPLB_L1_CHBL;
 322 #ifdef CONFIG_BLKFIN_WT
 323         d_data |= CPLB_L1_AOW | CPLB_WT;
 324 #endif
 325 #endif
 326
 327         disable_dcplb();
 328         for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
 329                 dcplb_tbl[i].addr = addr;
 330                 dcplb_tbl[i].data = d_data;
 331                 bfin_write32(DCPLB_DATA0 + i * 4, d_data);
 332                 bfin_write32(DCPLB_ADDR0 + i * 4, addr);
 333                 addr += PAGE_SIZE;
 334         }
 335         enable_dcplb();
 336 }
 337
 338 #endif