arch/sparc64/kernel/iommu.c

   1 /* iommu.c: Generic sparc64 IOMMU support.
   2  *
   3  * Copyright (C) 1999, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/module.h>
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/errno.h>
  13 #include <linux/iommu-helper.h>
  14
  15 #ifdef CONFIG_PCI
  16 #include <linux/pci.h>
  17 #endif
  18
  19 #include <asm/iommu.h>
  20
  21 #include "iommu_common.h"
  22
  23 #define STC_CTXMATCH_ADDR(STC, CTX)     \
  24         ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
  25 #define STC_FLUSHFLAG_INIT(STC) \
  26         (*((STC)->strbuf_flushflag) = 0UL)
  27 #define STC_FLUSHFLAG_SET(STC) \
  28         (*((STC)->strbuf_flushflag) != 0UL)
  29
  30 #define iommu_read(__reg) \
  31 ({      u64 __ret; \
  32         __asm__ __volatile__("ldxa [%1] %2, %0" \
  33                              : "=r" (__ret) \
  34                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  35                              : "memory"); \
  36         __ret; \
  37 })
  38 #define iommu_write(__reg, __val) \
  39         __asm__ __volatile__("stxa %0, [%1] %2" \
  40                              : /* no outputs */ \
  41                              : "r" (__val), "r" (__reg), \
  42                                "i" (ASI_PHYS_BYPASS_EC_E))
  43
  44 /* Must be invoked under the IOMMU lock. */
  45 static void iommu_flushall(struct iommu *iommu)
  46 {
  47         if (iommu->iommu_flushinv) {
  48                 iommu_write(iommu->iommu_flushinv, ~(u64)0);
  49         } else {
  50                 unsigned long tag;
  51                 int entry;
  52
  53                 tag = iommu->iommu_tags;
  54                 for (entry = 0; entry < 16; entry++) {
  55                         iommu_write(tag, 0);
  56                         tag += 8;
  57                 }
  58
  59                 /* Ensure completion of previous PIO writes. */
  60                 (void) iommu_read(iommu->write_complete_reg);
  61         }
  62 }
  63
  64 #define IOPTE_CONSISTENT(CTX) \
  65         (IOPTE_VALID | IOPTE_CACHE | \
  66          (((CTX) << 47) & IOPTE_CONTEXT))
  67
  68 #define IOPTE_STREAMING(CTX) \
  69         (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
  70
  71 /* Existing mappings are never marked invalid, instead they
  72  * are pointed to a dummy page.
  73  */
  74 #define IOPTE_IS_DUMMY(iommu, iopte)    \
  75         ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
  76
  77 static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte)
  78 {
  79         unsigned long val = iopte_val(*iopte);
  80
  81         val &= ~IOPTE_PAGE;
  82         val |= iommu->dummy_page_pa;
  83
  84         iopte_val(*iopte) = val;
  85 }
  86
  87 /* Based almost entirely upon the ppc64 iommu allocator.  If you use the 'handle'
  88  * facility it must all be done in one pass while under the iommu lock.
  89  *
  90  * On sun4u platforms, we only flush the IOMMU once every time we've passed
  91  * over the entire page table doing allocations.  Therefore we only ever advance
  92  * the hint and cannot backtrack it.
  93  */
  94 unsigned long iommu_range_alloc(struct device *dev,
  95                                 struct iommu *iommu,
  96                                 unsigned long npages,
  97                                 unsigned long *handle)
  98 {
  99         unsigned long n, end, start, limit, boundary_size;
 100         struct iommu_arena *arena = &iommu->arena;
 101         int pass = 0;
 102
 103         /* This allocator was derived from x86_64's bit string search */
 104
 105         /* Sanity check */
 106         if (unlikely(npages == 0)) {
 107                 if (printk_ratelimit())
 108                         WARN_ON(1);
 109                 return DMA_ERROR_CODE;
 110         }
 111
 112         if (handle && *handle)
 113                 start = *handle;
 114         else
 115                 start = arena->hint;
 116
 117         limit = arena->limit;
 118
 119         /* The case below can happen if we have a small segment appended
 120          * to a large, or when the previous alloc was at the very end of
 121          * the available space. If so, go back to the beginning and flush.
 122          */
 123         if (start >= limit) {
 124                 start = 0;
 125                 if (iommu->flush_all)
 126                         iommu->flush_all(iommu);
 127         }
 128
 129  again:
 130
 131         if (dev)
 132                 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 133                                       1 << IO_PAGE_SHIFT);
 134         else
 135                 boundary_size = ALIGN(1UL << 32, 1 << IO_PAGE_SHIFT);
 136
 137         n = iommu_area_alloc(arena->map, limit, start, npages, 0,
 138                              boundary_size >> IO_PAGE_SHIFT, 0);
 139         if (n == -1) {
 140                 if (likely(pass < 1)) {
 141                         /* First failure, rescan from the beginning.  */
 142                         start = 0;
 143                         if (iommu->flush_all)
 144                                 iommu->flush_all(iommu);
 145                         pass++;
 146                         goto again;
 147                 } else {
 148                         /* Second failure, give up */
 149                         return DMA_ERROR_CODE;
 150                 }
 151         }
 152
 153         end = n + npages;
 154
 155         arena->hint = end;
 156
 157         /* Update handle for SG allocations */
 158         if (handle)
 159                 *handle = end;
 160
 161         return n;
 162 }
 163
 164 void iommu_range_free(struct iommu *iommu, dma_addr_t dma_addr, unsigned long npages)
 165 {
 166         struct iommu_arena *arena = &iommu->arena;
 167         unsigned long entry;
 168
 169         entry = (dma_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT;
 170
 171         iommu_area_free(arena->map, entry, npages);
 172 }
 173
 174 int iommu_table_init(struct iommu *iommu, int tsbsize,
 175                      u32 dma_offset, u32 dma_addr_mask)
 176 {
 177         unsigned long i, tsbbase, order, sz, num_tsb_entries;
 178
 179         num_tsb_entries = tsbsize / sizeof(iopte_t);
 180
 181         /* Setup initial software IOMMU state. */
 182         spin_lock_init(&iommu->lock);
 183         iommu->ctx_lowest_free = 1;
 184         iommu->page_table_map_base = dma_offset;
 185         iommu->dma_addr_mask = dma_addr_mask;
 186
 187         /* Allocate and initialize the free area map.  */
 188         sz = num_tsb_entries / 8;
 189         sz = (sz + 7UL) & ~7UL;
 190         iommu->arena.map = kzalloc(sz, GFP_KERNEL);
 191         if (!iommu->arena.map) {
 192                 printk(KERN_ERR "IOMMU: Error, kmalloc(arena.map) failed.\n");
 193                 return -ENOMEM;
 194         }
 195         iommu->arena.limit = num_tsb_entries;
 196
 197         if (tlb_type != hypervisor)
 198                 iommu->flush_all = iommu_flushall;
 199
 200         /* Allocate and initialize the dummy page which we
 201          * set inactive IO PTEs to point to.
 202          */
 203         iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
 204         if (!iommu->dummy_page) {
 205                 printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n");
 206                 goto out_free_map;
 207         }
 208         memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
 209         iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
 210
 211         /* Now allocate and setup the IOMMU page table itself.  */
 212         order = get_order(tsbsize);
 213         tsbbase = __get_free_pages(GFP_KERNEL, order);
 214         if (!tsbbase) {
 215                 printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n");
 216                 goto out_free_dummy_page;
 217         }
 218         iommu->page_table = (iopte_t *)tsbbase;
 219
 220         for (i = 0; i < num_tsb_entries; i++)
 221                 iopte_make_dummy(iommu, &iommu->page_table[i]);
 222
 223         return 0;
 224
 225 out_free_dummy_page:
 226         free_page(iommu->dummy_page);
 227         iommu->dummy_page = 0UL;
 228
 229 out_free_map:
 230         kfree(iommu->arena.map);
 231         iommu->arena.map = NULL;
 232
 233         return -ENOMEM;
 234 }
 235
 236 static inline iopte_t *alloc_npages(struct device *dev, struct iommu *iommu,
 237                                     unsigned long npages)
 238 {
 239         unsigned long entry;
 240
 241         entry = iommu_range_alloc(dev, iommu, npages, NULL);
 242         if (unlikely(entry == DMA_ERROR_CODE))
 243                 return NULL;
 244
 245         return iommu->page_table + entry;
 246 }
 247
 248 static int iommu_alloc_ctx(struct iommu *iommu)
 249 {
 250         int lowest = iommu->ctx_lowest_free;
 251         int sz = IOMMU_NUM_CTXS - lowest;
 252         int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest);
 253
 254         if (unlikely(n == sz)) {
 255                 n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
 256                 if (unlikely(n == lowest)) {
 257                         printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
 258                         n = 0;
 259                 }
 260         }
 261         if (n)
 262                 __set_bit(n, iommu->ctx_bitmap);
 263
 264         return n;
 265 }
 266
 267 static inline void iommu_free_ctx(struct iommu *iommu, int ctx)
 268 {
 269         if (likely(ctx)) {
 270                 __clear_bit(ctx, iommu->ctx_bitmap);
 271                 if (ctx < iommu->ctx_lowest_free)
 272                         iommu->ctx_lowest_free = ctx;
 273         }
 274 }
 275
 276 static void *dma_4u_alloc_coherent(struct device *dev, size_t size,
 277                                    dma_addr_t *dma_addrp, gfp_t gfp)
 278 {
 279         struct iommu *iommu;
 280         iopte_t *iopte;
 281         unsigned long flags, order, first_page;
 282         void *ret;
 283         int npages;
 284
 285         size = IO_PAGE_ALIGN(size);
 286         order = get_order(size);
 287         if (order >= 10)
 288                 return NULL;
 289
 290         first_page = __get_free_pages(gfp, order);
 291         if (first_page == 0UL)
 292                 return NULL;
 293         memset((char *)first_page, 0, PAGE_SIZE << order);
 294
 295         iommu = dev->archdata.iommu;
 296
 297         spin_lock_irqsave(&iommu->lock, flags);
 298         iopte = alloc_npages(dev, iommu, size >> IO_PAGE_SHIFT);
 299         spin_unlock_irqrestore(&iommu->lock, flags);
 300
 301         if (unlikely(iopte == NULL)) {
 302                 free_pages(first_page, order);
 303                 return NULL;
 304         }
 305
 306         *dma_addrp = (iommu->page_table_map_base +
 307                       ((iopte - iommu->page_table) << IO_PAGE_SHIFT));
 308         ret = (void *) first_page;
 309         npages = size >> IO_PAGE_SHIFT;
 310         first_page = __pa(first_page);
 311         while (npages--) {
 312                 iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) |
 313                                      IOPTE_WRITE |
 314                                      (first_page & IOPTE_PAGE));
 315                 iopte++;
 316                 first_page += IO_PAGE_SIZE;
 317         }
 318
 319         return ret;
 320 }
 321
 322 static void dma_4u_free_coherent(struct device *dev, size_t size,
 323                                  void *cpu, dma_addr_t dvma)
 324 {
 325         struct iommu *iommu;
 326         iopte_t *iopte;
 327         unsigned long flags, order, npages;
 328
 329         npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
 330         iommu = dev->archdata.iommu;
 331         iopte = iommu->page_table +
 332                 ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 333
 334         spin_lock_irqsave(&iommu->lock, flags);
 335
 336         iommu_range_free(iommu, dvma, npages);
 337
 338         spin_unlock_irqrestore(&iommu->lock, flags);
 339
 340         order = get_order(size);
 341         if (order < 10)
 342                 free_pages((unsigned long)cpu, order);
 343 }
 344
 345 static dma_addr_t dma_4u_map_single(struct device *dev, void *ptr, size_t sz,
 346                                     enum dma_data_direction direction)
 347 {
 348         struct iommu *iommu;
 349         struct strbuf *strbuf;
 350         iopte_t *base;
 351         unsigned long flags, npages, oaddr;
 352         unsigned long i, base_paddr, ctx;
 353         u32 bus_addr, ret;
 354         unsigned long iopte_protection;
 355
 356         iommu = dev->archdata.iommu;
 357         strbuf = dev->archdata.stc;
 358
 359         if (unlikely(direction == DMA_NONE))
 360                 goto bad_no_ctx;
 361
 362         oaddr = (unsigned long)ptr;
 363         npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
 364         npages >>= IO_PAGE_SHIFT;
 365
 366         spin_lock_irqsave(&iommu->lock, flags);
 367         base = alloc_npages(dev, iommu, npages);
 368         ctx = 0;
 369         if (iommu->iommu_ctxflush)
 370                 ctx = iommu_alloc_ctx(iommu);
 371         spin_unlock_irqrestore(&iommu->lock, flags);
 372
 373         if (unlikely(!base))
 374                 goto bad;
 375
 376         bus_addr = (iommu->page_table_map_base +
 377                     ((base - iommu->page_table) << IO_PAGE_SHIFT));
 378         ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
 379         base_paddr = __pa(oaddr & IO_PAGE_MASK);
 380         if (strbuf->strbuf_enabled)
 381                 iopte_protection = IOPTE_STREAMING(ctx);
 382         else
 383                 iopte_protection = IOPTE_CONSISTENT(ctx);
 384         if (direction != DMA_TO_DEVICE)
 385                 iopte_protection |= IOPTE_WRITE;
 386
 387         for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
 388                 iopte_val(*base) = iopte_protection | base_paddr;
 389
 390         return ret;
 391
 392 bad:
 393         iommu_free_ctx(iommu, ctx);
 394 bad_no_ctx:
 395         if (printk_ratelimit())
 396                 WARN_ON(1);
 397         return DMA_ERROR_CODE;
 398 }
 399
 400 static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu,
 401                          u32 vaddr, unsigned long ctx, unsigned long npages,
 402                          enum dma_data_direction direction)
 403 {
 404         int limit;
 405
 406         if (strbuf->strbuf_ctxflush &&
 407             iommu->iommu_ctxflush) {
 408                 unsigned long matchreg, flushreg;
 409                 u64 val;
 410
 411                 flushreg = strbuf->strbuf_ctxflush;
 412                 matchreg = STC_CTXMATCH_ADDR(strbuf, ctx);
 413
 414                 iommu_write(flushreg, ctx);
 415                 val = iommu_read(matchreg);
 416                 val &= 0xffff;
 417                 if (!val)
 418                         goto do_flush_sync;
 419
 420                 while (val) {
 421                         if (val & 0x1)
 422                                 iommu_write(flushreg, ctx);
 423                         val >>= 1;
 424                 }
 425                 val = iommu_read(matchreg);
 426                 if (unlikely(val)) {
 427                         printk(KERN_WARNING "strbuf_flush: ctx flush "
 428                                "timeout matchreg[%lx] ctx[%lx]\n",
 429                                val, ctx);
 430                         goto do_page_flush;
 431                 }
 432         } else {
 433                 unsigned long i;
 434
 435         do_page_flush:
 436                 for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
 437                         iommu_write(strbuf->strbuf_pflush, vaddr);
 438         }
 439
 440 do_flush_sync:
 441         /* If the device could not have possibly put dirty data into
 442          * the streaming cache, no flush-flag synchronization needs
 443          * to be performed.
 444          */
 445         if (direction == DMA_TO_DEVICE)
 446                 return;
 447
 448         STC_FLUSHFLAG_INIT(strbuf);
 449         iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
 450         (void) iommu_read(iommu->write_complete_reg);
 451
 452         limit = 100000;
 453         while (!STC_FLUSHFLAG_SET(strbuf)) {
 454                 limit--;
 455                 if (!limit)
 456                         break;
 457                 udelay(1);
 458                 rmb();
 459         }
 460         if (!limit)
 461                 printk(KERN_WARNING "strbuf_flush: flushflag timeout "
 462                        "vaddr[%08x] ctx[%lx] npages[%ld]\n",
 463                        vaddr, ctx, npages);
 464 }
 465
 466 static void dma_4u_unmap_single(struct device *dev, dma_addr_t bus_addr,
 467                                 size_t sz, enum dma_data_direction direction)
 468 {
 469         struct iommu *iommu;
 470         struct strbuf *strbuf;
 471         iopte_t *base;
 472         unsigned long flags, npages, ctx, i;
 473
 474         if (unlikely(direction == DMA_NONE)) {
 475                 if (printk_ratelimit())
 476                         WARN_ON(1);
 477                 return;
 478         }
 479
 480         iommu = dev->archdata.iommu;
 481         strbuf = dev->archdata.stc;
 482
 483         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
 484         npages >>= IO_PAGE_SHIFT;
 485         base = iommu->page_table +
 486                 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 487         bus_addr &= IO_PAGE_MASK;
 488
 489         spin_lock_irqsave(&iommu->lock, flags);
 490
 491         /* Record the context, if any. */
 492         ctx = 0;
 493         if (iommu->iommu_ctxflush)
 494                 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
 495
 496         /* Step 1: Kick data out of streaming buffers if necessary. */
 497         if (strbuf->strbuf_enabled)
 498                 strbuf_flush(strbuf, iommu, bus_addr, ctx,
 499                              npages, direction);
 500
 501         /* Step 2: Clear out TSB entries. */
 502         for (i = 0; i < npages; i++)
 503                 iopte_make_dummy(iommu, base + i);
 504
 505         iommu_range_free(iommu, bus_addr, npages);
 506
 507         iommu_free_ctx(iommu, ctx);
 508
 509         spin_unlock_irqrestore(&iommu->lock, flags);
 510 }
 511
 512 static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
 513                          int nelems, enum dma_data_direction direction)
 514 {
 515         struct scatterlist *s, *outs, *segstart;
 516         unsigned long flags, handle, prot, ctx;
 517         dma_addr_t dma_next = 0, dma_addr;
 518         unsigned int max_seg_size;
 519         int outcount, incount, i;
 520         struct strbuf *strbuf;
 521         struct iommu *iommu;
 522
 523         BUG_ON(direction == DMA_NONE);
 524
 525         iommu = dev->archdata.iommu;
 526         strbuf = dev->archdata.stc;
 527         if (nelems == 0 || !iommu)
 528                 return 0;
 529
 530         spin_lock_irqsave(&iommu->lock, flags);
 531
 532         ctx = 0;
 533         if (iommu->iommu_ctxflush)
 534                 ctx = iommu_alloc_ctx(iommu);
 535
 536         if (strbuf->strbuf_enabled)
 537                 prot = IOPTE_STREAMING(ctx);
 538         else
 539                 prot = IOPTE_CONSISTENT(ctx);
 540         if (direction != DMA_TO_DEVICE)
 541                 prot |= IOPTE_WRITE;
 542
 543         outs = s = segstart = &sglist[0];
 544         outcount = 1;
 545         incount = nelems;
 546         handle = 0;
 547
 548         /* Init first segment length for backout at failure */
 549         outs->dma_length = 0;
 550
 551         max_seg_size = dma_get_max_seg_size(dev);
 552         for_each_sg(sglist, s, nelems, i) {
 553                 unsigned long paddr, npages, entry, slen;
 554                 iopte_t *base;
 555
 556                 slen = s->length;
 557                 /* Sanity check */
 558                 if (slen == 0) {
 559                         dma_next = 0;
 560                         continue;
 561                 }
 562                 /* Allocate iommu entries for that segment */
 563                 paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s);
 564                 npages = iommu_num_pages(paddr, slen);
 565                 entry = iommu_range_alloc(dev, iommu, npages, &handle);
 566
 567                 /* Handle failure */
 568                 if (unlikely(entry == DMA_ERROR_CODE)) {
 569                         if (printk_ratelimit())
 570                                 printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx"
 571                                        " npages %lx\n", iommu, paddr, npages);
 572                         goto iommu_map_failed;
 573                 }
 574
 575                 base = iommu->page_table + entry;
 576
 577                 /* Convert entry to a dma_addr_t */
 578                 dma_addr = iommu->page_table_map_base +
 579                         (entry << IO_PAGE_SHIFT);
 580                 dma_addr |= (s->offset & ~IO_PAGE_MASK);
 581
 582                 /* Insert into HW table */
 583                 paddr &= IO_PAGE_MASK;
 584                 while (npages--) {
 585                         iopte_val(*base) = prot | paddr;
 586                         base++;
 587                         paddr += IO_PAGE_SIZE;
 588                 }
 589
 590                 /* If we are in an open segment, try merging */
 591                 if (segstart != s) {
 592                         /* We cannot merge if:
 593                          * - allocated dma_addr isn't contiguous to previous allocation
 594                          */
 595                         if ((dma_addr != dma_next) ||
 596                             (outs->dma_length + s->length > max_seg_size)) {
 597                                 /* Can't merge: create a new segment */
 598                                 segstart = s;
 599                                 outcount++;
 600                                 outs = sg_next(outs);
 601                         } else {
 602                                 outs->dma_length += s->length;
 603                         }
 604                 }
 605
 606                 if (segstart == s) {
 607                         /* This is a new segment, fill entries */
 608                         outs->dma_address = dma_addr;
 609                         outs->dma_length = slen;
 610                 }
 611
 612                 /* Calculate next page pointer for contiguous check */
 613                 dma_next = dma_addr + slen;
 614         }
 615
 616         spin_unlock_irqrestore(&iommu->lock, flags);
 617
 618         if (outcount < incount) {
 619                 outs = sg_next(outs);
 620                 outs->dma_address = DMA_ERROR_CODE;
 621                 outs->dma_length = 0;
 622         }
 623
 624         return outcount;
 625
 626 iommu_map_failed:
 627         for_each_sg(sglist, s, nelems, i) {
 628                 if (s->dma_length != 0) {
 629                         unsigned long vaddr, npages, entry, i;
 630                         iopte_t *base;
 631
 632                         vaddr = s->dma_address & IO_PAGE_MASK;
 633                         npages = iommu_num_pages(s->dma_address, s->dma_length);
 634                         iommu_range_free(iommu, vaddr, npages);
 635
 636                         entry = (vaddr - iommu->page_table_map_base)
 637                                 >> IO_PAGE_SHIFT;
 638                         base = iommu->page_table + entry;
 639
 640                         for (i = 0; i < npages; i++)
 641                                 iopte_make_dummy(iommu, base + i);
 642
 643                         s->dma_address = DMA_ERROR_CODE;
 644                         s->dma_length = 0;
 645                 }
 646                 if (s == outs)
 647                         break;
 648         }
 649         spin_unlock_irqrestore(&iommu->lock, flags);
 650
 651         return 0;
 652 }
 653
 654 /* If contexts are being used, they are the same in all of the mappings
 655  * we make for a particular SG.
 656  */
 657 static unsigned long fetch_sg_ctx(struct iommu *iommu, struct scatterlist *sg)
 658 {
 659         unsigned long ctx = 0;
 660
 661         if (iommu->iommu_ctxflush) {
 662                 iopte_t *base;
 663                 u32 bus_addr;
 664
 665                 bus_addr = sg->dma_address & IO_PAGE_MASK;
 666                 base = iommu->page_table +
 667                         ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 668
 669                 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
 670         }
 671         return ctx;
 672 }
 673
 674 static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
 675                             int nelems, enum dma_data_direction direction)
 676 {
 677         unsigned long flags, ctx;
 678         struct scatterlist *sg;
 679         struct strbuf *strbuf;
 680         struct iommu *iommu;
 681
 682         BUG_ON(direction == DMA_NONE);
 683
 684         iommu = dev->archdata.iommu;
 685         strbuf = dev->archdata.stc;
 686
 687         ctx = fetch_sg_ctx(iommu, sglist);
 688
 689         spin_lock_irqsave(&iommu->lock, flags);
 690
 691         sg = sglist;
 692         while (nelems--) {
 693                 dma_addr_t dma_handle = sg->dma_address;
 694                 unsigned int len = sg->dma_length;
 695                 unsigned long npages, entry;
 696                 iopte_t *base;
 697                 int i;
 698
 699                 if (!len)
 700                         break;
 701                 npages = iommu_num_pages(dma_handle, len);
 702                 iommu_range_free(iommu, dma_handle, npages);
 703
 704                 entry = ((dma_handle - iommu->page_table_map_base)
 705                          >> IO_PAGE_SHIFT);
 706                 base = iommu->page_table + entry;
 707
 708                 dma_handle &= IO_PAGE_MASK;
 709                 if (strbuf->strbuf_enabled)
 710                         strbuf_flush(strbuf, iommu, dma_handle, ctx,
 711                                      npages, direction);
 712
 713                 for (i = 0; i < npages; i++)
 714                         iopte_make_dummy(iommu, base + i);
 715
 716                 sg = sg_next(sg);
 717         }
 718
 719         iommu_free_ctx(iommu, ctx);
 720
 721         spin_unlock_irqrestore(&iommu->lock, flags);
 722 }
 723
 724 static void dma_4u_sync_single_for_cpu(struct device *dev,
 725                                        dma_addr_t bus_addr, size_t sz,
 726                                        enum dma_data_direction direction)
 727 {
 728         struct iommu *iommu;
 729         struct strbuf *strbuf;
 730         unsigned long flags, ctx, npages;
 731
 732         iommu = dev->archdata.iommu;
 733         strbuf = dev->archdata.stc;
 734
 735         if (!strbuf->strbuf_enabled)
 736                 return;
 737
 738         spin_lock_irqsave(&iommu->lock, flags);
 739
 740         npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
 741         npages >>= IO_PAGE_SHIFT;
 742         bus_addr &= IO_PAGE_MASK;
 743
 744         /* Step 1: Record the context, if any. */
 745         ctx = 0;
 746         if (iommu->iommu_ctxflush &&
 747             strbuf->strbuf_ctxflush) {
 748                 iopte_t *iopte;
 749
 750                 iopte = iommu->page_table +
 751                         ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
 752                 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
 753         }
 754
 755         /* Step 2: Kick data out of streaming buffers. */
 756         strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 757
 758         spin_unlock_irqrestore(&iommu->lock, flags);
 759 }
 760
 761 static void dma_4u_sync_sg_for_cpu(struct device *dev,
 762                                    struct scatterlist *sglist, int nelems,
 763                                    enum dma_data_direction direction)
 764 {
 765         struct iommu *iommu;
 766         struct strbuf *strbuf;
 767         unsigned long flags, ctx, npages, i;
 768         struct scatterlist *sg, *sgprv;
 769         u32 bus_addr;
 770
 771         iommu = dev->archdata.iommu;
 772         strbuf = dev->archdata.stc;
 773
 774         if (!strbuf->strbuf_enabled)
 775                 return;
 776
 777         spin_lock_irqsave(&iommu->lock, flags);
 778
 779         /* Step 1: Record the context, if any. */
 780         ctx = 0;
 781         if (iommu->iommu_ctxflush &&
 782             strbuf->strbuf_ctxflush) {
 783                 iopte_t *iopte;
 784
 785                 iopte = iommu->page_table +
 786                         ((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
 787                 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
 788         }
 789
 790         /* Step 2: Kick data out of streaming buffers. */
 791         bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
 792         sgprv = NULL;
 793         for_each_sg(sglist, sg, nelems, i) {
 794                 if (sg->dma_length == 0)
 795                         break;
 796                 sgprv = sg;
 797         }
 798
 799         npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length)
 800                   - bus_addr) >> IO_PAGE_SHIFT;
 801         strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
 802
 803         spin_unlock_irqrestore(&iommu->lock, flags);
 804 }
 805
 806 const struct dma_ops sun4u_dma_ops = {
 807         .alloc_coherent         = dma_4u_alloc_coherent,
 808         .free_coherent          = dma_4u_free_coherent,
 809         .map_single             = dma_4u_map_single,
 810         .unmap_single           = dma_4u_unmap_single,
 811         .map_sg                 = dma_4u_map_sg,
 812         .unmap_sg               = dma_4u_unmap_sg,
 813         .sync_single_for_cpu    = dma_4u_sync_single_for_cpu,
 814         .sync_sg_for_cpu        = dma_4u_sync_sg_for_cpu,
 815 };
 816
 817 const struct dma_ops *dma_ops = &sun4u_dma_ops;
 818 EXPORT_SYMBOL(dma_ops);
 819
 820 int dma_supported(struct device *dev, u64 device_mask)
 821 {
 822         struct iommu *iommu = dev->archdata.iommu;
 823         u64 dma_addr_mask = iommu->dma_addr_mask;
 824
 825         if (device_mask >= (1UL << 32UL))
 826                 return 0;
 827
 828         if ((device_mask & dma_addr_mask) == dma_addr_mask)
 829                 return 1;
 830
 831 #ifdef CONFIG_PCI
 832         if (dev->bus == &pci_bus_type)
 833                 return pci_dma_supported(to_pci_dev(dev), device_mask);
 834 #endif
 835
 836         return 0;
 837 }
 838 EXPORT_SYMBOL(dma_supported);
 839
 840 int dma_set_mask(struct device *dev, u64 dma_mask)
 841 {
 842 #ifdef CONFIG_PCI
 843         if (dev->bus == &pci_bus_type)
 844                 return pci_set_dma_mask(to_pci_dev(dev), dma_mask);
 845 #endif
 846         return -EINVAL;
 847 }
 848 EXPORT_SYMBOL(dma_set_mask);