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Some modifications to files needed to succesfully compile ;)
[wrt350n-kernel.git] / arch / sparc64 / kernel / pci.c
bloba61c38fe75ead3db51c7b0ae0eb4a01ef7b912ee
1 /* pci.c: UltraSparc PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
9 */
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/capability.h>
16 #include <linux/errno.h>
17 #include <linux/pci.h>
18 #include <linux/msi.h>
19 #include <linux/irq.h>
20 #include <linux/init.h>
21
22 #include <asm/uaccess.h>
23 #include <asm/pgtable.h>
24 #include <asm/irq.h>
25 #include <asm/ebus.h>
26 #include <asm/isa.h>
27 #include <asm/prom.h>
28 #include <asm/apb.h>
29
30 #include "pci_impl.h"
31
32 #ifndef CONFIG_PCI
33 /* A "nop" PCI implementation. */
34 asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
35 unsigned long off, unsigned long len,
36 unsigned char *buf)
37 {
38 return 0;
39 }
40 asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
41 unsigned long off, unsigned long len,
42 unsigned char *buf)
43 {
44 return 0;
45 }
46 #else
47
48 /* List of all PCI controllers found in the system. */
49 struct pci_pbm_info *pci_pbm_root = NULL;
50
51 /* Each PBM found gets a unique index. */
52 int pci_num_pbms = 0;
53
54 volatile int pci_poke_in_progress;
55 volatile int pci_poke_cpu = -1;
56 volatile int pci_poke_faulted;
57
58 static DEFINE_SPINLOCK(pci_poke_lock);
59
60 void pci_config_read8(u8 *addr, u8 *ret)
61 {
62 unsigned long flags;
63 u8 byte;
64
65 spin_lock_irqsave(&pci_poke_lock, flags);
66 pci_poke_cpu = smp_processor_id();
67 pci_poke_in_progress = 1;
68 pci_poke_faulted = 0;
69 __asm__ __volatile__("membar #Sync\n\t"
70 "lduba [%1] %2, %0\n\t"
71 "membar #Sync"
72 : "=r" (byte)
73 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
74 : "memory");
75 pci_poke_in_progress = 0;
76 pci_poke_cpu = -1;
77 if (!pci_poke_faulted)
78 *ret = byte;
79 spin_unlock_irqrestore(&pci_poke_lock, flags);
80 }
81
82 void pci_config_read16(u16 *addr, u16 *ret)
83 {
84 unsigned long flags;
85 u16 word;
86
87 spin_lock_irqsave(&pci_poke_lock, flags);
88 pci_poke_cpu = smp_processor_id();
89 pci_poke_in_progress = 1;
90 pci_poke_faulted = 0;
91 __asm__ __volatile__("membar #Sync\n\t"
92 "lduha [%1] %2, %0\n\t"
93 "membar #Sync"
94 : "=r" (word)
95 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
96 : "memory");
97 pci_poke_in_progress = 0;
98 pci_poke_cpu = -1;
99 if (!pci_poke_faulted)
100 *ret = word;
101 spin_unlock_irqrestore(&pci_poke_lock, flags);
102 }
103
104 void pci_config_read32(u32 *addr, u32 *ret)
105 {
106 unsigned long flags;
107 u32 dword;
108
109 spin_lock_irqsave(&pci_poke_lock, flags);
110 pci_poke_cpu = smp_processor_id();
111 pci_poke_in_progress = 1;
112 pci_poke_faulted = 0;
113 __asm__ __volatile__("membar #Sync\n\t"
114 "lduwa [%1] %2, %0\n\t"
115 "membar #Sync"
116 : "=r" (dword)
117 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
118 : "memory");
119 pci_poke_in_progress = 0;
120 pci_poke_cpu = -1;
121 if (!pci_poke_faulted)
122 *ret = dword;
123 spin_unlock_irqrestore(&pci_poke_lock, flags);
124 }
125
126 void pci_config_write8(u8 *addr, u8 val)
127 {
128 unsigned long flags;
129
130 spin_lock_irqsave(&pci_poke_lock, flags);
131 pci_poke_cpu = smp_processor_id();
132 pci_poke_in_progress = 1;
133 pci_poke_faulted = 0;
134 __asm__ __volatile__("membar #Sync\n\t"
135 "stba %0, [%1] %2\n\t"
136 "membar #Sync"
137 : /* no outputs */
138 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
139 : "memory");
140 pci_poke_in_progress = 0;
141 pci_poke_cpu = -1;
142 spin_unlock_irqrestore(&pci_poke_lock, flags);
143 }
144
145 void pci_config_write16(u16 *addr, u16 val)
146 {
147 unsigned long flags;
148
149 spin_lock_irqsave(&pci_poke_lock, flags);
150 pci_poke_cpu = smp_processor_id();
151 pci_poke_in_progress = 1;
152 pci_poke_faulted = 0;
153 __asm__ __volatile__("membar #Sync\n\t"
154 "stha %0, [%1] %2\n\t"
155 "membar #Sync"
156 : /* no outputs */
157 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
158 : "memory");
159 pci_poke_in_progress = 0;
160 pci_poke_cpu = -1;
161 spin_unlock_irqrestore(&pci_poke_lock, flags);
162 }
163
164 void pci_config_write32(u32 *addr, u32 val)
165 {
166 unsigned long flags;
167
168 spin_lock_irqsave(&pci_poke_lock, flags);
169 pci_poke_cpu = smp_processor_id();
170 pci_poke_in_progress = 1;
171 pci_poke_faulted = 0;
172 __asm__ __volatile__("membar #Sync\n\t"
173 "stwa %0, [%1] %2\n\t"
174 "membar #Sync"
175 : /* no outputs */
176 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
177 : "memory");
178 pci_poke_in_progress = 0;
179 pci_poke_cpu = -1;
180 spin_unlock_irqrestore(&pci_poke_lock, flags);
181 }
182
183 /* Probe for all PCI controllers in the system. */
184 extern void sabre_init(struct device_node *, const char *);
185 extern void psycho_init(struct device_node *, const char *);
186 extern void schizo_init(struct device_node *, const char *);
187 extern void schizo_plus_init(struct device_node *, const char *);
188 extern void tomatillo_init(struct device_node *, const char *);
189 extern void sun4v_pci_init(struct device_node *, const char *);
190 extern void fire_pci_init(struct device_node *, const char *);
191
192 static struct {
193 char *model_name;
194 void (*init)(struct device_node *, const char *);
195 } pci_controller_table[] __initdata = {
196 { "SUNW,sabre", sabre_init },
197 { "pci108e,a000", sabre_init },
198 { "pci108e,a001", sabre_init },
199 { "SUNW,psycho", psycho_init },
200 { "pci108e,8000", psycho_init },
201 { "SUNW,schizo", schizo_init },
202 { "pci108e,8001", schizo_init },
203 { "SUNW,schizo+", schizo_plus_init },
204 { "pci108e,8002", schizo_plus_init },
205 { "SUNW,tomatillo", tomatillo_init },
206 { "pci108e,a801", tomatillo_init },
207 { "SUNW,sun4v-pci", sun4v_pci_init },
208 { "pciex108e,80f0", fire_pci_init },
209 };
210 #define PCI_NUM_CONTROLLER_TYPES ARRAY_SIZE(pci_controller_table)
211
212 static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
213 {
214 int i;
215
216 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
217 if (!strncmp(model_name,
218 pci_controller_table[i].model_name,
219 namelen)) {
220 pci_controller_table[i].init(dp, model_name);
221 return 1;
222 }
223 }
224
225 return 0;
226 }
227
228 static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
229 {
230 int i;
231
232 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
233 if (!strncmp(model_name,
234 pci_controller_table[i].model_name,
235 namelen)) {
236 return 1;
237 }
238 }
239 return 0;
240 }
241
242 static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
243 {
244 struct device_node *dp;
245 int count = 0;
246
247 for_each_node_by_name(dp, "pci") {
248 struct property *prop;
249 int len;
250
251 prop = of_find_property(dp, "model", &len);
252 if (!prop)
253 prop = of_find_property(dp, "compatible", &len);
254
255 if (prop) {
256 const char *model = prop->value;
257 int item_len = 0;
258
259 /* Our value may be a multi-valued string in the
260 * case of some compatible properties. For sanity,
261 * only try the first one.
262 */
263 while (model[item_len] && len) {
264 len--;
265 item_len++;
266 }
267
268 if (handler(model, item_len, dp))
269 count++;
270 }
271 }
272
273 return count;
274 }
275
276
277 /* Is there some PCI controller in the system? */
278 int __init pcic_present(void)
279 {
280 return pci_controller_scan(pci_is_controller);
281 }
282
283 /* Find each controller in the system, attach and initialize
284 * software state structure for each and link into the
285 * pci_pbm_root. Setup the controller enough such
286 * that bus scanning can be done.
287 */
288 static void __init pci_controller_probe(void)
289 {
290 printk("PCI: Probing for controllers.\n");
291
292 pci_controller_scan(pci_controller_init);
293 }
294
295 static int ofpci_verbose;
296
297 static int __init ofpci_debug(char *str)
298 {
299 int val = 0;
300
301 get_option(&str, &val);
302 if (val)
303 ofpci_verbose = 1;
304 return 1;
305 }
306
307 __setup("ofpci_debug=", ofpci_debug);
308
309 static unsigned long pci_parse_of_flags(u32 addr0)
310 {
311 unsigned long flags = 0;
312
313 if (addr0 & 0x02000000) {
314 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
315 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
316 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
317 if (addr0 & 0x40000000)
318 flags |= IORESOURCE_PREFETCH
319 | PCI_BASE_ADDRESS_MEM_PREFETCH;
320 } else if (addr0 & 0x01000000)
321 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
322 return flags;
323 }
324
325 /* The of_device layer has translated all of the assigned-address properties
326 * into physical address resources, we only have to figure out the register
327 * mapping.
328 */
329 static void pci_parse_of_addrs(struct of_device *op,
330 struct device_node *node,
331 struct pci_dev *dev)
332 {
333 struct resource *op_res;
334 const u32 *addrs;
335 int proplen;
336
337 addrs = of_get_property(node, "assigned-addresses", &proplen);
338 if (!addrs)
339 return;
340 if (ofpci_verbose)
341 printk(" parse addresses (%d bytes) @ %p\n",
342 proplen, addrs);
343 op_res = &op->resource[0];
344 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
345 struct resource *res;
346 unsigned long flags;
347 int i;
348
349 flags = pci_parse_of_flags(addrs[0]);
350 if (!flags)
351 continue;
352 i = addrs[0] & 0xff;
353 if (ofpci_verbose)
354 printk(" start: %lx, end: %lx, i: %x\n",
355 op_res->start, op_res->end, i);
356
357 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
358 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
359 } else if (i == dev->rom_base_reg) {
360 res = &dev->resource[PCI_ROM_RESOURCE];
361 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
362 } else {
363 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
364 continue;
365 }
366 res->start = op_res->start;
367 res->end = op_res->end;
368 res->flags = flags;
369 res->name = pci_name(dev);
370 }
371 }
372
373 struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
374 struct device_node *node,
375 struct pci_bus *bus, int devfn,
376 int host_controller)
377 {
378 struct dev_archdata *sd;
379 struct pci_dev *dev;
380 const char *type;
381 u32 class;
382
383 dev = alloc_pci_dev();
384 if (!dev)
385 return NULL;
386
387 sd = &dev->dev.archdata;
388 sd->iommu = pbm->iommu;
389 sd->stc = &pbm->stc;
390 sd->host_controller = pbm;
391 sd->prom_node = node;
392 sd->op = of_find_device_by_node(node);
393
394 sd = &sd->op->dev.archdata;
395 sd->iommu = pbm->iommu;
396 sd->stc = &pbm->stc;
397
398 type = of_get_property(node, "device_type", NULL);
399 if (type == NULL)
400 type = "";
401
402 if (ofpci_verbose)
403 printk(" create device, devfn: %x, type: %s\n",
404 devfn, type);
405
406 dev->bus = bus;
407 dev->sysdata = node;
408 dev->dev.parent = bus->bridge;
409 dev->dev.bus = &pci_bus_type;
410 dev->devfn = devfn;
411 dev->multifunction = 0; /* maybe a lie? */
412
413 if (host_controller) {
414 if (tlb_type != hypervisor) {
415 pci_read_config_word(dev, PCI_VENDOR_ID,
416 &dev->vendor);
417 pci_read_config_word(dev, PCI_DEVICE_ID,
418 &dev->device);
419 } else {
420 dev->vendor = PCI_VENDOR_ID_SUN;
421 dev->device = 0x80f0;
422 }
423 dev->cfg_size = 256;
424 dev->class = PCI_CLASS_BRIDGE_HOST << 8;
425 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
426 0x00, PCI_SLOT(devfn), PCI_FUNC(devfn));
427 } else {
428 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
429 dev->device = of_getintprop_default(node, "device-id", 0xffff);
430 dev->subsystem_vendor =
431 of_getintprop_default(node, "subsystem-vendor-id", 0);
432 dev->subsystem_device =
433 of_getintprop_default(node, "subsystem-id", 0);
434
435 dev->cfg_size = pci_cfg_space_size(dev);
436
437 /* We can't actually use the firmware value, we have
438 * to read what is in the register right now. One
439 * reason is that in the case of IDE interfaces the
440 * firmware can sample the value before the the IDE
441 * interface is programmed into native mode.
442 */
443 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
444 dev->class = class >> 8;
445 dev->revision = class & 0xff;
446
447 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
448 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
449 }
450 if (ofpci_verbose)
451 printk(" class: 0x%x device name: %s\n",
452 dev->class, pci_name(dev));
453
454 /* I have seen IDE devices which will not respond to
455 * the bmdma simplex check reads if bus mastering is
456 * disabled.
457 */
458 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
459 pci_set_master(dev);
460
461 dev->current_state = 4; /* unknown power state */
462 dev->error_state = pci_channel_io_normal;
463
464 if (host_controller) {
465 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
466 dev->rom_base_reg = PCI_ROM_ADDRESS1;
467 dev->irq = PCI_IRQ_NONE;
468 } else {
469 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
470 /* a PCI-PCI bridge */
471 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
472 dev->rom_base_reg = PCI_ROM_ADDRESS1;
473 } else if (!strcmp(type, "cardbus")) {
474 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
475 } else {
476 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
477 dev->rom_base_reg = PCI_ROM_ADDRESS;
478
479 dev->irq = sd->op->irqs[0];
480 if (dev->irq == 0xffffffff)
481 dev->irq = PCI_IRQ_NONE;
482 }
483 }
484 pci_parse_of_addrs(sd->op, node, dev);
485
486 if (ofpci_verbose)
487 printk(" adding to system ...\n");
488
489 pci_device_add(dev, bus);
490
491 return dev;
492 }
493
494 static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
495 {
496 u32 idx, first, last;
497
498 first = 8;
499 last = 0;
500 for (idx = 0; idx < 8; idx++) {
501 if ((map & (1 << idx)) != 0) {
502 if (first > idx)
503 first = idx;
504 if (last < idx)
505 last = idx;
506 }
507 }
508
509 *first_p = first;
510 *last_p = last;
511 }
512
513 static void pci_resource_adjust(struct resource *res,
514 struct resource *root)
515 {
516 res->start += root->start;
517 res->end += root->start;
518 }
519
520 /* For PCI bus devices which lack a 'ranges' property we interrogate
521 * the config space values to set the resources, just like the generic
522 * Linux PCI probing code does.
523 */
524 static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
525 struct pci_bus *bus,
526 struct pci_pbm_info *pbm)
527 {
528 struct resource *res;
529 u8 io_base_lo, io_limit_lo;
530 u16 mem_base_lo, mem_limit_lo;
531 unsigned long base, limit;
532
533 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
534 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
535 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
536 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
537
538 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
539 u16 io_base_hi, io_limit_hi;
540
541 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
542 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
543 base |= (io_base_hi << 16);
544 limit |= (io_limit_hi << 16);
545 }
546
547 res = bus->resource[0];
548 if (base <= limit) {
549 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
550 if (!res->start)
551 res->start = base;
552 if (!res->end)
553 res->end = limit + 0xfff;
554 pci_resource_adjust(res, &pbm->io_space);
555 }
556
557 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
558 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
559 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
560 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
561
562 res = bus->resource[1];
563 if (base <= limit) {
564 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
565 IORESOURCE_MEM);
566 res->start = base;
567 res->end = limit + 0xfffff;
568 pci_resource_adjust(res, &pbm->mem_space);
569 }
570
571 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
572 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
573 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
574 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
575
576 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
577 u32 mem_base_hi, mem_limit_hi;
578
579 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
580 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
581
582 /*
583 * Some bridges set the base > limit by default, and some
584 * (broken) BIOSes do not initialize them. If we find
585 * this, just assume they are not being used.
586 */
587 if (mem_base_hi <= mem_limit_hi) {
588 base |= ((long) mem_base_hi) << 32;
589 limit |= ((long) mem_limit_hi) << 32;
590 }
591 }
592
593 res = bus->resource[2];
594 if (base <= limit) {
595 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
596 IORESOURCE_MEM | IORESOURCE_PREFETCH);
597 res->start = base;
598 res->end = limit + 0xfffff;
599 pci_resource_adjust(res, &pbm->mem_space);
600 }
601 }
602
603 /* Cook up fake bus resources for SUNW,simba PCI bridges which lack
604 * a proper 'ranges' property.
605 */
606 static void __devinit apb_fake_ranges(struct pci_dev *dev,
607 struct pci_bus *bus,
608 struct pci_pbm_info *pbm)
609 {
610 struct resource *res;
611 u32 first, last;
612 u8 map;
613
614 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
615 apb_calc_first_last(map, &first, &last);
616 res = bus->resource[0];
617 res->start = (first << 21);
618 res->end = (last << 21) + ((1 << 21) - 1);
619 res->flags = IORESOURCE_IO;
620 pci_resource_adjust(res, &pbm->io_space);
621
622 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
623 apb_calc_first_last(map, &first, &last);
624 res = bus->resource[1];
625 res->start = (first << 21);
626 res->end = (last << 21) + ((1 << 21) - 1);
627 res->flags = IORESOURCE_MEM;
628 pci_resource_adjust(res, &pbm->mem_space);
629 }
630
631 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
632 struct device_node *node,
633 struct pci_bus *bus);
634
635 #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
636
637 static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
638 struct device_node *node,
639 struct pci_dev *dev)
640 {
641 struct pci_bus *bus;
642 const u32 *busrange, *ranges;
643 int len, i, simba;
644 struct resource *res;
645 unsigned int flags;
646 u64 size;
647
648 if (ofpci_verbose)
649 printk("of_scan_pci_bridge(%s)\n", node->full_name);
650
651 /* parse bus-range property */
652 busrange = of_get_property(node, "bus-range", &len);
653 if (busrange == NULL || len != 8) {
654 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
655 node->full_name);
656 return;
657 }
658 ranges = of_get_property(node, "ranges", &len);
659 simba = 0;
660 if (ranges == NULL) {
661 const char *model = of_get_property(node, "model", NULL);
662 if (model && !strcmp(model, "SUNW,simba"))
663 simba = 1;
664 }
665
666 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
667 if (!bus) {
668 printk(KERN_ERR "Failed to create pci bus for %s\n",
669 node->full_name);
670 return;
671 }
672
673 bus->primary = dev->bus->number;
674 bus->subordinate = busrange[1];
675 bus->bridge_ctl = 0;
676
677 /* parse ranges property, or cook one up by hand for Simba */
678 /* PCI #address-cells == 3 and #size-cells == 2 always */
679 res = &dev->resource[PCI_BRIDGE_RESOURCES];
680 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
681 res->flags = 0;
682 bus->resource[i] = res;
683 ++res;
684 }
685 if (simba) {
686 apb_fake_ranges(dev, bus, pbm);
687 goto after_ranges;
688 } else if (ranges == NULL) {
689 pci_cfg_fake_ranges(dev, bus, pbm);
690 goto after_ranges;
691 }
692 i = 1;
693 for (; len >= 32; len -= 32, ranges += 8) {
694 struct resource *root;
695
696 flags = pci_parse_of_flags(ranges[0]);
697 size = GET_64BIT(ranges, 6);
698 if (flags == 0 || size == 0)
699 continue;
700 if (flags & IORESOURCE_IO) {
701 res = bus->resource[0];
702 if (res->flags) {
703 printk(KERN_ERR "PCI: ignoring extra I/O range"
704 " for bridge %s\n", node->full_name);
705 continue;
706 }
707 root = &pbm->io_space;
708 } else {
709 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
710 printk(KERN_ERR "PCI: too many memory ranges"
711 " for bridge %s\n", node->full_name);
712 continue;
713 }
714 res = bus->resource[i];
715 ++i;
716 root = &pbm->mem_space;
717 }
718
719 res->start = GET_64BIT(ranges, 1);
720 res->end = res->start + size - 1;
721 res->flags = flags;
722
723 /* Another way to implement this would be to add an of_device
724 * layer routine that can calculate a resource for a given
725 * range property value in a PCI device.
726 */
727 pci_resource_adjust(res, root);
728 }
729 after_ranges:
730 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
731 bus->number);
732 if (ofpci_verbose)
733 printk(" bus name: %s\n", bus->name);
734
735 pci_of_scan_bus(pbm, node, bus);
736 }
737
738 static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
739 struct device_node *node,
740 struct pci_bus *bus)
741 {
742 struct device_node *child;
743 const u32 *reg;
744 int reglen, devfn, prev_devfn;
745 struct pci_dev *dev;
746
747 if (ofpci_verbose)
748 printk("PCI: scan_bus[%s] bus no %d\n",
749 node->full_name, bus->number);
750
751 child = NULL;
752 prev_devfn = -1;
753 while ((child = of_get_next_child(node, child)) != NULL) {
754 if (ofpci_verbose)
755 printk(" * %s\n", child->full_name);
756 reg = of_get_property(child, "reg", &reglen);
757 if (reg == NULL || reglen < 20)
758 continue;
759
760 devfn = (reg[0] >> 8) & 0xff;
761
762 /* This is a workaround for some device trees
763 * which list PCI devices twice. On the V100
764 * for example, device number 3 is listed twice.
765 * Once as "pm" and once again as "lomp".
766 */
767 if (devfn == prev_devfn)
768 continue;
769 prev_devfn = devfn;
770
771 /* create a new pci_dev for this device */
772 dev = of_create_pci_dev(pbm, child, bus, devfn, 0);
773 if (!dev)
774 continue;
775 if (ofpci_verbose)
776 printk("PCI: dev header type: %x\n",
777 dev->hdr_type);
778
779 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
780 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
781 of_scan_pci_bridge(pbm, child, dev);
782 }
783 }
784
785 static ssize_t
786 show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
787 {
788 struct pci_dev *pdev;
789 struct device_node *dp;
790
791 pdev = to_pci_dev(dev);
792 dp = pdev->dev.archdata.prom_node;
793
794 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
795 }
796
797 static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
798
799 static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
800 {
801 struct pci_dev *dev;
802 struct pci_bus *child_bus;
803 int err;
804
805 list_for_each_entry(dev, &bus->devices, bus_list) {
806 /* we don't really care if we can create this file or
807 * not, but we need to assign the result of the call
808 * or the world will fall under alien invasion and
809 * everybody will be frozen on a spaceship ready to be
810 * eaten on alpha centauri by some green and jelly
811 * humanoid.
812 */
813 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
814 }
815 list_for_each_entry(child_bus, &bus->children, node)
816 pci_bus_register_of_sysfs(child_bus);
817 }
818
819 int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
820 unsigned int devfn,
821 int where, int size,
822 u32 *value)
823 {
824 static u8 fake_pci_config[] = {
825 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
826 0xf0, 0x80, /* Device: 0x80f0 (Fire) */
827 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
828 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
829 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
830 0x00, /* Cacheline: 0x00 */
831 0x40, /* Latency: 0x40 */
832 0x00, /* Header-Type: 0x00 normal */
833 };
834
835 *value = 0;
836 if (where >= 0 && where < sizeof(fake_pci_config) &&
837 (where + size) >= 0 &&
838 (where + size) < sizeof(fake_pci_config) &&
839 size <= sizeof(u32)) {
840 while (size--) {
841 *value <<= 8;
842 *value |= fake_pci_config[where + size];
843 }
844 }
845
846 return PCIBIOS_SUCCESSFUL;
847 }
848
849 int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
850 unsigned int devfn,
851 int where, int size,
852 u32 value)
853 {
854 return PCIBIOS_SUCCESSFUL;
855 }
856
857 struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
858 {
859 struct device_node *node = pbm->prom_node;
860 struct pci_dev *host_pdev;
861 struct pci_bus *bus;
862
863 printk("PCI: Scanning PBM %s\n", node->full_name);
864
865 /* XXX parent device? XXX */
866 bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm);
867 if (!bus) {
868 printk(KERN_ERR "Failed to create bus for %s\n",
869 node->full_name);
870 return NULL;
871 }
872 bus->secondary = pbm->pci_first_busno;
873 bus->subordinate = pbm->pci_last_busno;
874
875 bus->resource[0] = &pbm->io_space;
876 bus->resource[1] = &pbm->mem_space;
877
878 /* Create the dummy host bridge and link it in. */
879 host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
880 bus->self = host_pdev;
881
882 pci_of_scan_bus(pbm, node, bus);
883 pci_bus_add_devices(bus);
884 pci_bus_register_of_sysfs(bus);
885
886 return bus;
887 }
888
889 static void __init pci_scan_each_controller_bus(void)
890 {
891 struct pci_pbm_info *pbm;
892
893 for (pbm = pci_pbm_root; pbm; pbm = pbm->next)
894 pbm->scan_bus(pbm);
895 }
896
897 extern void power_init(void);
898
899 static int __init pcibios_init(void)
900 {
901 pci_controller_probe();
902 if (pci_pbm_root == NULL)
903 return 0;
904
905 pci_scan_each_controller_bus();
906
907 isa_init();
908 ebus_init();
909 power_init();
910
911 return 0;
912 }
913
914 subsys_initcall(pcibios_init);
915
916 void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
917 {
918 struct pci_pbm_info *pbm = pbus->sysdata;
919
920 /* Generic PCI bus probing sets these to point at
921 * &io{port,mem}_resouce which is wrong for us.
922 */
923 pbus->resource[0] = &pbm->io_space;
924 pbus->resource[1] = &pbm->mem_space;
925 }
926
927 struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
928 {
929 struct pci_pbm_info *pbm = pdev->bus->sysdata;
930 struct resource *root = NULL;
931
932 if (r->flags & IORESOURCE_IO)
933 root = &pbm->io_space;
934 if (r->flags & IORESOURCE_MEM)
935 root = &pbm->mem_space;
936
937 return root;
938 }
939
940 void pcibios_update_irq(struct pci_dev *pdev, int irq)
941 {
942 }
943
944 void pcibios_align_resource(void *data, struct resource *res,
945 resource_size_t size, resource_size_t align)
946 {
947 }
948
949 int pcibios_enable_device(struct pci_dev *dev, int mask)
950 {
951 u16 cmd, oldcmd;
952 int i;
953
954 pci_read_config_word(dev, PCI_COMMAND, &cmd);
955 oldcmd = cmd;
956
957 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
958 struct resource *res = &dev->resource[i];
959
960 /* Only set up the requested stuff */
961 if (!(mask & (1<<i)))
962 continue;
963
964 if (res->flags & IORESOURCE_IO)
965 cmd |= PCI_COMMAND_IO;
966 if (res->flags & IORESOURCE_MEM)
967 cmd |= PCI_COMMAND_MEMORY;
968 }
969
970 if (cmd != oldcmd) {
971 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
972 pci_name(dev), cmd);
973 /* Enable the appropriate bits in the PCI command register. */
974 pci_write_config_word(dev, PCI_COMMAND, cmd);
975 }
976 return 0;
977 }
978
979 void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
980 struct resource *res)
981 {
982 struct pci_pbm_info *pbm = pdev->bus->sysdata;
983 struct resource zero_res, *root;
984
985 zero_res.start = 0;
986 zero_res.end = 0;
987 zero_res.flags = res->flags;
988
989 if (res->flags & IORESOURCE_IO)
990 root = &pbm->io_space;
991 else
992 root = &pbm->mem_space;
993
994 pci_resource_adjust(&zero_res, root);
995
996 region->start = res->start - zero_res.start;
997 region->end = res->end - zero_res.start;
998 }
999 EXPORT_SYMBOL(pcibios_resource_to_bus);
1000
1001 void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
1002 struct pci_bus_region *region)
1003 {
1004 struct pci_pbm_info *pbm = pdev->bus->sysdata;
1005 struct resource *root;
1006
1007 res->start = region->start;
1008 res->end = region->end;
1009
1010 if (res->flags & IORESOURCE_IO)
1011 root = &pbm->io_space;
1012 else
1013 root = &pbm->mem_space;
1014
1015 pci_resource_adjust(res, root);
1016 }
1017 EXPORT_SYMBOL(pcibios_bus_to_resource);
1018
1019 char * __devinit pcibios_setup(char *str)
1020 {
1021 return str;
1022 }
1023
1024 /* Platform support for /proc/bus/pci/X/Y mmap()s. */
1025
1026 /* If the user uses a host-bridge as the PCI device, he may use
1027 * this to perform a raw mmap() of the I/O or MEM space behind
1028 * that controller.
1029 *
1030 * This can be useful for execution of x86 PCI bios initialization code
1031 * on a PCI card, like the xfree86 int10 stuff does.
1032 */
1033 static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
1034 enum pci_mmap_state mmap_state)
1035 {
1036 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1037 unsigned long space_size, user_offset, user_size;
1038
1039 if (mmap_state == pci_mmap_io) {
1040 space_size = (pbm->io_space.end -
1041 pbm->io_space.start) + 1;
1042 } else {
1043 space_size = (pbm->mem_space.end -
1044 pbm->mem_space.start) + 1;
1045 }
1046
1047 /* Make sure the request is in range. */
1048 user_offset = vma->vm_pgoff << PAGE_SHIFT;
1049 user_size = vma->vm_end - vma->vm_start;
1050
1051 if (user_offset >= space_size ||
1052 (user_offset + user_size) > space_size)
1053 return -EINVAL;
1054
1055 if (mmap_state == pci_mmap_io) {
1056 vma->vm_pgoff = (pbm->io_space.start +
1057 user_offset) >> PAGE_SHIFT;
1058 } else {
1059 vma->vm_pgoff = (pbm->mem_space.start +
1060 user_offset) >> PAGE_SHIFT;
1061 }
1062
1063 return 0;
1064 }
1065
1066 /* Adjust vm_pgoff of VMA such that it is the physical page offset
1067 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
1068 *
1069 * Basically, the user finds the base address for his device which he wishes
1070 * to mmap. They read the 32-bit value from the config space base register,
1071 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
1072 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
1073 *
1074 * Returns negative error code on failure, zero on success.
1075 */
1076 static int __pci_mmap_make_offset(struct pci_dev *pdev,
1077 struct vm_area_struct *vma,
1078 enum pci_mmap_state mmap_state)
1079 {
1080 unsigned long user_paddr, user_size;
1081 int i, err;
1082
1083 /* First compute the physical address in vma->vm_pgoff,
1084 * making sure the user offset is within range in the
1085 * appropriate PCI space.
1086 */
1087 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
1088 if (err)
1089 return err;
1090
1091 /* If this is a mapping on a host bridge, any address
1092 * is OK.
1093 */
1094 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1095 return err;
1096
1097 /* Otherwise make sure it's in the range for one of the
1098 * device's resources.
1099 */
1100 user_paddr = vma->vm_pgoff << PAGE_SHIFT;
1101 user_size = vma->vm_end - vma->vm_start;
1102
1103 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1104 struct resource *rp = &pdev->resource[i];
1105
1106 /* Active? */
1107 if (!rp->flags)
1108 continue;
1109
1110 /* Same type? */
1111 if (i == PCI_ROM_RESOURCE) {
1112 if (mmap_state != pci_mmap_mem)
1113 continue;
1114 } else {
1115 if ((mmap_state == pci_mmap_io &&
1116 (rp->flags & IORESOURCE_IO) == 0) ||
1117 (mmap_state == pci_mmap_mem &&
1118 (rp->flags & IORESOURCE_MEM) == 0))
1119 continue;
1120 }
1121
1122 if ((rp->start <= user_paddr) &&
1123 (user_paddr + user_size) <= (rp->end + 1UL))
1124 break;
1125 }
1126
1127 if (i > PCI_ROM_RESOURCE)
1128 return -EINVAL;
1129
1130 return 0;
1131 }
1132
1133 /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1134 * mapping.
1135 */
1136 static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1137 enum pci_mmap_state mmap_state)
1138 {
1139 vma->vm_flags |= (VM_IO | VM_RESERVED);
1140 }
1141
1142 /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1143 * device mapping.
1144 */
1145 static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1146 enum pci_mmap_state mmap_state)
1147 {
1148 /* Our io_remap_pfn_range takes care of this, do nothing. */
1149 }
1150
1151 /* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1152 * for this architecture. The region in the process to map is described by vm_start
1153 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1154 * The pci device structure is provided so that architectures may make mapping
1155 * decisions on a per-device or per-bus basis.
1156 *
1157 * Returns a negative error code on failure, zero on success.
1158 */
1159 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1160 enum pci_mmap_state mmap_state,
1161 int write_combine)
1162 {
1163 int ret;
1164
1165 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1166 if (ret < 0)
1167 return ret;
1168
1169 __pci_mmap_set_flags(dev, vma, mmap_state);
1170 __pci_mmap_set_pgprot(dev, vma, mmap_state);
1171
1172 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1173 ret = io_remap_pfn_range(vma, vma->vm_start,
1174 vma->vm_pgoff,
1175 vma->vm_end - vma->vm_start,
1176 vma->vm_page_prot);
1177 if (ret)
1178 return ret;
1179
1180 return 0;
1181 }
1182
1183 /* Return the domain nuber for this pci bus */
1184
1185 int pci_domain_nr(struct pci_bus *pbus)
1186 {
1187 struct pci_pbm_info *pbm = pbus->sysdata;
1188 int ret;
1189
1190 if (pbm == NULL || pbm->parent == NULL) {
1191 ret = -ENXIO;
1192 } else {
1193 ret = pbm->index;
1194 }
1195
1196 return ret;
1197 }
1198 EXPORT_SYMBOL(pci_domain_nr);
1199
1200 #ifdef CONFIG_PCI_MSI
1201 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1202 {
1203 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1204 int virt_irq;
1205
1206 if (!pbm->setup_msi_irq)
1207 return -EINVAL;
1208
1209 return pbm->setup_msi_irq(&virt_irq, pdev, desc);
1210 }
1211
1212 void arch_teardown_msi_irq(unsigned int virt_irq)
1213 {
1214 struct msi_desc *entry = get_irq_msi(virt_irq);
1215 struct pci_dev *pdev = entry->dev;
1216 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1217
1218 if (!pbm->teardown_msi_irq)
1219 return;
1220
1221 return pbm->teardown_msi_irq(virt_irq, pdev);
1222 }
1223 #endif /* !(CONFIG_PCI_MSI) */
1224
1225 struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1226 {
1227 return pdev->dev.archdata.prom_node;
1228 }
1229 EXPORT_SYMBOL(pci_device_to_OF_node);
1230
1231 static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
1232 {
1233 struct pci_dev *ali_isa_bridge;
1234 u8 val;
1235
1236 /* ALI sound chips generate 31-bits of DMA, a special register
1237 * determines what bit 31 is emitted as.
1238 */
1239 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
1240 PCI_DEVICE_ID_AL_M1533,
1241 NULL);
1242
1243 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
1244 if (set_bit)
1245 val |= 0x01;
1246 else
1247 val &= ~0x01;
1248 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
1249 pci_dev_put(ali_isa_bridge);
1250 }
1251
1252 int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
1253 {
1254 u64 dma_addr_mask;
1255
1256 if (pdev == NULL) {
1257 dma_addr_mask = 0xffffffff;
1258 } else {
1259 struct iommu *iommu = pdev->dev.archdata.iommu;
1260
1261 dma_addr_mask = iommu->dma_addr_mask;
1262
1263 if (pdev->vendor == PCI_VENDOR_ID_AL &&
1264 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
1265 device_mask == 0x7fffffff) {
1266 ali_sound_dma_hack(pdev,
1267 (dma_addr_mask & 0x80000000) != 0);
1268 return 1;
1269 }
1270 }
1271
1272 if (device_mask >= (1UL << 32UL))
1273 return 0;
1274
1275 return (device_mask & dma_addr_mask) == dma_addr_mask;
1276 }
1277
1278 void pci_resource_to_user(const struct pci_dev *pdev, int bar,
1279 const struct resource *rp, resource_size_t *start,
1280 resource_size_t *end)
1281 {
1282 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1283 unsigned long offset;
1284
1285 if (rp->flags & IORESOURCE_IO)
1286 offset = pbm->io_space.start;
1287 else
1288 offset = pbm->mem_space.start;
1289
1290 *start = rp->start - offset;
1291 *end = rp->end - offset;
1292 }
1293
1294 #endif /* !(CONFIG_PCI) */
WRT350N Kernel Patches