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overo: changes required to make x-load USB downloadable
[x-load.git] / board / overo / overo.c
blob8454e24fe7720eb1bf067d754ad9c96d2faf6262
1 /*
2 * (C) Copyright 2006
3 * Texas Instruments, <www.ti.com>
4 * Jian Zhang <jzhang@ti.com>
5 * Richard Woodruff <r-woodruff2@ti.com>
6 *
7 * Modified for overo
8 * Steve Sakoman <steve@sakoman.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29 #include <common.h>
30 #include <command.h>
31 #include <part.h>
32 #include <fat.h>
33 #include <asm/arch/cpu.h>
34 #include <asm/arch/bits.h>
35 #include <asm/arch/mux.h>
36 #include <asm/arch/sys_proto.h>
37 #include <asm/arch/sys_info.h>
38 #include <asm/arch/clocks.h>
39 #include <asm/arch/mem.h>
40
41 /* Used to index into DPLL parameter tables */
42 struct dpll_param {
43 unsigned int m;
44 unsigned int n;
45 unsigned int fsel;
46 unsigned int m2;
47 };
48
49 typedef struct dpll_param dpll_param;
50
51 /* Following functions are exported from lowlevel_init.S */
52 extern dpll_param *get_mpu_dpll_param();
53 extern dpll_param *get_iva_dpll_param();
54 extern dpll_param *get_core_dpll_param();
55 extern dpll_param *get_per_dpll_param();
56
57 #define __raw_readl(a) (*(volatile unsigned int *)(a))
58 #define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v))
59 #define __raw_readw(a) (*(volatile unsigned short *)(a))
60 #define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v))
61
62 /*******************************************************
63 * Routine: delay
64 * Description: spinning delay to use before udelay works
65 ******************************************************/
66 static inline void delay(unsigned long loops)
67 {
68 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
69 "bne 1b":"=r" (loops):"0"(loops));
70 }
71
72 void udelay (unsigned long usecs) {
73 delay(usecs);
74 }
75
76 /*****************************************
77 * Routine: board_init
78 * Description: Early hardware init.
79 *****************************************/
80 int board_init(void)
81 {
82 return 0;
83 }
84
85 /*************************************************************
86 * get_device_type(): tell if GP/HS/EMU/TST
87 *************************************************************/
88 u32 get_device_type(void)
89 {
90 int mode;
91 mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
92 return mode >>= 8;
93 }
94
95 /************************************************
96 * get_sysboot_value(void) - return SYS_BOOT[4:0]
97 ************************************************/
98 u32 get_sysboot_value(void)
99 {
100 int mode;
101 mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
102 return mode;
103 }
104
105 /*************************************************************
106 * Routine: get_mem_type(void) - returns the kind of memory connected
107 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
108 *************************************************************/
109 u32 get_mem_type(void)
110 {
111 u32 mem_type = get_sysboot_value();
112 switch (mem_type) {
113 case 0:
114 case 2:
115 case 4:
116 case 16:
117 case 22:
118 return GPMC_ONENAND;
119
120 case 1:
121 case 12:
122 case 15:
123 case 21:
124 case 27:
125 return GPMC_NAND;
126
127 case 3:
128 case 6:
129 return MMC_ONENAND;
130
131 case 8:
132 case 11:
133 case 14:
134 case 20:
135 case 26:
136 return GPMC_MDOC;
137
138 case 17:
139 case 18:
140 case 24:
141 return MMC_NAND;
142
143 case 7:
144 case 10:
145 case 13:
146 case 19:
147 case 25:
148 default:
149 return GPMC_NOR;
150 }
151 }
152
153 /******************************************
154 * get_cpu_rev(void) - extract version info
155 ******************************************/
156 u32 get_cpu_rev(void)
157 {
158 u32 cpuid = 0;
159 /* On ES1.0 the IDCODE register is not exposed on L4
160 * so using CPU ID to differentiate
161 * between ES2.0 and ES1.0.
162 */
163 __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
164 if ((cpuid & 0xf) == 0x0)
165 return CPU_3430_ES1;
166 else
167 return CPU_3430_ES2;
168
169 }
170
171 /******************************************
172 * cpu_is_3410(void) - returns true for 3410
173 ******************************************/
174 u32 cpu_is_3410(void)
175 {
176 int status;
177 if (get_cpu_rev() < CPU_3430_ES2) {
178 return 0;
179 } else {
180 /* read scalability status and return 1 for 3410*/
181 status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
182 /* Check whether MPU frequency is set to 266 MHz which
183 * is nominal for 3410. If yes return true else false
184 */
185 if (((status >> 8) & 0x3) == 0x2)
186 return 1;
187 else
188 return 0;
189 }
190 }
191
192 /*****************************************************************
193 * sr32 - clear & set a value in a bit range for a 32 bit address
194 *****************************************************************/
195 void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
196 {
197 u32 tmp, msk = 0;
198 msk = 1 << num_bits;
199 --msk;
200 tmp = __raw_readl(addr) & ~(msk << start_bit);
201 tmp |= value << start_bit;
202 __raw_writel(tmp, addr);
203 }
204
205 /*********************************************************************
206 * wait_on_value() - common routine to allow waiting for changes in
207 * volatile regs.
208 *********************************************************************/
209 u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
210 {
211 u32 i = 0, val;
212 do {
213 ++i;
214 val = __raw_readl(read_addr) & read_bit_mask;
215 if (val == match_value)
216 return 1;
217 if (i == bound)
218 return 0;
219 } while (1);
220 }
221
222 #ifdef CFG_3430SDRAM_DDR
223 /*********************************************************************
224 * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
225 *********************************************************************/
226 void config_3430sdram_ddr(void)
227 {
228 /* reset sdrc controller */
229 __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
230 wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
231 __raw_writel(0, SDRC_SYSCONFIG);
232
233 /* setup sdrc to ball mux */
234 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
235
236 /* SDRC put in weak */
237 // (*(unsigned int*)0x6D00008C) = 0x00000020;
238
239 /* SDRC_MCFG0 register */
240 (*(unsigned int*)0x6D000080) = 0x02584099;//from Micron
241
242 /* SDRC_ACTIM_CTRLA0 register */
243 //our value (*(unsigned int*)0x6D00009c) = 0xa29db4c6;// for 166M
244 (*(unsigned int*)0x6D00009c) = 0xaa9db4c6;// for 166M from rkw
245
246 /* SDRC_ACTIM_CTRLB0 register */
247 //from micron (*(unsigned int*)0x6D0000a0) = 0x12214;// for 166M
248
249 // (*(unsigned int*)0x6D0000a0) = 0x00011417; our value
250 (*(unsigned int*)0x6D0000a0) = 0x00011517;
251
252 /* SDRC_RFR_CTRL0 register */
253 //from micron (*(unsigned int*)0x6D0000a4) =0x54601; // for 166M
254
255 (*(unsigned int*)0x6D0000a4) =0x0004DC01;
256
257 /* Disble Power Down of CKE cuz of 1 CKE on combo part */
258 (*(unsigned int*)0x6D000070) = 0x00000081;
259
260 /* SDRC_Manual command register */
261 (*(unsigned int*)0x6D0000a8) = 0x00000000; // NOP command
262 delay(5000);
263 (*(unsigned int*)0x6D0000a8) = 0x00000001; // Precharge command
264 (*(unsigned int*)0x6D0000a8) = 0x00000002; // Auto-refresh command
265 (*(unsigned int*)0x6D0000a8) = 0x00000002; // Auto-refresh command
266
267 /* SDRC MR0 register */
268 (*(int*)0x6D000084) = 0x00000032; // Burst length =4
269 // CAS latency = 3
270 // Write Burst = Read Burst
271 // Serial Mode
272
273 /* SDRC DLLA control register */
274 (*(unsigned int*)0x6D000060) = 0x0000A;
275 delay(0x20000); // some delay
276
277 }
278 #endif /* CFG_3430SDRAM_DDR */
279
280 /*************************************************************
281 * get_sys_clk_speed - determine reference oscillator speed
282 * based on known 32kHz clock and gptimer.
283 *************************************************************/
284 u32 get_osc_clk_speed(void)
285 {
286 u32 start, cstart, cend, cdiff, val;
287
288 val = __raw_readl(PRM_CLKSRC_CTRL);
289 /* If SYS_CLK is being divided by 2, remove for now */
290 val = (val & (~BIT7)) | BIT6;
291 __raw_writel(val, PRM_CLKSRC_CTRL);
292
293 /* enable timer2 */
294 val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
295 __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
296
297 /* Enable I and F Clocks for GPT1 */
298 val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
299 __raw_writel(val, CM_ICLKEN_WKUP);
300 val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
301 __raw_writel(val, CM_FCLKEN_WKUP);
302
303 __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
304 __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
305 /* enable 32kHz source */
306 /* enabled out of reset */
307 /* determine sys_clk via gauging */
308
309 start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
310 while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
311 cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
312 while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
313 cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
314 cdiff = cend - cstart; /* get elapsed ticks */
315
316 /* based on number of ticks assign speed */
317 if (cdiff > 19000)
318 return S38_4M;
319 else if (cdiff > 15200)
320 return S26M;
321 else if (cdiff > 13000)
322 return S24M;
323 else if (cdiff > 9000)
324 return S19_2M;
325 else if (cdiff > 7600)
326 return S13M;
327 else
328 return S12M;
329 }
330
331 /******************************************************************************
332 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
333 * -- input oscillator clock frequency.
334 *
335 *****************************************************************************/
336 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
337 {
338 if (osc_clk == S38_4M)
339 *sys_clkin_sel = 4;
340 else if (osc_clk == S26M)
341 *sys_clkin_sel = 3;
342 else if (osc_clk == S19_2M)
343 *sys_clkin_sel = 2;
344 else if (osc_clk == S13M)
345 *sys_clkin_sel = 1;
346 else if (osc_clk == S12M)
347 *sys_clkin_sel = 0;
348 }
349
350 /******************************************************************************
351 * prcm_init() - inits clocks for PRCM as defined in clocks.h
352 * -- called from SRAM, or Flash (using temp SRAM stack).
353 *****************************************************************************/
354 void prcm_init(void)
355 {
356 u32 osc_clk = 0, sys_clkin_sel;
357 dpll_param *dpll_param_p;
358 u32 clk_index, sil_index;
359
360 /* Gauge the input clock speed and find out the sys_clkin_sel
361 * value corresponding to the input clock.
362 */
363 osc_clk = get_osc_clk_speed();
364 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
365
366 sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
367
368 /* If the input clock is greater than 19.2M always divide/2 */
369 if (sys_clkin_sel > 2) {
370 sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
371 clk_index = sys_clkin_sel/2;
372 } else {
373 sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
374 clk_index = sys_clkin_sel;
375 }
376
377 /* The DPLL tables are defined according to sysclk value and
378 * silicon revision. The clk_index value will be used to get
379 * the values for that input sysclk from the DPLL param table
380 * and sil_index will get the values for that SysClk for the
381 * appropriate silicon rev.
382 */
383 sil_index = get_cpu_rev() - 1;
384
385 /* Unlock MPU DPLL (slows things down, and needed later) */
386 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
387 wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
388
389 /* Getting the base address of Core DPLL param table*/
390 dpll_param_p = (dpll_param *)get_core_dpll_param();
391 /* Moving it to the right sysclk and ES rev base */
392 dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
393 /* CORE DPLL */
394 /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
395 sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
396 wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
397 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
398 sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
399 sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
400 sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
401 sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
402 sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
403 sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
404 sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
405 sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
406 sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
407 sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
408 sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
409 sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
410 wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
411
412 /* Getting the base address to PER DPLL param table*/
413 dpll_param_p = (dpll_param *)get_per_dpll_param();
414 /* Moving it to the right sysclk base */
415 dpll_param_p = dpll_param_p + clk_index;
416 /* PER DPLL */
417 sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
418 wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
419 sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
420 sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
421 sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
422 sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
423 sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
424 sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
425 sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
426 sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */
427 sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
428 wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
429
430 /* Getting the base address to MPU DPLL param table*/
431 dpll_param_p = (dpll_param *)get_mpu_dpll_param();
432 /* Moving it to the right sysclk and ES rev base */
433 dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
434 /* MPU DPLL (unlocked already) */
435 sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
436 sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
437 sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
438 sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
439 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
440 wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
441
442 /* Getting the base address to IVA DPLL param table*/
443 dpll_param_p = (dpll_param *)get_iva_dpll_param();
444 /* Moving it to the right sysclk and ES rev base */
445 dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
446 /* IVA DPLL (set to 12*20=240MHz) */
447 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
448 wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
449 sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
450 sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
451 sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
452 sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
453 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
454 wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
455
456 /* Set up GPTimers to sys_clk source only */
457 sr32(CM_CLKSEL_PER, 0, 8, 0xff);
458 sr32(CM_CLKSEL_WKUP, 0, 1, 1);
459
460 delay(5000);
461 }
462
463 /*****************************************
464 * Routine: secure_unlock
465 * Description: Setup security registers for access
466 * (GP Device only)
467 *****************************************/
468 void secure_unlock(void)
469 {
470 /* Permission values for registers -Full fledged permissions to all */
471 #define UNLOCK_1 0xFFFFFFFF
472 #define UNLOCK_2 0x00000000
473 #define UNLOCK_3 0x0000FFFF
474 /* Protection Module Register Target APE (PM_RT)*/
475 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
476 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
477 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
478 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
479
480 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
481 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
482 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
483
484 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
485 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
486 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
487 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
488
489 /* IVA Changes */
490 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
491 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
492 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
493
494 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
495 }
496
497 /**********************************************************
498 * Routine: try_unlock_sram()
499 * Description: If chip is GP type, unlock the SRAM for
500 * general use.
501 ***********************************************************/
502 void try_unlock_memory(void)
503 {
504 int mode;
505
506 /* if GP device unlock device SRAM for general use */
507 /* secure code breaks for Secure/Emulation device - HS/E/T*/
508 mode = get_device_type();
509 if (mode == GP_DEVICE)
510 secure_unlock();
511 return;
512 }
513
514 /**********************************************************
515 * Routine: s_init
516 * Description: Does early system init of muxing and clocks.
517 * - Called at time when only stack is available.
518 **********************************************************/
519
520 void s_init(void)
521 {
522 watchdog_init();
523 #ifdef CONFIG_3430_AS_3410
524 /* setup the scalability control register for
525 * 3430 to work in 3410 mode
526 */
527 __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP);
528 #endif
529 try_unlock_memory();
530 set_muxconf_regs();
531 delay(100);
532 prcm_init();
533 per_clocks_enable();
534 config_3430sdram_ddr();
535 }
536
537 /*******************************************************
538 * Routine: misc_init_r
539 * Description: Init ethernet (done here so udelay works)
540 ********************************************************/
541 int misc_init_r(void)
542 {
543 #ifdef CONFIG_MMC
544 /* REMOVE!! for proto boards only */
545 /* set vaux2 to 2.8V */
546 unsigned char byte = 0x20;
547 i2c_write(0x4B, 0x76, 1, &byte, 1);
548 byte = 0x09;
549 i2c_write(0x4B, 0x79, 1, &byte, 1);
550
551 udelay(5000);
552 #endif
553 return 0;
554 }
555
556 /******************************************************
557 * Routine: wait_for_command_complete
558 * Description: Wait for posting to finish on watchdog
559 ******************************************************/
560 void wait_for_command_complete(unsigned int wd_base)
561 {
562 int pending = 1;
563 do {
564 pending = __raw_readl(wd_base + WWPS);
565 } while (pending);
566 }
567
568 /****************************************
569 * Routine: watchdog_init
570 * Description: Shut down watch dogs
571 *****************************************/
572 void watchdog_init(void)
573 {
574 /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
575 * either taken care of by ROM (HS/EMU) or not accessible (GP).
576 * We need to take care of WD2-MPU or take a PRCM reset. WD3
577 * should not be running and does not generate a PRCM reset.
578 */
579 sr32(CM_FCLKEN_WKUP, 5, 1, 1);
580 sr32(CM_ICLKEN_WKUP, 5, 1, 1);
581 wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
582
583 __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
584 wait_for_command_complete(WD2_BASE);
585 __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
586 }
587
588 /**********************************************
589 * Routine: dram_init
590 * Description: sets uboots idea of sdram size
591 **********************************************/
592 int dram_init(void)
593 {
594 return 0;
595 }
596
597 /*****************************************************************
598 * Routine: peripheral_enable
599 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
600 ******************************************************************/
601 void per_clocks_enable(void)
602 {
603 /* Enable GP2 timer. */
604 sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
605 sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
606 sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
607
608 #ifdef CFG_NS16550
609 /* UART1 clocks */
610 sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
611 sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
612
613 /* UART 3 Clocks */
614 sr32(CM_FCLKEN_PER, 11, 1, 0x1);
615 sr32(CM_ICLKEN_PER, 11, 1, 0x1);
616
617 #endif
618
619 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
620 /* Turn on all 3 I2C clocks */
621 sr32(CM_FCLKEN1_CORE, 15, 3, 0x7);
622 sr32(CM_ICLKEN1_CORE, 15, 3, 0x7); /* I2C1,2,3 = on */
623 #endif
624
625 /* Enable the ICLK for 32K Sync Timer as its used in udelay */
626 sr32(CM_ICLKEN_WKUP, 2, 1, 0x1);
627
628 sr32(CM_FCLKEN_IVA2, 0, 32, FCK_IVA2_ON);
629 sr32(CM_FCLKEN1_CORE, 0, 32, FCK_CORE1_ON);
630 sr32(CM_ICLKEN1_CORE, 0, 32, ICK_CORE1_ON);
631 sr32(CM_ICLKEN2_CORE, 0, 32, ICK_CORE2_ON);
632 sr32(CM_FCLKEN_WKUP, 0, 32, FCK_WKUP_ON);
633 sr32(CM_ICLKEN_WKUP, 0, 32, ICK_WKUP_ON);
634 sr32(CM_FCLKEN_DSS, 0, 32, FCK_DSS_ON);
635 sr32(CM_ICLKEN_DSS, 0, 32, ICK_DSS_ON);
636 sr32(CM_FCLKEN_CAM, 0, 32, FCK_CAM_ON);
637 sr32(CM_ICLKEN_CAM, 0, 32, ICK_CAM_ON);
638 sr32(CM_FCLKEN_PER, 0, 32, FCK_PER_ON);
639 sr32(CM_ICLKEN_PER, 0, 32, ICK_PER_ON);
640
641 /* Enable GPIO5 clocks for blinky LEDs */
642 sr32(CM_FCLKEN_PER, 16, 1, 0x1); /* FCKen GPIO5 */
643 sr32(CM_ICLKEN_PER, 16, 1, 0x1); /* ICKen GPIO5 */
644
645 delay(1000);
646 }
647
648 /* Set MUX for UART, GPMC, SDRC, GPIO */
649
650 #define MUX_VAL(OFFSET,VALUE)\
651 __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
652
653 #define CP(x) (CONTROL_PADCONF_##x)
654 /*
655 * IEN - Input Enable
656 * IDIS - Input Disable
657 * PTD - Pull type Down
658 * PTU - Pull type Up
659 * DIS - Pull type selection is inactive
660 * EN - Pull type selection is active
661 * M0 - Mode 0
662 * The commented string gives the final mux configuration for that pin
663 */
664 #define MUX_DEFAULT()\
665 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
666 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
667 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
668 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
669 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
670 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
671 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
672 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
673 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
674 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
675 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
676 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
677 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
678 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
679 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
680 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
681 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
682 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
683 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
684 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
685 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
686 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
687 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
688 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
689 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
690 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
691 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
692 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
693 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
694 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
695 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
696 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
697 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
698 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
699 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
700 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
701 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
702 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
703 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
704 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
705 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
706 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
707 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
708 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
709 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
710 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
711 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
712 MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
713 MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
714 MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
715 MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
716 MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
717 MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
718 MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
719 MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
720 MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
721 MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
722 MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
723 MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
724 MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
725 MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
726 MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
727 MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
728 MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
729 MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
730 MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
731 MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
732 MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
733 MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
734 MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\
735 MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
736 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
737 MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
738 MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
739 MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
740 MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
741 MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\
742 MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
743 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
744 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
745 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
746 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\
747 MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
748 MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
749 MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
750 MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
751 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
752 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\
753 MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
754 MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
755 MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
756 MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
757 MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
758 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
759 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
760 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
761 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
762 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
763 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
764 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
765 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
766 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
767 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
768 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
769 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
770 MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
771 MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
772 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) /*I2C2_SCL*/\
773 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) /*I2C2_SDA*/\
774 MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
775 MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
776 MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
777 MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
778 MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
779 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
780 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
781 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
782 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
783 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
784 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
785 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
786 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
787 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
788 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
789 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
790 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
791 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
792 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
793 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
794 MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
795 MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
796 MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
797 MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
798 MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
799 MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
800 MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
801 MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
802 MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
803 MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
804 MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/
805
806 /**********************************************************
807 * Routine: set_muxconf_regs
808 * Description: Setting up the configuration Mux registers
809 * specific to the hardware. Many pins need
810 * to be moved from protect to primary mode.
811 *********************************************************/
812 void set_muxconf_regs(void)
813 {
814 MUX_DEFAULT();
815 }
816
817 /**********************************************************
818 * Routine: nand+_init
819 * Description: Set up nand for nand and jffs2 commands
820 *********************************************************/
821
822 int nand_init(void)
823 {
824 /* global settings */
825 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
826 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
827 __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
828
829 /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
830 * We configure only GPMC CS0 with required values. Configiring other devices
831 * at other CS is done in u-boot. So we don't have to bother doing it here.
832 */
833 __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
834 delay(1000);
835
836 if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
837 __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
838 __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
839 __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
840 __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
841 __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
842 __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
843
844 /* Enable the GPMC Mapping */
845 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
846 ((NAND_BASE_ADR>>24) & 0x3F) |
847 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
848 delay(2000);
849
850 if (nand_chip()) {
851 #ifdef CFG_PRINTF
852 printf("Unsupported Chip!\n");
853 #endif
854 return 1;
855 }
856
857 }
858
859 if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
860 __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
861 __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
862 __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
863 __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
864 __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
865 __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
866
867 /* Enable the GPMC Mapping */
868 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
869 ((ONENAND_BASE>>24) & 0x3F) |
870 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
871 delay(2000);
872
873 if (onenand_chip()) {
874 #ifdef CFG_PRINTF
875 printf("OneNAND Unsupported !\n");
876 #endif
877 return 1;
878 }
879 }
880 return 0;
881 }
882
883 /* optionally do something like blinking LED */
884 void board_hang(void)
885 {
886 while (0)
887 ;
888 }
889
890 /******************************************************************************
891 * Dummy function to handle errors for EABI incompatibility
892 *****************************************************************************/
893 void raise(void)
894 {
895 }
896
897 /******************************************************************************
898 * Dummy function to handle errors for EABI incompatibility
899 *****************************************************************************/
900 void abort(void)
901 {
902 }
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