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beagle: fix missing parentheses in while statement (cleanup error)
[x-load.git] / board / omap3530beagle / omap3530beagle.c
blob79e6d71f0ef5282ae3dd8836bff8256c0be472d7
1 /*
2 * (C) Copyright 2006
3 * Texas Instruments, <www.ti.com>
4 * Jian Zhang <jzhang@ti.com>
5 * Richard Woodruff <r-woodruff2@ti.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26 #include <common.h>
27 #include <command.h>
28 #include <part.h>
29 #include <fat.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/bits.h>
32 #include <asm/arch/mux.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/arch/sys_info.h>
35 #include <asm/arch/clocks.h>
36 #include <asm/arch/mem.h>
37
38 /* Used to index into DPLL parameter tables */
39 struct dpll_param {
40 unsigned int m;
41 unsigned int n;
42 unsigned int fsel;
43 unsigned int m2;
44 };
45
46 typedef struct dpll_param dpll_param;
47
48 /* Following functions are exported from lowlevel_init.S */
49 extern dpll_param *get_mpu_dpll_param();
50 extern dpll_param *get_iva_dpll_param();
51 extern dpll_param *get_core_dpll_param();
52 extern dpll_param *get_per_dpll_param();
53
54 #define __raw_readl(a) (*(volatile unsigned int *)(a))
55 #define __raw_writel(v, a) (*(volatile unsigned int *)(a) = (v))
56 #define __raw_readw(a) (*(volatile unsigned short *)(a))
57 #define __raw_writew(v, a) (*(volatile unsigned short *)(a) = (v))
58
59 /*******************************************************
60 * Routine: delay
61 * Description: spinning delay to use before udelay works
62 ******************************************************/
63 static inline void delay(unsigned long loops)
64 {
65 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
66 "bne 1b":"=r" (loops):"0"(loops));
67 }
68
69 /*****************************************
70 * Routine: board_init
71 * Description: Early hardware init.
72 *****************************************/
73 int board_init(void)
74 {
75 return 0;
76 }
77
78 /*************************************************************
79 * get_device_type(): tell if GP/HS/EMU/TST
80 *************************************************************/
81 u32 get_device_type(void)
82 {
83 int mode;
84 mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
85 return mode >>= 8;
86 }
87
88 /************************************************
89 * get_sysboot_value(void) - return SYS_BOOT[4:0]
90 ************************************************/
91 u32 get_sysboot_value(void)
92 {
93 int mode;
94 mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
95 return mode;
96 }
97
98 /*************************************************************
99 * Routine: get_mem_type(void) - returns the kind of memory connected
100 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
101 *************************************************************/
102 u32 get_mem_type(void)
103 {
104 u32 mem_type = get_sysboot_value();
105 switch (mem_type) {
106 case 0:
107 case 2:
108 case 4:
109 case 16:
110 case 22:
111 return GPMC_ONENAND;
112
113 case 1:
114 case 12:
115 case 15:
116 case 21:
117 case 27:
118 return GPMC_NAND;
119
120 case 3:
121 case 6:
122 return MMC_ONENAND;
123
124 case 8:
125 case 11:
126 case 14:
127 case 20:
128 case 26:
129 return GPMC_MDOC;
130
131 case 17:
132 case 18:
133 case 24:
134 return MMC_NAND;
135
136 case 7:
137 case 10:
138 case 13:
139 case 19:
140 case 25:
141 default:
142 return GPMC_NOR;
143 }
144 }
145
146 /******************************************
147 * get_cpu_rev(void) - extract version info
148 ******************************************/
149 u32 get_cpu_rev(void)
150 {
151 u32 cpuid = 0;
152 /* On ES1.0 the IDCODE register is not exposed on L4
153 * so using CPU ID to differentiate
154 * between ES2.0 and ES1.0.
155 */
156 __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
157 if ((cpuid & 0xf) == 0x0)
158 return CPU_3430_ES1;
159 else
160 return CPU_3430_ES2;
161
162 }
163
164 /******************************************
165 * cpu_is_3410(void) - returns true for 3410
166 ******************************************/
167 u32 cpu_is_3410(void)
168 {
169 int status;
170 if (get_cpu_rev() < CPU_3430_ES2) {
171 return 0;
172 } else {
173 /* read scalability status and return 1 for 3410*/
174 status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
175 /* Check whether MPU frequency is set to 266 MHz which
176 * is nominal for 3410. If yes return true else false
177 */
178 if (((status >> 8) & 0x3) == 0x2)
179 return 1;
180 else
181 return 0;
182 }
183 }
184
185 /*****************************************************************
186 * sr32 - clear & set a value in a bit range for a 32 bit address
187 *****************************************************************/
188 void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
189 {
190 u32 tmp, msk = 0;
191 msk = 1 << num_bits;
192 --msk;
193 tmp = __raw_readl(addr) & ~(msk << start_bit);
194 tmp |= value << start_bit;
195 __raw_writel(tmp, addr);
196 }
197
198 /*********************************************************************
199 * wait_on_value() - common routine to allow waiting for changes in
200 * volatile regs.
201 *********************************************************************/
202 u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
203 {
204 u32 i = 0, val;
205 do {
206 ++i;
207 val = __raw_readl(read_addr) & read_bit_mask;
208 if (val == match_value)
209 return 1;
210 if (i == bound)
211 return 0;
212 } while (1);
213 }
214
215 #ifdef CFG_3430SDRAM_DDR
216 /*********************************************************************
217 * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
218 *********************************************************************/
219 void config_3430sdram_ddr(void)
220 {
221 /* reset sdrc controller */
222 __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
223 wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
224 __raw_writel(0, SDRC_SYSCONFIG);
225
226 /* setup sdrc to ball mux */
227 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
228
229 /* set mdcfg */
230 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
231
232 /* set timing */
233 if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
234 __raw_writel(INFINEON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
235 __raw_writel(INFINEON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
236 }
237 if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
238 __raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
239 __raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
240 }
241
242 __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
243 __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
244
245 /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
246 __raw_writel(CMD_NOP, SDRC_MANUAL_0);
247 delay(5000);
248 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
249 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
250 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
251
252 /* set mr0 */
253 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
254
255 /* set up dll */
256 __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
257 delay(0x2000); /* give time to lock */
258
259 }
260 #endif /* CFG_3430SDRAM_DDR */
261
262 /*************************************************************
263 * get_sys_clk_speed - determine reference oscillator speed
264 * based on known 32kHz clock and gptimer.
265 *************************************************************/
266 u32 get_osc_clk_speed(void)
267 {
268 u32 start, cstart, cend, cdiff, val;
269
270 val = __raw_readl(PRM_CLKSRC_CTRL);
271 /* If SYS_CLK is being divided by 2, remove for now */
272 val = (val & (~BIT7)) | BIT6;
273 __raw_writel(val, PRM_CLKSRC_CTRL);
274
275 /* enable timer2 */
276 val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
277 __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
278
279 /* Enable I and F Clocks for GPT1 */
280 val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
281 __raw_writel(val, CM_ICLKEN_WKUP);
282 val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
283 __raw_writel(val, CM_FCLKEN_WKUP);
284
285 __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
286 __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
287 /* enable 32kHz source */
288 /* enabled out of reset */
289 /* determine sys_clk via gauging */
290
291 start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
292 while (__raw_readl(S32K_CR) < start) ; /* dead loop till start time */
293 cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
294 while (__raw_readl(S32K_CR) < (start + 20)) ; /* wait for 40 cycles */
295 cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
296 cdiff = cend - cstart; /* get elapsed ticks */
297
298 /* based on number of ticks assign speed */
299 if (cdiff > 19000)
300 return S38_4M;
301 else if (cdiff > 15200)
302 return S26M;
303 else if (cdiff > 13000)
304 return S24M;
305 else if (cdiff > 9000)
306 return S19_2M;
307 else if (cdiff > 7600)
308 return S13M;
309 else
310 return S12M;
311 }
312
313 /******************************************************************************
314 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
315 * -- input oscillator clock frequency.
316 *
317 *****************************************************************************/
318 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
319 {
320 if (osc_clk == S38_4M)
321 *sys_clkin_sel = 4;
322 else if (osc_clk == S26M)
323 *sys_clkin_sel = 3;
324 else if (osc_clk == S19_2M)
325 *sys_clkin_sel = 2;
326 else if (osc_clk == S13M)
327 *sys_clkin_sel = 1;
328 else if (osc_clk == S12M)
329 *sys_clkin_sel = 0;
330 }
331
332 /******************************************************************************
333 * prcm_init() - inits clocks for PRCM as defined in clocks.h
334 * -- called from SRAM, or Flash (using temp SRAM stack).
335 *****************************************************************************/
336 void prcm_init(void)
337 {
338 u32 osc_clk = 0, sys_clkin_sel;
339 dpll_param *dpll_param_p;
340 u32 clk_index, sil_index;
341
342 /* Gauge the input clock speed and find out the sys_clkin_sel
343 * value corresponding to the input clock.
344 */
345 osc_clk = get_osc_clk_speed();
346 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
347
348 sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
349
350 /* If the input clock is greater than 19.2M always divide/2 */
351 if (sys_clkin_sel > 2) {
352 sr32(PRM_CLKSRC_CTRL, 6, 2, 2); /* input clock divider */
353 clk_index = sys_clkin_sel / 2;
354 } else {
355 sr32(PRM_CLKSRC_CTRL, 6, 2, 1); /* input clock divider */
356 clk_index = sys_clkin_sel;
357 }
358
359 sr32(PRM_CLKSRC_CTRL, 0, 2, 0);/* Bypass mode: T2 inputs a square clock */
360
361 /* The DPLL tables are defined according to sysclk value and
362 * silicon revision. The clk_index value will be used to get
363 * the values for that input sysclk from the DPLL param table
364 * and sil_index will get the values for that SysClk for the
365 * appropriate silicon rev.
366 */
367 sil_index = get_cpu_rev() - 1;
368
369 /* Unlock MPU DPLL (slows things down, and needed later) */
370 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
371 wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
372
373 /* Getting the base address of Core DPLL param table */
374 dpll_param_p = (dpll_param *) get_core_dpll_param();
375 /* Moving it to the right sysclk and ES rev base */
376 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
377 /* CORE DPLL */
378 /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
379 sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
380 wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
381
382 /* For 3430 ES1.0 Errata 1.50, default value directly doesnt
383 work. write another value and then default value. */
384 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2 + 1); /* m3x2 */
385 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
386 sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
387 sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
388 sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
389 sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
390 sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
391 sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
392 sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
393 sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
394 sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
395 sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
396 sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
397 sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
398 wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
399
400 /* Getting the base address to PER DPLL param table */
401 dpll_param_p = (dpll_param *) get_per_dpll_param();
402 /* Moving it to the right sysclk base */
403 dpll_param_p = dpll_param_p + clk_index;
404 /* PER DPLL */
405 sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
406 wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
407 sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
408 sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
409 sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
410 sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
411 sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
412 sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
413 sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
414 sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel); /* FREQSEL */
415 sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
416 wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
417
418 /* Getting the base address to MPU DPLL param table */
419 dpll_param_p = (dpll_param *) get_mpu_dpll_param();
420
421 /* Moving it to the right sysclk and ES rev base */
422 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
423
424 /* MPU DPLL (unlocked already) */
425 sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
426 sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
427 sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
428 sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
429 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
430 wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
431
432 /* Getting the base address to IVA DPLL param table */
433 dpll_param_p = (dpll_param *) get_iva_dpll_param();
434 /* Moving it to the right sysclk and ES rev base */
435 dpll_param_p = dpll_param_p + 3 * clk_index + sil_index;
436 /* IVA DPLL (set to 12*20=240MHz) */
437 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
438 wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
439 sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
440 sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
441 sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
442 sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
443 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
444 wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
445
446 /* Set up GPTimers to sys_clk source only */
447 sr32(CM_CLKSEL_PER, 0, 8, 0xff);
448 sr32(CM_CLKSEL_WKUP, 0, 1, 1);
449
450 delay(5000);
451 }
452
453 /*****************************************
454 * Routine: secure_unlock
455 * Description: Setup security registers for access
456 * (GP Device only)
457 *****************************************/
458 void secure_unlock(void)
459 {
460 /* Permission values for registers -Full fledged permissions to all */
461 #define UNLOCK_1 0xFFFFFFFF
462 #define UNLOCK_2 0x00000000
463 #define UNLOCK_3 0x0000FFFF
464 /* Protection Module Register Target APE (PM_RT) */
465 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
466 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
467 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
468 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
469
470 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
471 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
472 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
473
474 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
475 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
476 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
477 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
478
479 /* IVA Changes */
480 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
481 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
482 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
483
484 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
485 }
486
487 /**********************************************************
488 * Routine: try_unlock_sram()
489 * Description: If chip is GP type, unlock the SRAM for
490 * general use.
491 ***********************************************************/
492 void try_unlock_memory(void)
493 {
494 int mode;
495
496 /* if GP device unlock device SRAM for general use */
497 /* secure code breaks for Secure/Emulation device - HS/E/T */
498 mode = get_device_type();
499 if (mode == GP_DEVICE)
500 secure_unlock();
501 return;
502 }
503
504 /**********************************************************
505 * Routine: s_init
506 * Description: Does early system init of muxing and clocks.
507 * - Called at time when only stack is available.
508 **********************************************************/
509
510 void s_init(void)
511 {
512 watchdog_init();
513 #ifdef CONFIG_3430_AS_3410
514 /* setup the scalability control register for
515 * 3430 to work in 3410 mode
516 */
517 __raw_writel(0x5ABF, CONTROL_SCALABLE_OMAP_OCP);
518 #endif
519 try_unlock_memory();
520 set_muxconf_regs();
521 delay(100);
522 prcm_init();
523 per_clocks_enable();
524 config_3430sdram_ddr();
525 }
526
527 /*******************************************************
528 * Routine: misc_init_r
529 * Description: Init ethernet (done here so udelay works)
530 ********************************************************/
531 int misc_init_r(void)
532 {
533 return 0;
534 }
535
536 /******************************************************
537 * Routine: wait_for_command_complete
538 * Description: Wait for posting to finish on watchdog
539 ******************************************************/
540 void wait_for_command_complete(unsigned int wd_base)
541 {
542 int pending = 1;
543 do {
544 pending = __raw_readl(wd_base + WWPS);
545 } while (pending);
546 }
547
548 /****************************************
549 * Routine: watchdog_init
550 * Description: Shut down watch dogs
551 *****************************************/
552 void watchdog_init(void)
553 {
554 /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
555 * either taken care of by ROM (HS/EMU) or not accessible (GP).
556 * We need to take care of WD2-MPU or take a PRCM reset. WD3
557 * should not be running and does not generate a PRCM reset.
558 */
559 sr32(CM_FCLKEN_WKUP, 5, 1, 1);
560 sr32(CM_ICLKEN_WKUP, 5, 1, 1);
561 wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
562
563 __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
564 wait_for_command_complete(WD2_BASE);
565 __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
566 }
567
568 /**********************************************
569 * Routine: dram_init
570 * Description: sets uboots idea of sdram size
571 **********************************************/
572 int dram_init(void)
573 {
574 return 0;
575 }
576
577 /*****************************************************************
578 * Routine: peripheral_enable
579 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
580 ******************************************************************/
581 void per_clocks_enable(void)
582 {
583 /* Enable GP2 timer. */
584 sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
585 sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
586 sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
587
588 #ifdef CFG_NS16550
589 /* UART1 clocks */
590 sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
591 sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
592
593 /* UART 3 Clocks */
594 sr32(CM_FCLKEN_PER, 11, 1, 0x1);
595 sr32(CM_ICLKEN_PER, 11, 1, 0x1);
596
597 #endif
598
599 /* Enable GPIO5 clocks for blinky LEDs */
600 sr32(CM_FCLKEN_PER, 16, 1, 0x1); /* FCKen GPIO5 */
601 sr32(CM_ICLKEN_PER, 16, 1, 0x1); /* ICKen GPIO5 */
602
603 delay(1000);
604 }
605
606 /* Set MUX for UART, GPMC, SDRC, GPIO */
607
608 #define MUX_VAL(OFFSET,VALUE)\
609 __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
610
611 #define CP(x) (CONTROL_PADCONF_##x)
612 /*
613 * IEN - Input Enable
614 * IDIS - Input Disable
615 * PTD - Pull type Down
616 * PTU - Pull type Up
617 * DIS - Pull type selection is inactive
618 * EN - Pull type selection is active
619 * M0 - Mode 0
620 * The commented string gives the final mux configuration for that pin
621 */
622 #define MUX_DEFAULT()\
623 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
624 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
625 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
626 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
627 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
628 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
629 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
630 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
631 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
632 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
633 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
634 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
635 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
636 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
637 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
638 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
639 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
640 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
641 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
642 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
643 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
644 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
645 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
646 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
647 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
648 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
649 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
650 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
651 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
652 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
653 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
654 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
655 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
656 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
657 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
658 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
659 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
660 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
661 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
662 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
663 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
664 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
665 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
666 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
667 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
668 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
669 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
670 MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
671 MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
672 MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
673 MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
674 MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
675 MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
676 MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
677 MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
678 MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
679 MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
680 MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
681 MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
682 MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
683 MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
684 MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
685 MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
686 MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
687 MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
688 MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
689 MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
690 MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
691 MUX_VAL(CP(GPMC_nCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\
692 MUX_VAL(CP(GPMC_nCS6), (IEN | PTD | DIS | M1)) /*GPMC_nCS6*/\
693 MUX_VAL(CP(GPMC_nCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7*/\
694 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
695 MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
696 MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
697 MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
698 MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
699 MUX_VAL(CP(GPMC_nBE1), (IEN | PTD | DIS | M0)) /*GPIO_61*/\
700 MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
701 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
702 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
703 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPIO_64*/\
704 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPIO_65*/\
705 MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
706 MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
707 MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
708 MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
709 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
710 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
711 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M4)) /*GPIO_149*/\
712 MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150*/\
713 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
714 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX */\
715 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) /*UART3_RTS_SD */\
716 MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
717 MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
718 MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
719 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
720 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
721 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
722 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
723 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
724 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
725 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
726 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
727 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
728 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
729 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
730 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
731 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
732 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
733 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
734 MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
735 MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
736 MUX_VAL(CP(ETK_D0), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
737 MUX_VAL(CP(ETK_D1), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
738 MUX_VAL(CP(ETK_D2), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
739 MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
740 MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
741 MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
742 MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
743 MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29 */\
744 MUX_VAL(CP(sdrc_cke0), (IDIS | PTU | EN | M0)) /*sdrc_cke0 */\
745 MUX_VAL(CP(sdrc_cke1), (IDIS | PTD | DIS | M7)) /*sdrc_cke1 not used*/
746
747 /**********************************************************
748 * Routine: set_muxconf_regs
749 * Description: Setting up the configuration Mux registers
750 * specific to the hardware. Many pins need
751 * to be moved from protect to primary mode.
752 *********************************************************/
753 void set_muxconf_regs(void)
754 {
755 MUX_DEFAULT();
756 }
757
758 /**********************************************************
759 * Routine: nand+_init
760 * Description: Set up nand for nand and jffs2 commands
761 *********************************************************/
762
763 int nand_init(void)
764 {
765 /* global settings */
766 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
767 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
768 __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
769
770 /* Set the GPMC Vals, NAND is mapped at CS0, oneNAND at CS0.
771 * We configure only GPMC CS0 with required values. Configiring other devices
772 * at other CS is done in u-boot. So we don't have to bother doing it here.
773 */
774 __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
775 delay(1000);
776
777 if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)) {
778 __raw_writel(M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
779 __raw_writel(M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
780 __raw_writel(M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
781 __raw_writel(M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
782 __raw_writel(M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
783 __raw_writel(M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
784
785 /* Enable the GPMC Mapping */
786 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
787 ((NAND_BASE_ADR>>24) & 0x3F) |
788 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
789 delay(2000);
790
791 if (nand_chip()) {
792 #ifdef CFG_PRINTF
793 printf("Unsupported Chip!\n");
794 #endif
795 return 1;
796 }
797
798 }
799
800 if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)) {
801 __raw_writel(ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
802 __raw_writel(ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
803 __raw_writel(ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
804 __raw_writel(ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
805 __raw_writel(ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
806 __raw_writel(ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
807
808 /* Enable the GPMC Mapping */
809 __raw_writel((((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
810 ((ONENAND_BASE>>24) & 0x3F) |
811 (1<<6)), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
812 delay(2000);
813
814 if (onenand_chip()) {
815 #ifdef CFG_PRINTF
816 printf("OneNAND Unsupported !\n");
817 #endif
818 return 1;
819 }
820 }
821 return 0;
822 }
823
824 #define DEBUG_LED1 149 /* gpio */
825 #define DEBUG_LED2 150 /* gpio */
826
827 void blinkLEDs()
828 {
829 void *p;
830
831 /* Alternately turn the LEDs on and off */
832 p = (unsigned long *)OMAP34XX_GPIO5_BASE;
833 while (1) {
834 /* turn LED1 on and LED2 off */
835 *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED1 % 32);
836 *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED2 % 32);
837
838 /* delay for a while */
839 delay(1000);
840
841 /* turn LED1 off and LED2 on */
842 *(unsigned long *)(p + 0x90) = 1 << (DEBUG_LED1 % 32);
843 *(unsigned long *)(p + 0x94) = 1 << (DEBUG_LED2 % 32);
844
845 /* delay for a while */
846 delay(1000);
847 }
848 }
849
850 typedef int (mmc_boot_addr) (void);
851 int mmc_boot(unsigned char *buf)
852 {
853
854 long size = 0;
855 #ifdef CFG_CMD_FAT
856 block_dev_desc_t *dev_desc = NULL;
857 unsigned char ret = 0;
858
859 printf("Starting X-loader on MMC \n");
860
861 ret = mmc_init(1);
862 if (ret == 0) {
863 printf("\n MMC init failed \n");
864 return 0;
865 }
866
867 dev_desc = mmc_get_dev(0);
868 fat_register_device(dev_desc, 1);
869 size = file_fat_read("u-boot.bin", buf, 0);
870 if (size == -1)
871 return 0;
872
873 printf("\n%ld Bytes Read from MMC \n", size);
874
875 printf("Starting OS Bootloader from MMC...\n");
876 #endif
877 return size;
878 }
879
880 /* optionally do something like blinking LED */
881 void board_hang(void)
882 {
883 while (1)
884 blinkLEDs();
885 }
X-Loader