include/configs/omap3530beagle.h

   1 /*
   2  * (C) Copyright 2006
   3  * Texas Instruments <www.ti.com>
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  *
   6  * X-Loader Configuation settings for the TI OMAP SDP3430 board.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /* serial printf facility takes about 3.5K */
  31 #define CFG_PRINTF
  32 //#undef CFG_PRINTF
  33
  34 /*
  35  * High Level Configuration Options
  36  */
  37 #define CONFIG_ARMCORTEXA8      1       /* This is an ARM V7 CPU core */
  38 #define CONFIG_OMAP             1       /* in a TI OMAP core */
  39 #define CONFIG_OMAP34XX         1       /* which is a 34XX */
  40 #define CONFIG_OMAP3430         1       /* which is in a 3430 */
  41 #define CONFIG_OMAP3_BEAGLE     1       /* working with BEAGLE */
  42
  43 #define CONFIG_BEAGLE_REV2       1
  44
  45 /* Enable the below macro if MMC boot support is required */
  46 #define CONFIG_MMC      1
  47 #if defined(CONFIG_MMC)
  48         #define CFG_CMD_MMC     1
  49         #define CFG_CMD_FAT     1
  50 #endif
  51
  52 #include <asm/arch/cpu.h>        /* get chip and board defs */
  53
  54 /* uncomment it if you need timer based udelay(). it takes about 250 bytes */
  55 //#define CFG_UDELAY
  56
  57 /* Clock Defines */
  58 #define V_OSCK  26000000  /* Clock output from T2 */
  59
  60 #if (V_OSCK > 19200000)
  61 #define V_SCLK  (V_OSCK >> 1)
  62 #else
  63 #define V_SCLK  V_OSCK
  64 #endif
  65
  66 //#define PRCM_CLK_CFG2_266MHZ  1       /* VDD2=1.15v - 133MHz DDR */
  67 #define PRCM_CLK_CFG2_332MHZ    1       /* VDD2=1.15v - 166MHz DDR */
  68 #define PRCM_PCLK_OPP2          1       /* ARM=381MHz - VDD1=1.20v */
  69
  70 /* Memory type */
  71 #define CFG_3430SDRAM_DDR       1
  72
  73 /* The actual register values are defined in u-boot- mem.h */
  74 /* SDRAM Bank Allocation method */
  75 //#define SDRC_B_R_C            1
  76 //#define SDRC_B1_R_B0_C        1
  77 #define SDRC_R_B_C              1
  78
  79 #define NAND_BASE_ADR   NAND_BASE
  80 #define ONENAND_BASE    ONENAND_MAP
  81 #define ONENAND_ADDR    ONENAND_BASE
  82
  83 #define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
  84
  85 #ifdef CFG_PRINTF
  86
  87 #define CFG_NS16550
  88 #define CFG_NS16550_SERIAL
  89 #define CFG_NS16550_REG_SIZE    -4
  90 #define CFG_NS16550_CLK         48000000
  91 #define CFG_NS16550_COM3        OMAP34XX_UART3
  92
  93 /*
  94  * select serial console configuration
  95  */
  96 #define CONFIG_SERIAL1          3       /* use UART3 */
  97 #define CONFIG_CONS_INDEX       3
  98
  99 #define CONFIG_BAUDRATE         115200
 100 #define CFG_PBSIZE              256
 101
 102 #endif /* CFG_PRINTF */
 103
 104 /*
 105  * Miscellaneous configurable options
 106  */
 107 #define CFG_LOADADDR            0x80008000
 108
 109 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 110
 111 /*-----------------------------------------------------------------------
 112  * Stack sizes
 113  *
 114  * The stack sizes are set up in start.S using the settings below
 115  */
 116 #define CONFIG_STACKSIZE        (128*1024) /* regular stack */
 117
 118 /*-----------------------------------------------------------------------
 119  * Board NAND Info.
 120  */
 121
 122
 123 #define CFG_NAND_K9F1G08R0A
 124 #define NAND_16BIT
 125
 126 /* NAND is partitioned:
 127  * 0x00000000 - 0x0007FFFF  Booting Image
 128  * 0x00080000 - 0x000BFFFF  U-Boot Image
 129  * 0x000C0000 - 0x000FFFFF  U-Boot Env Data (X-loader doesn't care)
 130  * 0x00100000 - 0x002FFFFF  Kernel Image
 131  * 0x00300000 - 0x08000000  depends on application
 132  */
 133 #define NAND_UBOOT_START        0x0080000 /* Leaving first 4 blocks for x-load */
 134 #define NAND_UBOOT_END          0x0160000 /* Giving a space of 2 blocks = 256KB */
 135 #define NAND_BLOCK_SIZE         0x20000
 136
 137 #define GPMC_CONFIG             (OMAP34XX_GPMC_BASE+0x50)
 138 #define GPMC_NAND_COMMAND_0     (OMAP34XX_GPMC_BASE+0x7C)
 139 #define GPMC_NAND_ADDRESS_0     (OMAP34XX_GPMC_BASE+0x80)
 140 #define GPMC_NAND_DATA_0        (OMAP34XX_GPMC_BASE+0x84)
 141
 142 #ifdef NAND_16BIT
 143 #define WRITE_NAND_COMMAND(d, adr) \
 144         do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0)
 145 #define WRITE_NAND_ADDRESS(d, adr) \
 146         do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
 147 #define WRITE_NAND(d, adr) \
 148         do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0)
 149 #define READ_NAND(adr) \
 150         (*(volatile u16 *)GPMC_NAND_DATA_0)
 151 #define NAND_WAIT_READY()
 152 #define NAND_WP_OFF()  \
 153         do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
 154 #define NAND_WP_ON()  \
 155          do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
 156
 157 #else /* to support 8-bit NAND devices */
 158 #define WRITE_NAND_COMMAND(d, adr) \
 159         do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0)
 160 #define WRITE_NAND_ADDRESS(d, adr) \
 161          do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
 162 #define WRITE_NAND(d, adr) \
 163         do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0)
 164 #define READ_NAND(adr) \
 165         (*(volatile u8 *)GPMC_NAND_DATA_0);
 166 #define NAND_WAIT_READY()
 167 #define NAND_WP_OFF()  \
 168         do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
 169 #define NAND_WP_ON()  \
 170         do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
 171
 172 #endif
 173
 174 #define NAND_CTL_CLRALE(adr)
 175 #define NAND_CTL_SETALE(adr)
 176 #define NAND_CTL_CLRCLE(adr)
 177 #define NAND_CTL_SETCLE(adr)
 178 #define NAND_DISABLE_CE()
 179 #define NAND_ENABLE_CE()
 180
 181 /*-----------------------------------------------------------------------
 182  * Board oneNAND Info.
 183  */
 184 #define CFG_SYNC_BURST_READ     1
 185
 186 /* OneNAND is partitioned:
 187  *   0x0000000 - 0x0080000  X-Loader
 188  *   0x0080000 - 0x00c0000   U-boot Image
 189  *   0x00c0000 - 0x00e0000   U-Boot Env Data (X-loader doesn't care)
 190  *   0x00e0000 - 0x0120000   Kernel Image
 191  *   0x0120000 - 0x4000000   depends on application
 192  */
 193
 194 #define ONENAND_START_BLOCK     4
 195 #define ONENAND_END_BLOCK       6
 196 #define ONENAND_PAGE_SIZE       2048     /* 2KB */
 197 #define ONENAND_BLOCK_SIZE      0x20000  /* 128KB */
 198
 199 #endif /* __CONFIG_H */
 200