xbmc/utils/fastmemcpy.c

   1 /*****************************************************************************
   2  * fastmemcpy.h : fast memcpy routines
   3  *****************************************************************************
   4  * $Id: fastmemcpy.h 13905 2006-01-12 23:10:04Z dionoea $
   5  *
   6  * Authors: various Linux kernel hackers
   7  *          various MPlayer hackers
   8  *          Nick Kurshev <nickols_k@mail.ru>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301, USA.
  23  *****************************************************************************/
  24 #if !defined(_WIN32) && !defined(__ppc__) && !defined(__powerpc__) && !defined(__arm__)
  25 #define HAVE_MMX2
  26 #define HAVE_SSE
  27
  28 /*
  29   aclib - advanced C library ;)
  30   This file contains functions which improve and expand standard C-library
  31 */
  32 #include <stddef.h>
  33
  34 #define BLOCK_SIZE 4096
  35 #define CONFUSION_FACTOR 0
  36 /*Feel free to fine-tune the above 2, it might be possible to get some speedup with them :)*/
  37
  38 /*#define STATISTICS*/
  39
  40 #ifndef HAVE_SSE2
  41 /*
  42    P3 processor has only one SSE decoder so can execute only 1 sse insn per
  43    cpu clock, but it has 3 mmx decoders (include load/store unit)
  44    and executes 3 mmx insns per cpu clock.
  45    P4 processor has some chances, but after reading:
  46    http://www.emulators.com/pentium4.htm
  47    I have doubts. Anyway SSE2 version of this code can be written better.
  48 */
  49 #undef HAVE_SSE
  50 #endif
  51
  52
  53 /*
  54  This part of code was taken by me from Linux-2.4.3 and slightly modified
  55 for MMX, MMX2, SSE instruction set. I have done it since linux uses page aligned
  56 blocks but mplayer uses weakly ordered data and original sources can not
  57 speedup them. Only using PREFETCHNTA and MOVNTQ together have effect!
  58
  59 >From IA-32 Intel Architecture Software Developer's Manual Volume 1,
  60
  61 Order Number 245470:
  62 "10.4.6. Cacheability Control, Prefetch, and Memory Ordering Instructions"
  63
  64 Data referenced by a program can be temporal (data will be used again) or
  65 non-temporal (data will be referenced once and not reused in the immediate
  66 future). To make efficient use of the processor's caches, it is generally
  67 desirable to cache temporal data and not cache non-temporal data. Overloading
  68 the processor's caches with non-temporal data is sometimes referred to as
  69 "polluting the caches".
  70 The non-temporal data is written to memory with Write-Combining semantics.
  71
  72 The PREFETCHh instructions permits a program to load data into the processor
  73 at a suggested cache level, so that it is closer to the processors load and
  74 store unit when it is needed. If the data is already present in a level of
  75 the cache hierarchy that is closer to the processor, the PREFETCHh instruction
  76 will not result in any data movement.
  77 But we should you PREFETCHNTA: Non-temporal data fetch data into location
  78 close to the processor, minimizing cache pollution.
  79
  80 The MOVNTQ (store quadword using non-temporal hint) instruction stores
  81 packed integer data from an MMX register to memory, using a non-temporal hint.
  82 The MOVNTPS (store packed single-precision floating-point values using
  83 non-temporal hint) instruction stores packed floating-point data from an
  84 XMM register to memory, using a non-temporal hint.
  85
  86 The SFENCE (Store Fence) instruction controls write ordering by creating a
  87 fence for memory store operations. This instruction guarantees that the results
  88 of every store instruction that precedes the store fence in program order is
  89 globally visible before any store instruction that follows the fence. The
  90 SFENCE instruction provides an efficient way of ensuring ordering between
  91 procedures that produce weakly-ordered data and procedures that consume that
  92 data.
  93
  94 If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru.
  95 */
  96
  97 /* 3dnow memcpy support from kernel 2.4.2 */
  98 /*  by Pontscho/fresh!mindworkz           */
  99
 100 #if defined( HAVE_MMX2 ) || defined( HAVE_3DNOW ) || defined( HAVE_MMX )
 101
 102 #undef HAVE_MMX1
 103 #if defined(HAVE_MMX) && !defined(HAVE_MMX2) && !defined(HAVE_3DNOW) && !defined(HAVE_SSE)
 104 /*  means: mmx v.1. Note: Since we added alignment of destinition it speedups
 105     of memory copying on PentMMX, Celeron-1 and P2 upto 12% versus
 106     standard (non MMX-optimized) version.
 107     Note: on K6-2+ it speedups memory copying upto 25% and
 108           on K7 and P3 about 500% (5 times). */
 109 #define HAVE_MMX1
 110 #endif
 111
 112
 113 #undef HAVE_K6_2PLUS
 114 #if !defined( HAVE_MMX2) && defined( HAVE_3DNOW)
 115 #define HAVE_K6_2PLUS
 116 #endif
 117
 118 /* for small memory blocks (<256 bytes) this version is faster */
 119 #define small_memcpy(to,from,n)\
 120 {\
 121 register unsigned long int dummy;\
 122 __asm__ __volatile__(\
 123         "rep; movsb"\
 124         :"=&D"(to), "=&S"(from), "=&c"(dummy)\
 125 /* It's most portable way to notify compiler */\
 126 /* that edi, esi and ecx are clobbered in asm block. */\
 127 /* Thanks to A'rpi for hint!!! */\
 128         :"0" (to), "1" (from),"2" (n)\
 129         : "memory");\
 130 }
 131
 132 #ifdef HAVE_SSE
 133 #define MMREG_SIZE 16
 134 #else
 135 #define MMREG_SIZE 64 /*8*/
 136 #endif
 137
 138 /* Small defines (for readability only) ;) */
 139 #ifdef HAVE_K6_2PLUS
 140 #define PREFETCH "prefetch"
 141 /* On K6 femms is faster of emms. On K7 femms is directly mapped on emms. */
 142 #define EMMS     "femms"
 143 #else
 144 #define PREFETCH "prefetchnta"
 145 #define EMMS     "emms"
 146 #endif
 147
 148 #ifdef HAVE_MMX2
 149 #define MOVNTQ "movntq"
 150 #else
 151 #define MOVNTQ "movq"
 152 #endif
 153
 154 #ifdef HAVE_MMX1
 155 #define MIN_LEN 0x800  /* 2K blocks */
 156 #else
 157 #define MIN_LEN 0x40  /* 64-byte blocks */
 158 #endif
 159
 160 void * fast_memcpy(void * to, const void * from, size_t len)
 161 {
 162         void *retval;
 163         size_t i;
 164         retval = to;
 165 #ifdef STATISTICS
 166         {
 167                 static int freq[33];
 168                 static int t=0;
 169                 int i;
 170                 for(i=0; len>(1<<i); i++);
 171                 freq[i]++;
 172                 t++;
 173                 if(1024*1024*1024 % t == 0)
 174                         for(i=0; i<32; i++)
 175                                 printf("freq < %8d %4d\n", 1<<i, freq[i]);
 176         }
 177 #endif
 178 #ifndef HAVE_MMX1
 179         /* PREFETCH has effect even for MOVSB instruction ;) */
 180         __asm__ __volatile__ (
 181                 PREFETCH" (%0)\n"
 182                 PREFETCH" 64(%0)\n"
 183                 PREFETCH" 128(%0)\n"
 184                 PREFETCH" 192(%0)\n"
 185                 PREFETCH" 256(%0)\n"
 186                 : : "r" (from) );
 187 #endif
 188         if(len >= MIN_LEN)
 189         {
 190           register unsigned long int delta;
 191           /* Align destinition to MMREG_SIZE -boundary */
 192           delta = ((unsigned long int)to)&(MMREG_SIZE-1);
 193           if(delta)
 194           {
 195             delta=MMREG_SIZE-delta;
 196             len -= delta;
 197             small_memcpy(to, from, delta);
 198           }
 199           i = len >> 6; /* len/64 */
 200           len&=63;
 201         /*
 202            This algorithm is top effective when the code consequently
 203            reads and writes blocks which have size of cache line.
 204            Size of cache line is processor-dependent.
 205            It will, however, be a minimum of 32 bytes on any processors.
 206            It would be better to have a number of instructions which
 207            perform reading and writing to be multiple to a number of
 208            processor's decoders, but it's not always possible.
 209         */
 210 #ifdef HAVE_SSE /* Only P3 (may be Cyrix3) */
 211         if(((unsigned long)from) & 15)
 212         /* if SRC is misaligned */
 213         for(; i>0; i--)
 214         {
 215                 __asm__ __volatile__ (
 216                 PREFETCH" 320(%0)\n"
 217                 "movups (%0), %%xmm0\n"
 218                 "movups 16(%0), %%xmm1\n"
 219                 "movups 32(%0), %%xmm2\n"
 220                 "movups 48(%0), %%xmm3\n"
 221                 "movntps %%xmm0, (%1)\n"
 222                 "movntps %%xmm1, 16(%1)\n"
 223                 "movntps %%xmm2, 32(%1)\n"
 224                 "movntps %%xmm3, 48(%1)\n"
 225                 :: "r" (from), "r" (to) : "memory");
 226                 ((const unsigned char *)from)+=64;
 227                 ((unsigned char *)to)+=64;
 228         }
 229         else
 230         /*
 231            Only if SRC is aligned on 16-byte boundary.
 232            It allows to use movaps instead of movups, which required data
 233            to be aligned or a general-protection exception (#GP) is generated.
 234         */
 235         for(; i>0; i--)
 236         {
 237                 __asm__ __volatile__ (
 238                 PREFETCH" 320(%0)\n"
 239                 "movaps (%0), %%xmm0\n"
 240                 "movaps 16(%0), %%xmm1\n"
 241                 "movaps 32(%0), %%xmm2\n"
 242                 "movaps 48(%0), %%xmm3\n"
 243                 "movntps %%xmm0, (%1)\n"
 244                 "movntps %%xmm1, 16(%1)\n"
 245                 "movntps %%xmm2, 32(%1)\n"
 246                 "movntps %%xmm3, 48(%1)\n"
 247                 :: "r" (from), "r" (to) : "memory");
 248                 ((const unsigned char *)from)+=64;
 249                 ((unsigned char *)to)+=64;
 250         }
 251 #else
 252         /* Align destination at BLOCK_SIZE boundary */
 253         for(; ((ptrdiff_t)to & (BLOCK_SIZE-1)) && i>0; i--)
 254         {
 255                 __asm__ __volatile__ (
 256 #ifndef HAVE_MMX1
 257                 PREFETCH" 320(%0)\n"
 258 #endif
 259                 "movq (%0), %%mm0\n"
 260                 "movq 8(%0), %%mm1\n"
 261                 "movq 16(%0), %%mm2\n"
 262                 "movq 24(%0), %%mm3\n"
 263                 "movq 32(%0), %%mm4\n"
 264                 "movq 40(%0), %%mm5\n"
 265                 "movq 48(%0), %%mm6\n"
 266                 "movq 56(%0), %%mm7\n"
 267                 MOVNTQ" %%mm0, (%1)\n"
 268                 MOVNTQ" %%mm1, 8(%1)\n"
 269                 MOVNTQ" %%mm2, 16(%1)\n"
 270                 MOVNTQ" %%mm3, 24(%1)\n"
 271                 MOVNTQ" %%mm4, 32(%1)\n"
 272                 MOVNTQ" %%mm5, 40(%1)\n"
 273                 MOVNTQ" %%mm6, 48(%1)\n"
 274                 MOVNTQ" %%mm7, 56(%1)\n"
 275                 :: "r" (from), "r" (to) : "memory");
 276                 from = (const void *) (((const unsigned char *)from)+64);
 277                 to = (void *) (((unsigned char *)to)+64);
 278         }
 279
 280 /*      printf(" %p %p\n", (ptrdiff_t)from&1023, (ptrdiff_t)to&1023); */
 281         /* Pure Assembly cuz gcc is a bit unpredictable ;) */
 282 # if 0
 283         if(i>=BLOCK_SIZE/64)
 284                 asm volatile(
 285                         "xorl %%eax, %%eax      \n\t"
 286                         ".balign 16             \n\t"
 287                         "1:                     \n\t"
 288                                 "movl (%0, %%eax), %%ebx        \n\t"
 289                                 "movl 32(%0, %%eax), %%ebx      \n\t"
 290                                 "movl 64(%0, %%eax), %%ebx      \n\t"
 291                                 "movl 96(%0, %%eax), %%ebx      \n\t"
 292                                 "addl $128, %%eax               \n\t"
 293                                 "cmpl %3, %%eax                 \n\t"
 294                                 " jb 1b                         \n\t"
 295
 296                         "xorl %%eax, %%eax      \n\t"
 297
 298                                 ".balign 16             \n\t"
 299                                 "2:                     \n\t"
 300                                 "movq (%0, %%eax), %%mm0\n"
 301                                 "movq 8(%0, %%eax), %%mm1\n"
 302                                 "movq 16(%0, %%eax), %%mm2\n"
 303                                 "movq 24(%0, %%eax), %%mm3\n"
 304                                 "movq 32(%0, %%eax), %%mm4\n"
 305                                 "movq 40(%0, %%eax), %%mm5\n"
 306                                 "movq 48(%0, %%eax), %%mm6\n"
 307                                 "movq 56(%0, %%eax), %%mm7\n"
 308                                 MOVNTQ" %%mm0, (%1, %%eax)\n"
 309                                 MOVNTQ" %%mm1, 8(%1, %%eax)\n"
 310                                 MOVNTQ" %%mm2, 16(%1, %%eax)\n"
 311                                 MOVNTQ" %%mm3, 24(%1, %%eax)\n"
 312                                 MOVNTQ" %%mm4, 32(%1, %%eax)\n"
 313                                 MOVNTQ" %%mm5, 40(%1, %%eax)\n"
 314                                 MOVNTQ" %%mm6, 48(%1, %%eax)\n"
 315                                 MOVNTQ" %%mm7, 56(%1, %%eax)\n"
 316                                 "addl $64, %%eax                \n\t"
 317                                 "cmpl %3, %%eax         \n\t"
 318                                 "jb 2b                          \n\t"
 319
 320 #if CONFUSION_FACTOR > 0
 321         /* a few percent speedup on out of order executing CPUs */
 322                         "movl %5, %%eax         \n\t"
 323                                 "2:                     \n\t"
 324                                 "movl (%0), %%ebx       \n\t"
 325                                 "movl (%0), %%ebx       \n\t"
 326                                 "movl (%0), %%ebx       \n\t"
 327                                 "movl (%0), %%ebx       \n\t"
 328                                 "decl %%eax             \n\t"
 329                                 " jnz 2b                \n\t"
 330 #endif
 331
 332                         "xorl %%eax, %%eax      \n\t"
 333                         "addl %3, %0            \n\t"
 334                         "addl %3, %1            \n\t"
 335                         "subl %4, %2            \n\t"
 336                         "cmpl %4, %2            \n\t"
 337                         " jae 1b                \n\t"
 338                                 : "+r" (from), "+r" (to), "+r" (i)
 339                                 : "r" (BLOCK_SIZE), "i" (BLOCK_SIZE/64), "i" (CONFUSION_FACTOR)
 340                                 : "%eax", "%ebx"
 341                 );
 342 #endif
 343
 344         for(; i>0; i--)
 345         {
 346                 __asm__ __volatile__ (
 347 #ifndef HAVE_MMX1
 348                 PREFETCH" 320(%0)\n"
 349 #endif
 350                 "movq (%0), %%mm0\n"
 351                 "movq 8(%0), %%mm1\n"
 352                 "movq 16(%0), %%mm2\n"
 353                 "movq 24(%0), %%mm3\n"
 354                 "movq 32(%0), %%mm4\n"
 355                 "movq 40(%0), %%mm5\n"
 356                 "movq 48(%0), %%mm6\n"
 357                 "movq 56(%0), %%mm7\n"
 358                 MOVNTQ" %%mm0, (%1)\n"
 359                 MOVNTQ" %%mm1, 8(%1)\n"
 360                 MOVNTQ" %%mm2, 16(%1)\n"
 361                 MOVNTQ" %%mm3, 24(%1)\n"
 362                 MOVNTQ" %%mm4, 32(%1)\n"
 363                 MOVNTQ" %%mm5, 40(%1)\n"
 364                 MOVNTQ" %%mm6, 48(%1)\n"
 365                 MOVNTQ" %%mm7, 56(%1)\n"
 366                 :: "r" (from), "r" (to) : "memory");
 367                 from = (const void *) (((const unsigned char *)from)+64);
 368                 to = (void *) (((unsigned char *)to)+64);
 369         }
 370
 371 #endif /* Have SSE */
 372 #ifdef HAVE_MMX2
 373                 /* since movntq is weakly-ordered, a "sfence"
 374                  * is needed to become ordered again. */
 375                 __asm__ __volatile__ ("sfence":::"memory");
 376 #endif
 377 #ifndef HAVE_SSE
 378                 /* enables to use FPU */
 379                 __asm__ __volatile__ (EMMS:::"memory");
 380 #endif
 381         }
 382         /*
 383          *      Now do the tail of the block
 384          */
 385         if(len) small_memcpy(to, from, len);
 386         return retval;
 387 }
 388
 389
 390 #endif /* #if defined( HAVE_MMX2 ) || defined( HAVE_3DNOW ) || defined( HAVE_MMX ) */
 391
 392 #endif