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Corrected a long-standing error in which ending text with a literal
[xcircuit.git]
/
examples
/
logic.sim
blob
495377d7f5bd3acb05080896066afbc92a06928f
1
| sim circuit "logic" from XCircuit v3.30
2
p Pin.1 Vdd int6
3
n Pin.1 GND int6
4
p int6 Vdd Pin.4
5
n int6 nand_1/ext13 Pin.4
6
n Pin.2 GND nand_1/ext13
7
p Pin.2 Vdd Pin.4
8
p Pin.2 Vdd Pin.5
9
n Pin.2 nand_2/ext13 Pin.5
10
n Pin.3 GND nand_2/ext13
11
p Pin.3 Vdd Pin.5