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SiS_DDC2Delay: initialize variable before adding to it
[xf86-video-sis.git] / src / init.c
blob79c7f66638f84bda9f47faecfc48e14738699865
1 /*
2 * Mode initializing code (CRT1 section) for
3 * for SiS 300/305/540/630/730,
4 * SiS 315/550/[M]650/651/[M]661[FGM]X/[M]74x[GX]/330/[M]76x[GX],
5 * XGI Volari V3XT/V5/V8, Z7
6 * (Universal module for Linux kernel framebuffer and X.org/XFree86 4.x)
7 *
8 * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
9 *
10 * If distributed as part of the Linux kernel, the following license terms
11 * apply:
12 *
13 * * This program is free software; you can redistribute it and/or modify
14 * * it under the terms of the GNU General Public License as published by
15 * * the Free Software Foundation; either version 2 of the named License,
16 * * or any later version.
17 * *
18 * * This program is distributed in the hope that it will be useful,
19 * * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * * GNU General Public License for more details.
22 * *
23 * * You should have received a copy of the GNU General Public License
24 * * along with this program; if not, write to the Free Software
25 * * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
26 *
27 * Otherwise, the following license terms apply:
28 *
29 * * Redistribution and use in source and binary forms, with or without
30 * * modification, are permitted provided that the following conditions
31 * * are met:
32 * * 1) Redistributions of source code must retain the above copyright
33 * * notice, this list of conditions and the following disclaimer.
34 * * 2) Redistributions in binary form must reproduce the above copyright
35 * * notice, this list of conditions and the following disclaimer in the
36 * * documentation and/or other materials provided with the distribution.
37 * * 3) The name of the author may not be used to endorse or promote products
38 * * derived from this software without specific prior written permission.
39 * *
40 * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
41 * * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
42 * * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
43 * * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
44 * * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
45 * * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
46 * * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
47 * * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
48 * * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
49 * * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
50 *
51 * Author: Thomas Winischhofer <thomas@winischhofer.net>
52 *
53 * Formerly based on non-functional code-fragements for 300 series by SiS, Inc.
54 * Used by permission.
55 */
56
57 #ifdef HAVE_CONFIG_H
58 #include "config.h"
59 #endif
60
61 #include "init.h"
62 #include "sis_dac.h"
63 #include "300vtbl.h"
64 #include "310vtbl.h"
65
66 #if defined(ALLOC_PRAGMA)
67 #pragma alloc_text(PAGE,SiSSetMode)
68 #endif
69
70 /*********************************************/
71 /* POINTER INITIALIZATION */
72 /*********************************************/
73
74 static void
75 InitCommonPointer(struct SiS_Private *SiS_Pr)
76 {
77 SiS_Pr->SiS_SModeIDTable = SiS_SModeIDTable;
78 SiS_Pr->SiS_StResInfo = SiS_StResInfo;
79 SiS_Pr->SiS_ModeResInfo = SiS_ModeResInfo;
80 SiS_Pr->SiS_StandTable = SiS_StandTable;
81
82 SiS_Pr->SiS_NTSCTiming = SiS_NTSCTiming;
83 SiS_Pr->SiS_PALTiming = SiS_PALTiming;
84 SiS_Pr->SiS_HiTVSt1Timing = SiS_HiTVSt1Timing;
85 SiS_Pr->SiS_HiTVSt2Timing = SiS_HiTVSt2Timing;
86
87 SiS_Pr->SiS_HiTVExtTiming = SiS_HiTVExtTiming;
88 SiS_Pr->SiS_HiTVGroup3Data = SiS_HiTVGroup3Data;
89 SiS_Pr->SiS_HiTVGroup3Simu = SiS_HiTVGroup3Simu;
90 #if 0
91 SiS_Pr->SiS_HiTVTextTiming = SiS_HiTVTextTiming;
92 SiS_Pr->SiS_HiTVGroup3Text = SiS_HiTVGroup3Text;
93 #endif
94
95 SiS_Pr->SiS_StPALData = SiS_StPALData;
96 SiS_Pr->SiS_ExtPALData = SiS_ExtPALData;
97 SiS_Pr->SiS_StNTSCData = SiS_StNTSCData;
98 SiS_Pr->SiS_ExtNTSCData = SiS_ExtNTSCData;
99 SiS_Pr->SiS_St1HiTVData = SiS_StHiTVData;
100 SiS_Pr->SiS_St2HiTVData = SiS_St2HiTVData;
101 SiS_Pr->SiS_ExtHiTVData = SiS_ExtHiTVData;
102 SiS_Pr->SiS_St525iData = SiS_StNTSCData;
103 SiS_Pr->SiS_St525pData = SiS_St525pData;
104 SiS_Pr->SiS_St625iData = SiS_StPALData;
105 SiS_Pr->SiS_St625pData = SiS_StPALData;
106 SiS_Pr->SiS_St750pData = SiS_St750pData;
107 SiS_Pr->SiS_Ext525iData = SiS_ExtNTSCData;
108 SiS_Pr->SiS_Ext525pData = SiS_ExtNTSCData;
109 SiS_Pr->SiS_Ext625iData = SiS_ExtPALData;
110 SiS_Pr->SiS_Ext625pData = SiS_ExtPALData;
111 SiS_Pr->SiS_Ext750pData = SiS_Ext750pData;
112
113 SiS_Pr->pSiS_OutputSelect = &SiS_OutputSelect;
114 SiS_Pr->pSiS_SoftSetting = &SiS_SoftSetting;
115
116 SiS_Pr->SiS_LCD1280x720Data = SiS_LCD1280x720Data;
117 SiS_Pr->SiS_StLCD1280x768_2Data = SiS_StLCD1280x768_2Data;
118 SiS_Pr->SiS_ExtLCD1280x768_2Data = SiS_ExtLCD1280x768_2Data;
119 SiS_Pr->SiS_LCD1280x800Data = SiS_LCD1280x800Data;
120 SiS_Pr->SiS_LCD1280x800_2Data = SiS_LCD1280x800_2Data;
121 SiS_Pr->SiS_LCD1280x854Data = SiS_LCD1280x854Data;
122 SiS_Pr->SiS_LCD1280x960Data = SiS_LCD1280x960Data;
123 SiS_Pr->SiS_StLCD1400x1050Data = SiS_StLCD1400x1050Data;
124 SiS_Pr->SiS_ExtLCD1400x1050Data = SiS_ExtLCD1400x1050Data;
125 SiS_Pr->SiS_LCD1680x1050Data = SiS_LCD1680x1050Data;
126 SiS_Pr->SiS_StLCD1600x1200Data = SiS_StLCD1600x1200Data;
127 SiS_Pr->SiS_ExtLCD1600x1200Data = SiS_ExtLCD1600x1200Data;
128 SiS_Pr->SiS_NoScaleData = SiS_NoScaleData;
129
130 SiS_Pr->SiS_LVDS320x240Data_1 = SiS_LVDS320x240Data_1;
131 SiS_Pr->SiS_LVDS320x240Data_2 = SiS_LVDS320x240Data_2;
132 SiS_Pr->SiS_LVDS640x480Data_1 = SiS_LVDS640x480Data_1;
133 SiS_Pr->SiS_LVDS800x600Data_1 = SiS_LVDS800x600Data_1;
134 SiS_Pr->SiS_LVDS1024x600Data_1 = SiS_LVDS1024x600Data_1;
135 SiS_Pr->SiS_LVDS1024x768Data_1 = SiS_LVDS1024x768Data_1;
136
137 SiS_Pr->SiS_LVDSCRT1320x240_1 = SiS_LVDSCRT1320x240_1;
138 SiS_Pr->SiS_LVDSCRT1320x240_2 = SiS_LVDSCRT1320x240_2;
139 SiS_Pr->SiS_LVDSCRT1320x240_2_H = SiS_LVDSCRT1320x240_2_H;
140 SiS_Pr->SiS_LVDSCRT1320x240_3 = SiS_LVDSCRT1320x240_3;
141 SiS_Pr->SiS_LVDSCRT1320x240_3_H = SiS_LVDSCRT1320x240_3_H;
142 SiS_Pr->SiS_LVDSCRT1640x480_1 = SiS_LVDSCRT1640x480_1;
143 SiS_Pr->SiS_LVDSCRT1640x480_1_H = SiS_LVDSCRT1640x480_1_H;
144 #if 0
145 SiS_Pr->SiS_LVDSCRT11024x600_1 = SiS_LVDSCRT11024x600_1;
146 SiS_Pr->SiS_LVDSCRT11024x600_1_H = SiS_LVDSCRT11024x600_1_H;
147 SiS_Pr->SiS_LVDSCRT11024x600_2 = SiS_LVDSCRT11024x600_2;
148 SiS_Pr->SiS_LVDSCRT11024x600_2_H = SiS_LVDSCRT11024x600_2_H;
149 #endif
150
151 SiS_Pr->SiS_CHTVUNTSCData = SiS_CHTVUNTSCData;
152 SiS_Pr->SiS_CHTVONTSCData = SiS_CHTVONTSCData;
153
154 SiS_Pr->SiS_PanelMinLVDS = Panel_800x600; /* lowest value LVDS/LCDA */
155 SiS_Pr->SiS_PanelMin301 = Panel_1024x768; /* lowest value 301 */
156 }
157
158 static void
159 InitTo300Pointer(struct SiS_Private *SiS_Pr)
160 {
161 InitCommonPointer(SiS_Pr);
162
163 SiS_Pr->SiS_VBModeIDTable = SiS300_VBModeIDTable;
164 SiS_Pr->SiS_EModeIDTable = SiS300_EModeIDTable;
165 SiS_Pr->SiS_RefIndex = SiS300_RefIndex;
166 SiS_Pr->SiS_CRT1Table = SiS300_CRT1Table;
167 if(SiS_Pr->ChipType == SIS_300) {
168 SiS_Pr->SiS_MCLKData_0 = SiS300_MCLKData_300; /* 300 */
169 } else {
170 SiS_Pr->SiS_MCLKData_0 = SiS300_MCLKData_630; /* 630, 730 */
171 }
172 SiS_Pr->SiS_VCLKData = SiS300_VCLKData;
173 SiS_Pr->SiS_VBVCLKData = (struct SiS_VBVCLKData *)SiS300_VCLKData;
174
175 SiS_Pr->SiS_SR15 = SiS300_SR15;
176
177 SiS_Pr->SiS_PanelDelayTbl = SiS300_PanelDelayTbl;
178 SiS_Pr->SiS_PanelDelayTblLVDS = SiS300_PanelDelayTbl;
179
180 SiS_Pr->SiS_ExtLCD1024x768Data = SiS300_ExtLCD1024x768Data;
181 SiS_Pr->SiS_St2LCD1024x768Data = SiS300_St2LCD1024x768Data;
182 SiS_Pr->SiS_ExtLCD1280x1024Data = SiS300_ExtLCD1280x1024Data;
183 SiS_Pr->SiS_St2LCD1280x1024Data = SiS300_St2LCD1280x1024Data;
184
185 SiS_Pr->SiS_CRT2Part2_1024x768_1 = SiS300_CRT2Part2_1024x768_1;
186 SiS_Pr->SiS_CRT2Part2_1024x768_2 = SiS300_CRT2Part2_1024x768_2;
187 SiS_Pr->SiS_CRT2Part2_1024x768_3 = SiS300_CRT2Part2_1024x768_3;
188
189 SiS_Pr->SiS_CHTVUPALData = SiS300_CHTVUPALData;
190 SiS_Pr->SiS_CHTVOPALData = SiS300_CHTVOPALData;
191 SiS_Pr->SiS_CHTVUPALMData = SiS_CHTVUNTSCData; /* not supported on 300 series */
192 SiS_Pr->SiS_CHTVOPALMData = SiS_CHTVONTSCData; /* not supported on 300 series */
193 SiS_Pr->SiS_CHTVUPALNData = SiS300_CHTVUPALData; /* not supported on 300 series */
194 SiS_Pr->SiS_CHTVOPALNData = SiS300_CHTVOPALData; /* not supported on 300 series */
195 SiS_Pr->SiS_CHTVSOPALData = SiS300_CHTVSOPALData;
196
197 SiS_Pr->SiS_LVDS848x480Data_1 = SiS300_LVDS848x480Data_1;
198 SiS_Pr->SiS_LVDS848x480Data_2 = SiS300_LVDS848x480Data_2;
199 SiS_Pr->SiS_LVDSBARCO1024Data_1 = SiS300_LVDSBARCO1024Data_1;
200 SiS_Pr->SiS_LVDSBARCO1366Data_1 = SiS300_LVDSBARCO1366Data_1;
201 SiS_Pr->SiS_LVDSBARCO1366Data_2 = SiS300_LVDSBARCO1366Data_2;
202
203 SiS_Pr->SiS_PanelType04_1a = SiS300_PanelType04_1a;
204 SiS_Pr->SiS_PanelType04_2a = SiS300_PanelType04_2a;
205 SiS_Pr->SiS_PanelType04_1b = SiS300_PanelType04_1b;
206 SiS_Pr->SiS_PanelType04_2b = SiS300_PanelType04_2b;
207
208 SiS_Pr->SiS_CHTVCRT1UNTSC = SiS300_CHTVCRT1UNTSC;
209 SiS_Pr->SiS_CHTVCRT1ONTSC = SiS300_CHTVCRT1ONTSC;
210 SiS_Pr->SiS_CHTVCRT1UPAL = SiS300_CHTVCRT1UPAL;
211 SiS_Pr->SiS_CHTVCRT1OPAL = SiS300_CHTVCRT1OPAL;
212 SiS_Pr->SiS_CHTVCRT1SOPAL = SiS300_CHTVCRT1SOPAL;
213 SiS_Pr->SiS_CHTVReg_UNTSC = SiS300_CHTVReg_UNTSC;
214 SiS_Pr->SiS_CHTVReg_ONTSC = SiS300_CHTVReg_ONTSC;
215 SiS_Pr->SiS_CHTVReg_UPAL = SiS300_CHTVReg_UPAL;
216 SiS_Pr->SiS_CHTVReg_OPAL = SiS300_CHTVReg_OPAL;
217 SiS_Pr->SiS_CHTVReg_UPALM = SiS300_CHTVReg_UNTSC; /* not supported on 300 series */
218 SiS_Pr->SiS_CHTVReg_OPALM = SiS300_CHTVReg_ONTSC; /* not supported on 300 series */
219 SiS_Pr->SiS_CHTVReg_UPALN = SiS300_CHTVReg_UPAL; /* not supported on 300 series */
220 SiS_Pr->SiS_CHTVReg_OPALN = SiS300_CHTVReg_OPAL; /* not supported on 300 series */
221 SiS_Pr->SiS_CHTVReg_SOPAL = SiS300_CHTVReg_SOPAL;
222 SiS_Pr->SiS_CHTVVCLKUNTSC = SiS300_CHTVVCLKUNTSC;
223 SiS_Pr->SiS_CHTVVCLKONTSC = SiS300_CHTVVCLKONTSC;
224 SiS_Pr->SiS_CHTVVCLKUPAL = SiS300_CHTVVCLKUPAL;
225 SiS_Pr->SiS_CHTVVCLKOPAL = SiS300_CHTVVCLKOPAL;
226 SiS_Pr->SiS_CHTVVCLKUPALM = SiS300_CHTVVCLKUNTSC; /* not supported on 300 series */
227 SiS_Pr->SiS_CHTVVCLKOPALM = SiS300_CHTVVCLKONTSC; /* not supported on 300 series */
228 SiS_Pr->SiS_CHTVVCLKUPALN = SiS300_CHTVVCLKUPAL; /* not supported on 300 series */
229 SiS_Pr->SiS_CHTVVCLKOPALN = SiS300_CHTVVCLKOPAL; /* not supported on 300 series */
230 SiS_Pr->SiS_CHTVVCLKSOPAL = SiS300_CHTVVCLKSOPAL;
231 }
232
233 static void
234 InitTo310Pointer(struct SiS_Private *SiS_Pr)
235 {
236 InitCommonPointer(SiS_Pr);
237
238 SiS_Pr->SiS_EModeIDTable = SiS310_EModeIDTable;
239 SiS_Pr->SiS_RefIndex = SiS310_RefIndex;
240 SiS_Pr->SiS_CRT1Table = SiS310_CRT1Table;
241 if(SiS_Pr->ChipType >= SIS_340) {
242 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_340; /* 340 + XGI */
243 } else if(SiS_Pr->ChipType >= SIS_761) {
244 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_761; /* 761 - preliminary */
245 } else if(SiS_Pr->ChipType >= SIS_760) {
246 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_760; /* 760 */
247 } else if(SiS_Pr->ChipType >= SIS_661) {
248 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_660; /* 661/741 */
249 } else if(SiS_Pr->ChipType == SIS_330) {
250 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_330; /* 330 */
251 } else if(SiS_Pr->ChipType > SIS_315PRO) {
252 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_650; /* 550, 650, 740 */
253 } else {
254 SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_315; /* 315 */
255 }
256 if(SiS_Pr->ChipType >= SIS_340) {
257 SiS_Pr->SiS_MCLKData_1 = SiS310_MCLKData_1_340;
258 } else {
259 SiS_Pr->SiS_MCLKData_1 = SiS310_MCLKData_1;
260 }
261 SiS_Pr->SiS_VCLKData = SiS310_VCLKData;
262 SiS_Pr->SiS_VBVCLKData = SiS310_VBVCLKData;
263
264 SiS_Pr->SiS_SR15 = SiS310_SR15;
265
266 SiS_Pr->SiS_PanelDelayTbl = SiS310_PanelDelayTbl;
267 SiS_Pr->SiS_PanelDelayTblLVDS = SiS310_PanelDelayTblLVDS;
268
269 SiS_Pr->SiS_St2LCD1024x768Data = SiS310_St2LCD1024x768Data;
270 SiS_Pr->SiS_ExtLCD1024x768Data = SiS310_ExtLCD1024x768Data;
271 SiS_Pr->SiS_St2LCD1280x1024Data = SiS310_St2LCD1280x1024Data;
272 SiS_Pr->SiS_ExtLCD1280x1024Data = SiS310_ExtLCD1280x1024Data;
273
274 SiS_Pr->SiS_CRT2Part2_1024x768_1 = SiS310_CRT2Part2_1024x768_1;
275
276 SiS_Pr->SiS_CHTVUPALData = SiS310_CHTVUPALData;
277 SiS_Pr->SiS_CHTVOPALData = SiS310_CHTVOPALData;
278 SiS_Pr->SiS_CHTVUPALMData = SiS310_CHTVUPALMData;
279 SiS_Pr->SiS_CHTVOPALMData = SiS310_CHTVOPALMData;
280 SiS_Pr->SiS_CHTVUPALNData = SiS310_CHTVUPALNData;
281 SiS_Pr->SiS_CHTVOPALNData = SiS310_CHTVOPALNData;
282 SiS_Pr->SiS_CHTVSOPALData = SiS310_CHTVSOPALData;
283
284 SiS_Pr->SiS_CHTVCRT1UNTSC = SiS310_CHTVCRT1UNTSC;
285 SiS_Pr->SiS_CHTVCRT1ONTSC = SiS310_CHTVCRT1ONTSC;
286 SiS_Pr->SiS_CHTVCRT1UPAL = SiS310_CHTVCRT1UPAL;
287 SiS_Pr->SiS_CHTVCRT1OPAL = SiS310_CHTVCRT1OPAL;
288 SiS_Pr->SiS_CHTVCRT1SOPAL = SiS310_CHTVCRT1OPAL;
289
290 SiS_Pr->SiS_CHTVReg_UNTSC = SiS310_CHTVReg_UNTSC;
291 SiS_Pr->SiS_CHTVReg_ONTSC = SiS310_CHTVReg_ONTSC;
292 SiS_Pr->SiS_CHTVReg_UPAL = SiS310_CHTVReg_UPAL;
293 SiS_Pr->SiS_CHTVReg_OPAL = SiS310_CHTVReg_OPAL;
294 SiS_Pr->SiS_CHTVReg_UPALM = SiS310_CHTVReg_UPALM;
295 SiS_Pr->SiS_CHTVReg_OPALM = SiS310_CHTVReg_OPALM;
296 SiS_Pr->SiS_CHTVReg_UPALN = SiS310_CHTVReg_UPALN;
297 SiS_Pr->SiS_CHTVReg_OPALN = SiS310_CHTVReg_OPALN;
298 SiS_Pr->SiS_CHTVReg_SOPAL = SiS310_CHTVReg_OPAL;
299
300 SiS_Pr->SiS_CHTVVCLKUNTSC = SiS310_CHTVVCLKUNTSC;
301 SiS_Pr->SiS_CHTVVCLKONTSC = SiS310_CHTVVCLKONTSC;
302 SiS_Pr->SiS_CHTVVCLKUPAL = SiS310_CHTVVCLKUPAL;
303 SiS_Pr->SiS_CHTVVCLKOPAL = SiS310_CHTVVCLKOPAL;
304 SiS_Pr->SiS_CHTVVCLKUPALM = SiS310_CHTVVCLKUPALM;
305 SiS_Pr->SiS_CHTVVCLKOPALM = SiS310_CHTVVCLKOPALM;
306 SiS_Pr->SiS_CHTVVCLKUPALN = SiS310_CHTVVCLKUPALN;
307 SiS_Pr->SiS_CHTVVCLKOPALN = SiS310_CHTVVCLKOPALN;
308 SiS_Pr->SiS_CHTVVCLKSOPAL = SiS310_CHTVVCLKOPAL;
309 }
310
311 BOOLEAN
312 SiSInitPtr(struct SiS_Private *SiS_Pr)
313 {
314 if(SiS_Pr->ChipType < SIS_315H) {
315 InitTo300Pointer(SiS_Pr);
316 } else {
317 InitTo310Pointer(SiS_Pr);
318 }
319 return TRUE;
320 }
321
322 /*********************************************/
323 /* HELPER: Get ModeID */
324 /*********************************************/
325
326 unsigned short
327 SiS_GetModeID(int VGAEngine, unsigned int VBFlags, int HDisplay, int VDisplay,
328 int Depth, BOOLEAN FSTN, int LCDwidth, int LCDheight)
329 {
330 unsigned short ModeIndex = 0;
331
332 switch(HDisplay)
333 {
334 case 320:
335 if(VDisplay == 200) ModeIndex = ModeIndex_320x200[Depth];
336 else if(VDisplay == 240) {
337 if((VBFlags & CRT2_LCD) && (FSTN))
338 ModeIndex = ModeIndex_320x240_FSTN[Depth];
339 else
340 ModeIndex = ModeIndex_320x240[Depth];
341 }
342 break;
343 case 400:
344 if((!(VBFlags & CRT1_LCDA)) || ((LCDwidth >= 800) && (LCDheight >= 600))) {
345 if(VDisplay == 300) ModeIndex = ModeIndex_400x300[Depth];
346 }
347 break;
348 case 512:
349 if((!(VBFlags & CRT1_LCDA)) || ((LCDwidth >= 1024) && (LCDheight >= 768))) {
350 if(VDisplay == 384) ModeIndex = ModeIndex_512x384[Depth];
351 }
352 break;
353 case 640:
354 if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
355 else if(VDisplay == 400) ModeIndex = ModeIndex_640x400[Depth];
356 break;
357 case 720:
358 if(VDisplay == 480) ModeIndex = ModeIndex_720x480[Depth];
359 else if(VDisplay == 576) ModeIndex = ModeIndex_720x576[Depth];
360 break;
361 case 768:
362 if(VDisplay == 576) ModeIndex = ModeIndex_768x576[Depth];
363 break;
364 case 800:
365 if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
366 else if(VDisplay == 480) ModeIndex = ModeIndex_800x480[Depth];
367 break;
368 case 848:
369 if(VDisplay == 480) ModeIndex = ModeIndex_848x480[Depth];
370 break;
371 case 856:
372 if(VDisplay == 480) ModeIndex = ModeIndex_856x480[Depth];
373 break;
374 case 960:
375 if(VGAEngine == SIS_315_VGA) {
376 if(VDisplay == 540) ModeIndex = ModeIndex_960x540[Depth];
377 else if(VDisplay == 600) ModeIndex = ModeIndex_960x600[Depth];
378 }
379 break;
380 case 1024:
381 if(VDisplay == 576) ModeIndex = ModeIndex_1024x576[Depth];
382 else if(VDisplay == 768) ModeIndex = ModeIndex_1024x768[Depth];
383 else if(VGAEngine == SIS_300_VGA) {
384 if(VDisplay == 600) ModeIndex = ModeIndex_1024x600[Depth];
385 }
386 break;
387 case 1152:
388 if(VDisplay == 864) ModeIndex = ModeIndex_1152x864[Depth];
389 if(VGAEngine == SIS_300_VGA) {
390 if(VDisplay == 768) ModeIndex = ModeIndex_1152x768[Depth];
391 }
392 break;
393 case 1280:
394 switch(VDisplay) {
395 case 720:
396 ModeIndex = ModeIndex_1280x720[Depth];
397 break;
398 case 768:
399 if(VGAEngine == SIS_300_VGA) {
400 ModeIndex = ModeIndex_300_1280x768[Depth];
401 } else {
402 ModeIndex = ModeIndex_310_1280x768[Depth];
403 }
404 break;
405 case 800:
406 if(VGAEngine == SIS_315_VGA) {
407 ModeIndex = ModeIndex_1280x800[Depth];
408 }
409 break;
410 case 854:
411 if(VGAEngine == SIS_315_VGA) {
412 ModeIndex = ModeIndex_1280x854[Depth];
413 }
414 break;
415 case 960:
416 ModeIndex = ModeIndex_1280x960[Depth];
417 break;
418 case 1024:
419 ModeIndex = ModeIndex_1280x1024[Depth];
420 break;
421 }
422 break;
423 case 1360:
424 if(VDisplay == 768) ModeIndex = ModeIndex_1360x768[Depth];
425 if(VGAEngine == SIS_300_VGA) {
426 if(VDisplay == 1024) ModeIndex = ModeIndex_300_1360x1024[Depth];
427 }
428 break;
429 case 1400:
430 if(VGAEngine == SIS_315_VGA) {
431 if(VDisplay == 1050) {
432 ModeIndex = ModeIndex_1400x1050[Depth];
433 }
434 }
435 break;
436 case 1600:
437 if(VDisplay == 1200) ModeIndex = ModeIndex_1600x1200[Depth];
438 break;
439 case 1680:
440 if(VGAEngine == SIS_315_VGA) {
441 if(VDisplay == 1050) ModeIndex = ModeIndex_1680x1050[Depth];
442 }
443 break;
444 case 1920:
445 if(VDisplay == 1440) ModeIndex = ModeIndex_1920x1440[Depth];
446 else if(VGAEngine == SIS_315_VGA) {
447 if(VDisplay == 1080) ModeIndex = ModeIndex_1920x1080[Depth];
448 }
449 break;
450 case 2048:
451 if(VDisplay == 1536) {
452 if(VGAEngine == SIS_300_VGA) {
453 ModeIndex = ModeIndex_300_2048x1536[Depth];
454 } else {
455 ModeIndex = ModeIndex_310_2048x1536[Depth];
456 }
457 }
458 break;
459 }
460
461 return ModeIndex;
462 }
463
464 unsigned short
465 SiS_GetModeID_LCD(int VGAEngine, unsigned int VBFlags, int HDisplay, int VDisplay,
466 int Depth, BOOLEAN FSTN, unsigned short CustomT, int LCDwidth, int LCDheight,
467 unsigned int VBFlags2)
468 {
469 unsigned short ModeIndex = 0;
470
471 if(VBFlags2 & (VB2_LVDS | VB2_30xBDH)) {
472
473 switch(HDisplay)
474 {
475 case 320:
476 if((CustomT != CUT_PANEL848) && (CustomT != CUT_PANEL856)) {
477 if(VDisplay == 200) {
478 if(!FSTN) ModeIndex = ModeIndex_320x200[Depth];
479 } else if(VDisplay == 240) {
480 if(!FSTN) ModeIndex = ModeIndex_320x240[Depth];
481 else if(VGAEngine == SIS_315_VGA) {
482 ModeIndex = ModeIndex_320x240_FSTN[Depth];
483 }
484 }
485 }
486 break;
487 case 400:
488 if((CustomT != CUT_PANEL848) && (CustomT != CUT_PANEL856)) {
489 if(!((VGAEngine == SIS_300_VGA) && (VBFlags2 & VB2_TRUMPION))) {
490 if(VDisplay == 300) ModeIndex = ModeIndex_400x300[Depth];
491 }
492 }
493 break;
494 case 512:
495 if((CustomT != CUT_PANEL848) && (CustomT != CUT_PANEL856)) {
496 if(!((VGAEngine == SIS_300_VGA) && (VBFlags2 & VB2_TRUMPION))) {
497 if(LCDwidth >= 1024 && LCDwidth != 1152 && LCDheight >= 768) {
498 if(VDisplay == 384) {
499 ModeIndex = ModeIndex_512x384[Depth];
500 }
501 }
502 }
503 }
504 break;
505 case 640:
506 if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
507 else if(VDisplay == 400) {
508 if((CustomT != CUT_PANEL848) && (CustomT != CUT_PANEL856))
509 ModeIndex = ModeIndex_640x400[Depth];
510 }
511 break;
512 case 800:
513 if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
514 break;
515 case 848:
516 if(CustomT == CUT_PANEL848) {
517 if(VDisplay == 480) ModeIndex = ModeIndex_848x480[Depth];
518 }
519 break;
520 case 856:
521 if(CustomT == CUT_PANEL856) {
522 if(VDisplay == 480) ModeIndex = ModeIndex_856x480[Depth];
523 }
524 break;
525 case 1024:
526 if(VDisplay == 768) ModeIndex = ModeIndex_1024x768[Depth];
527 else if(VGAEngine == SIS_300_VGA) {
528 if((VDisplay == 600) && (LCDheight == 600)) {
529 ModeIndex = ModeIndex_1024x600[Depth];
530 }
531 }
532 break;
533 case 1152:
534 if(VGAEngine == SIS_300_VGA) {
535 if((VDisplay == 768) && (LCDheight == 768)) {
536 ModeIndex = ModeIndex_1152x768[Depth];
537 }
538 }
539 break;
540 case 1280:
541 if(VDisplay == 1024) ModeIndex = ModeIndex_1280x1024[Depth];
542 else if(VGAEngine == SIS_315_VGA) {
543 if((VDisplay == 768) && (LCDheight == 768)) {
544 ModeIndex = ModeIndex_310_1280x768[Depth];
545 }
546 }
547 break;
548 case 1360:
549 if(VGAEngine == SIS_300_VGA) {
550 if(CustomT == CUT_BARCO1366) {
551 if(VDisplay == 1024) ModeIndex = ModeIndex_300_1360x1024[Depth];
552 }
553 }
554 if(CustomT == CUT_PANEL848) {
555 if(VDisplay == 768) ModeIndex = ModeIndex_1360x768[Depth];
556 }
557 break;
558 case 1400:
559 if(VGAEngine == SIS_315_VGA) {
560 if(VDisplay == 1050) ModeIndex = ModeIndex_1400x1050[Depth];
561 }
562 break;
563 case 1600:
564 if(VGAEngine == SIS_315_VGA) {
565 if(VDisplay == 1200) ModeIndex = ModeIndex_1600x1200[Depth];
566 }
567 break;
568 }
569
570 } else if(VBFlags2 & VB2_SISBRIDGE) {
571
572 switch(HDisplay)
573 {
574 case 320:
575 if(VDisplay == 200) ModeIndex = ModeIndex_320x200[Depth];
576 else if(VDisplay == 240) ModeIndex = ModeIndex_320x240[Depth];
577 break;
578 case 400:
579 if(LCDwidth >= 800 && LCDheight >= 600) {
580 if(VDisplay == 300) ModeIndex = ModeIndex_400x300[Depth];
581 }
582 break;
583 case 512:
584 if(LCDwidth >= 1024 && LCDheight >= 768 && LCDwidth != 1152) {
585 if(VDisplay == 384) ModeIndex = ModeIndex_512x384[Depth];
586 }
587 break;
588 case 640:
589 if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
590 else if(VDisplay == 400) ModeIndex = ModeIndex_640x400[Depth];
591 break;
592 case 720:
593 if(VGAEngine == SIS_315_VGA) {
594 if(VDisplay == 480) ModeIndex = ModeIndex_720x480[Depth];
595 else if(VDisplay == 576) ModeIndex = ModeIndex_720x576[Depth];
596 }
597 break;
598 case 768:
599 if(VGAEngine == SIS_315_VGA) {
600 if(VDisplay == 576) ModeIndex = ModeIndex_768x576[Depth];
601 }
602 break;
603 case 800:
604 if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
605 if(VGAEngine == SIS_315_VGA) {
606 if(VDisplay == 480) ModeIndex = ModeIndex_800x480[Depth];
607 }
608 break;
609 case 848:
610 if(VGAEngine == SIS_315_VGA) {
611 if(VDisplay == 480) ModeIndex = ModeIndex_848x480[Depth];
612 }
613 break;
614 case 856:
615 if(VGAEngine == SIS_315_VGA) {
616 if(VDisplay == 480) ModeIndex = ModeIndex_856x480[Depth];
617 }
618 break;
619 case 960:
620 if(VGAEngine == SIS_315_VGA) {
621 if(VDisplay == 540) ModeIndex = ModeIndex_960x540[Depth];
622 else if(VDisplay == 600) ModeIndex = ModeIndex_960x600[Depth];
623 }
624 break;
625 case 1024:
626 if(VDisplay == 768) ModeIndex = ModeIndex_1024x768[Depth];
627 if(VGAEngine == SIS_315_VGA) {
628 if(VDisplay == 576) ModeIndex = ModeIndex_1024x576[Depth];
629 }
630 break;
631 case 1152:
632 if(VGAEngine == SIS_315_VGA) {
633 if(VDisplay == 864) ModeIndex = ModeIndex_1152x864[Depth];
634 }
635 break;
636 case 1280:
637 switch(VDisplay) {
638 case 720:
639 ModeIndex = ModeIndex_1280x720[Depth];
640 break;
641 case 768:
642 if(VGAEngine == SIS_300_VGA) {
643 ModeIndex = ModeIndex_300_1280x768[Depth];
644 } else {
645 ModeIndex = ModeIndex_310_1280x768[Depth];
646 }
647 break;
648 case 800:
649 if(VGAEngine == SIS_315_VGA) {
650 ModeIndex = ModeIndex_1280x800[Depth];
651 }
652 break;
653 case 854:
654 if(VGAEngine == SIS_315_VGA) {
655 ModeIndex = ModeIndex_1280x854[Depth];
656 }
657 break;
658 case 960:
659 ModeIndex = ModeIndex_1280x960[Depth];
660 break;
661 case 1024:
662 ModeIndex = ModeIndex_1280x1024[Depth];
663 break;
664 }
665 break;
666 case 1360:
667 if(VGAEngine == SIS_315_VGA) { /* OVER1280 only? */
668 if(VDisplay == 768) ModeIndex = ModeIndex_1360x768[Depth];
669 }
670 break;
671 case 1400:
672 if(VGAEngine == SIS_315_VGA) {
673 if(VBFlags2 & VB2_LCDOVER1280BRIDGE) {
674 if(VDisplay == 1050) ModeIndex = ModeIndex_1400x1050[Depth];
675 }
676 }
677 break;
678 case 1600:
679 if(VGAEngine == SIS_315_VGA) {
680 if(VBFlags2 & VB2_LCDOVER1280BRIDGE) {
681 if(VDisplay == 1200) ModeIndex = ModeIndex_1600x1200[Depth];
682 }
683 }
684 break;
685 #ifndef VB_FORBID_CRT2LCD_OVER_1600
686 case 1680:
687 if(VGAEngine == SIS_315_VGA) {
688 if(VBFlags2 & VB2_LCDOVER1280BRIDGE) {
689 if(VDisplay == 1050) ModeIndex = ModeIndex_1680x1050[Depth];
690 }
691 }
692 break;
693 case 1920:
694 if(VGAEngine == SIS_315_VGA) {
695 if(VBFlags2 & VB2_LCDOVER1600BRIDGE) {
696 if(VDisplay == 1440) ModeIndex = ModeIndex_1920x1440[Depth];
697 }
698 }
699 break;
700 case 2048:
701 if(VGAEngine == SIS_315_VGA) {
702 if(VBFlags2 & VB2_LCDOVER1600BRIDGE) {
703 if(VDisplay == 1536) ModeIndex = ModeIndex_310_2048x1536[Depth];
704 }
705 }
706 break;
707 #endif
708 }
709 }
710
711 return ModeIndex;
712 }
713
714 unsigned short
715 SiS_GetModeID_TV(int VGAEngine, unsigned int VBFlags, int HDisplay, int VDisplay, int Depth,
716 unsigned int VBFlags2)
717 {
718 unsigned short ModeIndex = 0;
719
720 if(VBFlags2 & VB2_CHRONTEL) {
721
722 switch(HDisplay)
723 {
724 case 512:
725 if(VGAEngine == SIS_315_VGA) {
726 if(VDisplay == 384) ModeIndex = ModeIndex_512x384[Depth];
727 }
728 break;
729 case 640:
730 if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
731 else if(VDisplay == 400) ModeIndex = ModeIndex_640x400[Depth];
732 break;
733 case 800:
734 if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
735 break;
736 case 1024:
737 if(VGAEngine == SIS_315_VGA) {
738 if(VDisplay == 768) ModeIndex = ModeIndex_1024x768[Depth];
739 }
740 break;
741 }
742
743 } else if(VBFlags2 & VB2_SISTVBRIDGE) {
744
745 switch(HDisplay)
746 {
747 case 320:
748 if(VDisplay == 200) ModeIndex = ModeIndex_320x200[Depth];
749 else if(VDisplay == 240) ModeIndex = ModeIndex_320x240[Depth];
750 break;
751 case 400:
752 if(VDisplay == 300) ModeIndex = ModeIndex_400x300[Depth];
753 break;
754 case 512:
755 if(VBFlags2 & VB2_30xBLV) {
756 if( ((VBFlags & TV_YPBPR) && (!(VBFlags & (TV_YPBPR525P | TV_YPBPR525I)))) ||
757 (VBFlags & TV_HIVISION) ||
758 ((!(VBFlags & (TV_YPBPR | TV_PALM))) && (VBFlags & TV_PAL)) ) {
759 if(VDisplay == 384) ModeIndex = ModeIndex_512x384[Depth];
760 }
761 }
762 break;
763 case 640:
764 if(VDisplay == 480) ModeIndex = ModeIndex_640x480[Depth];
765 else if(VDisplay == 400) ModeIndex = ModeIndex_640x400[Depth];
766 break;
767 case 720:
768 if((!(VBFlags & TV_HIVISION)) && (!((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I)))) {
769 if(VDisplay == 480) {
770 ModeIndex = ModeIndex_720x480[Depth];
771 } else if(VDisplay == 576) {
772 ModeIndex = ModeIndex_720x576[Depth];
773 }
774 }
775 break;
776 case 768:
777 if((!(VBFlags & TV_HIVISION)) && (!((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I)))) {
778 if(VDisplay == 576) ModeIndex = ModeIndex_768x576[Depth];
779 }
780 break;
781 case 800:
782 if(VDisplay == 600) ModeIndex = ModeIndex_800x600[Depth];
783 else if(VDisplay == 480) ModeIndex = ModeIndex_800x480[Depth];
784 break;
785 case 960:
786 if(VGAEngine == SIS_315_VGA) {
787 if((VBFlags & TV_HIVISION) || ((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I))) {
788 if(VDisplay == 600) {
789 ModeIndex = ModeIndex_960x600[Depth];
790 } else if(VDisplay == 540) {
791 ModeIndex = ModeIndex_960x540[Depth];
792 }
793 }
794 }
795 break;
796 case 1024:
797 if((VBFlags2 & VB2_30xBLV) ||
798 (VBFlags & TV_HIVISION) ||
799 ((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I))) {
800 if(VDisplay == 768) {
801 ModeIndex = ModeIndex_1024x768[Depth];
802 } else if(VDisplay == 576) {
803 ModeIndex = ModeIndex_1024x576[Depth];
804 }
805 }
806 break;
807 case 1280:
808 if(VDisplay == 720) {
809 if((VBFlags & TV_HIVISION) ||
810 ((VBFlags & TV_YPBPR) && (VBFlags & (TV_YPBPR1080I | TV_YPBPR750P)))) {
811 ModeIndex = ModeIndex_1280x720[Depth];
812 }
813 } else if(VDisplay == 1024) {
814 if((VBFlags & TV_HIVISION) ||
815 ((VBFlags & TV_YPBPR) && (VBFlags & TV_YPBPR1080I))) {
816 ModeIndex = ModeIndex_1280x1024[Depth];
817 }
818 }
819 break;
820 }
821 }
822 return ModeIndex;
823 }
824
825 unsigned short
826 SiS_GetModeID_VGA2(int VGAEngine, unsigned int VBFlags, int HDisplay, int VDisplay, int Depth,
827 unsigned int VBFlags2)
828 {
829 if(!(VBFlags2 & VB2_SISVGA2BRIDGE)) return 0;
830
831 if(HDisplay >= 1920) return 0;
832
833 switch(HDisplay)
834 {
835 case 1600:
836 if(VDisplay == 1200) {
837 if(VGAEngine != SIS_315_VGA) return 0;
838 if(!(VBFlags2 & VB2_30xB)) return 0;
839 }
840 break;
841 case 1680:
842 if(VDisplay == 1050) {
843 if(VGAEngine != SIS_315_VGA) return 0;
844 if(!(VBFlags2 & VB2_30xB)) return 0;
845 }
846 break;
847 }
848
849 return SiS_GetModeID(VGAEngine, 0, HDisplay, VDisplay, Depth, FALSE, 0, 0);
850 }
851
852
853 /*********************************************/
854 /* HELPER: SetReg, GetReg */
855 /*********************************************/
856
857 void
858 SiS_SetReg(SISIOADDRESS port, unsigned short index, unsigned short data)
859 {
860 OutPortByte(port, index);
861 OutPortByte(port + 1, data);
862 }
863
864 void
865 SiS_SetRegByte(SISIOADDRESS port, unsigned short data)
866 {
867 OutPortByte(port, data);
868 }
869
870 void
871 SiS_SetRegShort(SISIOADDRESS port, unsigned short data)
872 {
873 OutPortWord(port, data);
874 }
875
876 void
877 SiS_SetRegLong(SISIOADDRESS port, unsigned int data)
878 {
879 OutPortLong(port, data);
880 }
881
882 unsigned char
883 SiS_GetReg(SISIOADDRESS port, unsigned short index)
884 {
885 OutPortByte(port, index);
886 return(InPortByte(port + 1));
887 }
888
889 unsigned char
890 SiS_GetRegByte(SISIOADDRESS port)
891 {
892 return(InPortByte(port));
893 }
894
895 unsigned short
896 SiS_GetRegShort(SISIOADDRESS port)
897 {
898 return(InPortWord(port));
899 }
900
901 unsigned int
902 SiS_GetRegLong(SISIOADDRESS port)
903 {
904 return(InPortLong(port));
905 }
906
907 void
908 SiS_SetRegANDOR(SISIOADDRESS Port, unsigned short Index, unsigned short DataAND, unsigned short DataOR)
909 {
910 unsigned short temp;
911
912 temp = SiS_GetReg(Port, Index);
913 temp = (temp & (DataAND)) | DataOR;
914 SiS_SetReg(Port, Index, temp);
915 }
916
917 void
918 SiS_SetRegAND(SISIOADDRESS Port, unsigned short Index, unsigned short DataAND)
919 {
920 unsigned short temp;
921
922 temp = SiS_GetReg(Port, Index);
923 temp &= DataAND;
924 SiS_SetReg(Port, Index, temp);
925 }
926
927 void
928 SiS_SetRegOR(SISIOADDRESS Port, unsigned short Index, unsigned short DataOR)
929 {
930 unsigned short temp;
931
932 temp = SiS_GetReg(Port, Index);
933 temp |= DataOR;
934 SiS_SetReg(Port, Index, temp);
935 }
936
937 /*********************************************/
938 /* HELPER: DisplayOn, DisplayOff */
939 /*********************************************/
940
941 void
942 SiS_DisplayOn(struct SiS_Private *SiS_Pr)
943 {
944 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x01,0xDF);
945 }
946
947 void
948 SiS_DisplayOff(struct SiS_Private *SiS_Pr)
949 {
950 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x01,0x20);
951 }
952
953
954 /*********************************************/
955 /* HELPER: Init Port Addresses */
956 /*********************************************/
957
958 void
959 SiSRegInit(struct SiS_Private *SiS_Pr, SISIOADDRESS BaseAddr)
960 {
961 SiS_Pr->SiS_P3c4 = BaseAddr + 0x14;
962 SiS_Pr->SiS_P3d4 = BaseAddr + 0x24;
963 SiS_Pr->SiS_P3c0 = BaseAddr + 0x10;
964 SiS_Pr->SiS_P3ce = BaseAddr + 0x1e;
965 SiS_Pr->SiS_P3c2 = BaseAddr + 0x12;
966 SiS_Pr->SiS_P3ca = BaseAddr + 0x1a;
967 SiS_Pr->SiS_P3c6 = BaseAddr + 0x16;
968 SiS_Pr->SiS_P3c7 = BaseAddr + 0x17;
969 SiS_Pr->SiS_P3c8 = BaseAddr + 0x18;
970 SiS_Pr->SiS_P3c9 = BaseAddr + 0x19;
971 SiS_Pr->SiS_P3cb = BaseAddr + 0x1b;
972 SiS_Pr->SiS_P3cc = BaseAddr + 0x1c;
973 SiS_Pr->SiS_P3cd = BaseAddr + 0x1d;
974 SiS_Pr->SiS_P3da = BaseAddr + 0x2a;
975 SiS_Pr->SiS_Part1Port = BaseAddr + SIS_CRT2_PORT_04;
976 SiS_Pr->SiS_Part2Port = BaseAddr + SIS_CRT2_PORT_10;
977 SiS_Pr->SiS_Part3Port = BaseAddr + SIS_CRT2_PORT_12;
978 SiS_Pr->SiS_Part4Port = BaseAddr + SIS_CRT2_PORT_14;
979 SiS_Pr->SiS_Part5Port = BaseAddr + SIS_CRT2_PORT_14 + 2;
980 SiS_Pr->SiS_DDC_Port = BaseAddr + 0x14;
981 SiS_Pr->SiS_VidCapt = BaseAddr + SIS_VIDEO_CAPTURE;
982 SiS_Pr->SiS_VidPlay = BaseAddr + SIS_VIDEO_PLAYBACK;
983 }
984
985 /*********************************************/
986 /* HELPER: GetSysFlags */
987 /*********************************************/
988
989 static void
990 SiS_GetSysFlags(struct SiS_Private *SiS_Pr)
991 {
992 unsigned char cr5f, temp1, temp2;
993
994 /* 661 and newer: NEVER write non-zero to SR11[7:4] */
995 /* (SR11 is used for DDC and in enable/disablebridge) */
996 SiS_Pr->SiS_SensibleSR11 = FALSE;
997 SiS_Pr->SiS_MyCR63 = 0x63;
998 if(SiS_Pr->ChipType >= SIS_330) {
999 SiS_Pr->SiS_MyCR63 = 0x53;
1000 if(SiS_Pr->ChipType >= SIS_661) {
1001 SiS_Pr->SiS_SensibleSR11 = TRUE;
1002 }
1003 }
1004
1005 /* You should use the macros, not these flags directly */
1006
1007 SiS_Pr->SiS_SysFlags = 0;
1008 if(SiS_Pr->ChipType == SIS_650) {
1009 cr5f = SiS_GetReg(SiS_Pr->SiS_P3d4,0x5f) & 0xf0;
1010 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x5c,0x07);
1011 temp1 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x5c) & 0xf8;
1012 SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x5c,0xf8);
1013 temp2 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x5c) & 0xf8;
1014 if((!temp1) || (temp2)) {
1015 switch(cr5f) {
1016 case 0x80:
1017 case 0x90:
1018 case 0xc0:
1019 SiS_Pr->SiS_SysFlags |= SF_IsM650;
1020 break;
1021 case 0xa0:
1022 case 0xb0:
1023 case 0xe0:
1024 SiS_Pr->SiS_SysFlags |= SF_Is651;
1025 break;
1026 }
1027 } else {
1028 switch(cr5f) {
1029 case 0x90:
1030 temp1 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x5c) & 0xf8;
1031 switch(temp1) {
1032 case 0x00: SiS_Pr->SiS_SysFlags |= SF_IsM652; break;
1033 case 0x40: SiS_Pr->SiS_SysFlags |= SF_IsM653; break;
1034 default: SiS_Pr->SiS_SysFlags |= SF_IsM650; break;
1035 }
1036 break;
1037 case 0xb0:
1038 SiS_Pr->SiS_SysFlags |= SF_Is652;
1039 break;
1040 default:
1041 SiS_Pr->SiS_SysFlags |= SF_IsM650;
1042 break;
1043 }
1044 }
1045 }
1046
1047 if(SiS_Pr->ChipType >= SIS_760 && SiS_Pr->ChipType <= SIS_761) {
1048 if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x78) & 0x30) {
1049 SiS_Pr->SiS_SysFlags |= SF_760LFB;
1050 }
1051 if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x79) & 0xf0) {
1052 SiS_Pr->SiS_SysFlags |= SF_760UMA;
1053 }
1054 }
1055 }
1056
1057 /*********************************************/
1058 /* HELPER: Init PCI & Engines */
1059 /*********************************************/
1060
1061 static void
1062 SiSInitPCIetc(struct SiS_Private *SiS_Pr)
1063 {
1064 switch(SiS_Pr->ChipType) {
1065 case SIS_300:
1066 case SIS_540:
1067 case SIS_630:
1068 case SIS_730:
1069 /* Set - PCI LINEAR ADDRESSING ENABLE (0x80)
1070 * - RELOCATED VGA IO ENABLED (0x20)
1071 * - MMIO ENABLED (0x01)
1072 * Leave other bits untouched.
1073 */
1074 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x20,0xa1);
1075 /* - Enable 2D (0x40)
1076 * - Enable 3D (0x02)
1077 * - Enable 3D Vertex command fetch (0x10) ?
1078 * - Enable 3D command parser (0x08) ?
1079 */
1080 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0x5A);
1081 break;
1082 case SIS_315H:
1083 case SIS_315:
1084 case SIS_315PRO:
1085 case SIS_650:
1086 case SIS_740:
1087 case SIS_330:
1088 case SIS_661:
1089 case SIS_741:
1090 case SIS_660:
1091 case SIS_760:
1092 case SIS_761:
1093 case SIS_340:
1094 case XGI_40:
1095 /* See above */
1096 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x20,0xa1);
1097 /* - Enable 3D G/L transformation engine (0x80)
1098 * - Enable 2D (0x40)
1099 * - Enable 3D vertex command fetch (0x10)
1100 * - Enable 3D command parser (0x08)
1101 * - Enable 3D (0x02)
1102 */
1103 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x1E,0xDA);
1104 break;
1105 case XGI_20:
1106 case SIS_550:
1107 /* See above */
1108 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x20,0xa1);
1109 /* No 3D engine ! */
1110 /* - Enable 2D (0x40)
1111 * - disable 3D
1112 */
1113 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x1E,0x60,0x40);
1114 break;
1115 default:
1116 break;
1117 }
1118 }
1119
1120 /*********************************************/
1121 /* HELPER: SetLVDSetc */
1122 /*********************************************/
1123
1124 void
1125 SiSSetLVDSetc(struct SiS_Private *SiS_Pr)
1126 {
1127 unsigned short temp;
1128
1129 SiS_Pr->SiS_IF_DEF_LVDS = 0;
1130 SiS_Pr->SiS_IF_DEF_TRUMPION = 0;
1131 SiS_Pr->SiS_IF_DEF_CH70xx = 0;
1132 SiS_Pr->SiS_IF_DEF_CONEX = 0;
1133
1134 SiS_Pr->SiS_ChrontelInit = 0;
1135
1136 if(SiS_Pr->ChipType == XGI_20) return;
1137
1138 /* Check for SiS30x first */
1139 temp = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x00);
1140 if((temp == 1) || (temp == 2)) return;
1141
1142 switch(SiS_Pr->ChipType) {
1143 case SIS_540:
1144 case SIS_630:
1145 case SIS_730:
1146 temp = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x37) & 0x0e) >> 1;
1147 if((temp >= 2) && (temp <= 5)) SiS_Pr->SiS_IF_DEF_LVDS = 1;
1148 if(temp == 3) SiS_Pr->SiS_IF_DEF_TRUMPION = 1;
1149 if((temp == 4) || (temp == 5)) {
1150 /* Save power status (and error check) - UNUSED */
1151 SiS_Pr->SiS_Backup70xx = SiS_GetCH700x(SiS_Pr, 0x0e);
1152 SiS_Pr->SiS_IF_DEF_CH70xx = 1;
1153 }
1154 break;
1155 case SIS_550:
1156 case SIS_650:
1157 case SIS_740:
1158 case SIS_330:
1159 temp = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x37) & 0x0e) >> 1;
1160 if((temp >= 2) && (temp <= 3)) SiS_Pr->SiS_IF_DEF_LVDS = 1;
1161 if(temp == 3) SiS_Pr->SiS_IF_DEF_CH70xx = 2;
1162 break;
1163 case SIS_661:
1164 case SIS_741:
1165 case SIS_660:
1166 case SIS_760:
1167 case SIS_761:
1168 case SIS_340:
1169 case XGI_20:
1170 case XGI_40:
1171 temp = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x38) & 0xe0) >> 5;
1172 if((temp >= 2) && (temp <= 3)) SiS_Pr->SiS_IF_DEF_LVDS = 1;
1173 if(temp == 3) SiS_Pr->SiS_IF_DEF_CH70xx = 2;
1174 if(temp == 4) SiS_Pr->SiS_IF_DEF_CONEX = 1; /* Not yet supported */
1175 break;
1176 default:
1177 break;
1178 }
1179 }
1180
1181 /*********************************************/
1182 /* HELPER: Enable DSTN/FSTN */
1183 /*********************************************/
1184
1185 void
1186 SiS_SetEnableDstn(struct SiS_Private *SiS_Pr, int enable)
1187 {
1188 SiS_Pr->SiS_IF_DEF_DSTN = enable ? 1 : 0;
1189 }
1190
1191 void
1192 SiS_SetEnableFstn(struct SiS_Private *SiS_Pr, int enable)
1193 {
1194 SiS_Pr->SiS_IF_DEF_FSTN = enable ? 1 : 0;
1195 }
1196
1197 /*********************************************/
1198 /* HELPER: Get modeflag */
1199 /*********************************************/
1200
1201 unsigned short
1202 SiS_GetModeFlag(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
1203 unsigned short ModeIdIndex)
1204 {
1205 if(SiS_Pr->UseCustomMode) {
1206 return SiS_Pr->CModeFlag;
1207 } else if(ModeNo <= 0x13) {
1208 return SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
1209 } else {
1210 return SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
1211 }
1212 }
1213
1214 /*********************************************/
1215 /* HELPER: Determine ROM usage */
1216 /*********************************************/
1217
1218 BOOLEAN
1219 SiSDetermineROMLayout661(struct SiS_Private *SiS_Pr)
1220 {
1221 unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
1222 unsigned short romversoffs, romvmaj = 1, romvmin = 0;
1223
1224 if(SiS_Pr->ChipType >= XGI_20) {
1225 /* XGI ROMs don't qualify */
1226 return FALSE;
1227 } else if(SiS_Pr->ChipType >= SIS_761) {
1228 /* I very much assume 761, 340 and newer will use new layout */
1229 return TRUE;
1230 } else if(SiS_Pr->ChipType >= SIS_661) {
1231 if((ROMAddr[0x1a] == 'N') &&
1232 (ROMAddr[0x1b] == 'e') &&
1233 (ROMAddr[0x1c] == 'w') &&
1234 (ROMAddr[0x1d] == 'V')) {
1235 return TRUE;
1236 }
1237 romversoffs = ROMAddr[0x16] | (ROMAddr[0x17] << 8);
1238 if(romversoffs) {
1239 if((ROMAddr[romversoffs+1] == '.') || (ROMAddr[romversoffs+4] == '.')) {
1240 romvmaj = ROMAddr[romversoffs] - '0';
1241 romvmin = ((ROMAddr[romversoffs+2] -'0') * 10) + (ROMAddr[romversoffs+3] - '0');
1242 }
1243 }
1244 if((romvmaj != 0) || (romvmin >= 92)) {
1245 return TRUE;
1246 }
1247 } else if(IS_SIS650740) {
1248 if((ROMAddr[0x1a] == 'N') &&
1249 (ROMAddr[0x1b] == 'e') &&
1250 (ROMAddr[0x1c] == 'w') &&
1251 (ROMAddr[0x1d] == 'V')) {
1252 return TRUE;
1253 }
1254 }
1255 return FALSE;
1256 }
1257
1258 static void
1259 SiSDetermineROMUsage(struct SiS_Private *SiS_Pr)
1260 {
1261 unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
1262 unsigned short romptr = 0;
1263
1264 SiS_Pr->SiS_UseROM = FALSE;
1265 SiS_Pr->SiS_ROMNew = FALSE;
1266 SiS_Pr->SiS_PWDOffset = 0;
1267
1268 if(SiS_Pr->ChipType >= XGI_20) return;
1269
1270 if((ROMAddr) && (SiS_Pr->UseROM)) {
1271 if(SiS_Pr->ChipType == SIS_300) {
1272 /* 300: We check if the code starts below 0x220 by
1273 * checking the jmp instruction at the beginning
1274 * of the BIOS image.
1275 */
1276 if((ROMAddr[3] == 0xe9) && ((ROMAddr[5] << 8) | ROMAddr[4]) > 0x21a)
1277 SiS_Pr->SiS_UseROM = TRUE;
1278 } else if(SiS_Pr->ChipType < SIS_315H) {
1279 /* Sony's VAIO BIOS 1.09 follows the standard, so perhaps
1280 * the others do as well
1281 */
1282 SiS_Pr->SiS_UseROM = TRUE;
1283 } else {
1284 /* 315/330 series stick to the standard(s) */
1285 SiS_Pr->SiS_UseROM = TRUE;
1286 if((SiS_Pr->SiS_ROMNew = SiSDetermineROMLayout661(SiS_Pr))) {
1287 SiS_Pr->SiS_EMIOffset = 14;
1288 SiS_Pr->SiS_PWDOffset = 17;
1289 SiS_Pr->SiS661LCD2TableSize = 36;
1290 /* Find out about LCD data table entry size */
1291 if((romptr = SISGETROMW(0x0102))) {
1292 if(ROMAddr[romptr + (32 * 16)] == 0xff)
1293 SiS_Pr->SiS661LCD2TableSize = 32;
1294 else if(ROMAddr[romptr + (34 * 16)] == 0xff)
1295 SiS_Pr->SiS661LCD2TableSize = 34;
1296 else if(ROMAddr[romptr + (36 * 16)] == 0xff) /* 0.94, 2.05.00+ */
1297 SiS_Pr->SiS661LCD2TableSize = 36;
1298 else if( (ROMAddr[romptr + (38 * 16)] == 0xff) || /* 2.00.00 - 2.02.00 */
1299 (ROMAddr[0x6F] & 0x01) ) { /* 2.03.00 - <2.05.00 */
1300 SiS_Pr->SiS661LCD2TableSize = 38; /* UMC data layout abandoned at 2.05.00 */
1301 SiS_Pr->SiS_EMIOffset = 16;
1302 SiS_Pr->SiS_PWDOffset = 19;
1303 }
1304 }
1305 }
1306 }
1307 }
1308 }
1309
1310 /*********************************************/
1311 /* HELPER: SET SEGMENT REGISTERS */
1312 /*********************************************/
1313
1314 static void
1315 SiS_SetSegRegLower(struct SiS_Private *SiS_Pr, unsigned short value)
1316 {
1317 unsigned short temp;
1318
1319 value &= 0x00ff;
1320 temp = SiS_GetRegByte(SiS_Pr->SiS_P3cb) & 0xf0;
1321 temp |= (value >> 4);
1322 SiS_SetRegByte(SiS_Pr->SiS_P3cb, temp);
1323 temp = SiS_GetRegByte(SiS_Pr->SiS_P3cd) & 0xf0;
1324 temp |= (value & 0x0f);
1325 SiS_SetRegByte(SiS_Pr->SiS_P3cd, temp);
1326 }
1327
1328 static void
1329 SiS_SetSegRegUpper(struct SiS_Private *SiS_Pr, unsigned short value)
1330 {
1331 unsigned short temp;
1332
1333 value &= 0x00ff;
1334 temp = SiS_GetRegByte(SiS_Pr->SiS_P3cb) & 0x0f;
1335 temp |= (value & 0xf0);
1336 SiS_SetRegByte(SiS_Pr->SiS_P3cb, temp);
1337 temp = SiS_GetRegByte(SiS_Pr->SiS_P3cd) & 0x0f;
1338 temp |= (value << 4);
1339 SiS_SetRegByte(SiS_Pr->SiS_P3cd, temp);
1340 }
1341
1342 static void
1343 SiS_SetSegmentReg(struct SiS_Private *SiS_Pr, unsigned short value)
1344 {
1345 SiS_SetSegRegLower(SiS_Pr, value);
1346 SiS_SetSegRegUpper(SiS_Pr, value);
1347 }
1348
1349 static void
1350 SiS_ResetSegmentReg(struct SiS_Private *SiS_Pr)
1351 {
1352 SiS_SetSegmentReg(SiS_Pr, 0);
1353 }
1354
1355 static void
1356 SiS_SetSegmentRegOver(struct SiS_Private *SiS_Pr, unsigned short value)
1357 {
1358 unsigned short temp = value >> 8;
1359
1360 temp &= 0x07;
1361 temp |= (temp << 4);
1362 SiS_SetReg(SiS_Pr->SiS_P3c4,0x1d,temp);
1363 SiS_SetSegmentReg(SiS_Pr, value);
1364 }
1365
1366 static void
1367 SiS_ResetSegmentRegOver(struct SiS_Private *SiS_Pr)
1368 {
1369 SiS_SetSegmentRegOver(SiS_Pr, 0);
1370 }
1371
1372 static void
1373 SiS_ResetSegmentRegisters(struct SiS_Private *SiS_Pr)
1374 {
1375 if((IS_SIS65x) || (SiS_Pr->ChipType >= SIS_661)) {
1376 SiS_ResetSegmentReg(SiS_Pr);
1377 SiS_ResetSegmentRegOver(SiS_Pr);
1378 }
1379 }
1380
1381 /*********************************************/
1382 /* HELPER: GetVBType */
1383 /*********************************************/
1384
1385 void
1386 SiS_GetVBType(struct SiS_Private *SiS_Pr)
1387 {
1388 unsigned short flag = 0, rev = 0, nolcd = 0;
1389 unsigned short p4_0f, p4_25, p4_27;
1390
1391 SiS_Pr->SiS_VBType = 0;
1392
1393 if((SiS_Pr->SiS_IF_DEF_LVDS) || (SiS_Pr->SiS_IF_DEF_CONEX))
1394 return;
1395
1396 if(SiS_Pr->ChipType == XGI_20)
1397 return;
1398
1399 flag = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x00);
1400
1401 if(flag > 3)
1402 return;
1403
1404 rev = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x01);
1405
1406 if(flag >= 2) {
1407 SiS_Pr->SiS_VBType = VB_SIS302B;
1408 } else if(flag == 1) {
1409 if(rev >= 0xC0) {
1410 SiS_Pr->SiS_VBType = VB_SIS301C;
1411 } else if(rev >= 0xB0) {
1412 SiS_Pr->SiS_VBType = VB_SIS301B;
1413 /* Check if 30xB DH version (no LCD support, use Panel Link instead) */
1414 nolcd = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x23);
1415 if(!(nolcd & 0x02)) SiS_Pr->SiS_VBType |= VB_NoLCD;
1416 } else {
1417 SiS_Pr->SiS_VBType = VB_SIS301;
1418 }
1419 }
1420 if(SiS_Pr->SiS_VBType & (VB_SIS301B | VB_SIS301C | VB_SIS302B)) {
1421 if(rev >= 0xE0) {
1422 flag = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x39);
1423 if(flag == 0xff) SiS_Pr->SiS_VBType = VB_SIS302LV;
1424 else SiS_Pr->SiS_VBType = VB_SIS301C; /* VB_SIS302ELV; */
1425 } else if(rev >= 0xD0) {
1426 SiS_Pr->SiS_VBType = VB_SIS301LV;
1427 }
1428 }
1429 if(SiS_Pr->SiS_VBType & (VB_SIS301C | VB_SIS301LV | VB_SIS302LV | VB_SIS302ELV)) {
1430 p4_0f = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x0f);
1431 p4_25 = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x25);
1432 p4_27 = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x27);
1433 SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x0f,0x7f);
1434 SiS_SetRegOR(SiS_Pr->SiS_Part4Port,0x25,0x08);
1435 SiS_SetRegAND(SiS_Pr->SiS_Part4Port,0x27,0xfd);
1436 if(SiS_GetReg(SiS_Pr->SiS_Part4Port,0x26) & 0x08) {
1437 SiS_Pr->SiS_VBType |= VB_UMC;
1438 }
1439 SiS_SetReg(SiS_Pr->SiS_Part4Port,0x27,p4_27);
1440 SiS_SetReg(SiS_Pr->SiS_Part4Port,0x25,p4_25);
1441 SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0f,p4_0f);
1442 }
1443 }
1444
1445 /*********************************************/
1446 /* HELPER: Get DRAM type */
1447 /*********************************************/
1448
1449 static unsigned char
1450 SiS_Get310DRAMType(struct SiS_Private *SiS_Pr)
1451 {
1452 unsigned char data;
1453
1454 if((*SiS_Pr->pSiS_SoftSetting) & SoftDRAMType) {
1455 data = (*SiS_Pr->pSiS_SoftSetting) & 0x03;
1456 } else {
1457 if(SiS_Pr->ChipType >= XGI_20) {
1458 /* Do I need this? SR17 seems to be zero anyway... */
1459 data = 0;
1460 } else if(SiS_Pr->ChipType >= SIS_340) {
1461 /* TODO */
1462 data = 0;
1463 } else if(SiS_Pr->ChipType >= SIS_661) {
1464 if(SiS_Pr->SiS_ROMNew) {
1465 data = ((SiS_GetReg(SiS_Pr->SiS_P3d4,0x78) & 0xc0) >> 6);
1466 } else {
1467 data = SiS_GetReg(SiS_Pr->SiS_P3d4,0x78) & 0x07;
1468 }
1469 } else if(IS_SIS550650740) {
1470 data = SiS_GetReg(SiS_Pr->SiS_P3c4,0x13) & 0x07;
1471 } else { /* 315, 330 */
1472 data = SiS_GetReg(SiS_Pr->SiS_P3c4,0x3a) & 0x03;
1473 if(SiS_Pr->ChipType == SIS_330) {
1474 if(data > 1) {
1475 switch(SiS_GetReg(SiS_Pr->SiS_P3d4,0x5f) & 0x30) {
1476 case 0x00: data = 1; break;
1477 case 0x10: data = 3; break;
1478 case 0x20: data = 3; break;
1479 case 0x30: data = 2; break;
1480 }
1481 } else {
1482 data = 0;
1483 }
1484 }
1485 }
1486 }
1487
1488 return data;
1489 }
1490
1491 static unsigned short
1492 SiS_GetMCLK(struct SiS_Private *SiS_Pr)
1493 {
1494 unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
1495 unsigned short index;
1496
1497 index = SiS_Get310DRAMType(SiS_Pr);
1498 if(SiS_Pr->ChipType >= SIS_661) {
1499 if(SiS_Pr->SiS_ROMNew) {
1500 return((unsigned short)(SISGETROMW((0x90 + (index * 5) + 3))));
1501 }
1502 return(SiS_Pr->SiS_MCLKData_0[index].CLOCK);
1503 } else if(index >= 4) {
1504 return(SiS_Pr->SiS_MCLKData_1[index - 4].CLOCK);
1505 } else {
1506 return(SiS_Pr->SiS_MCLKData_0[index].CLOCK);
1507 }
1508 }
1509
1510 /*********************************************/
1511 /* HELPER: SearchModeID */
1512 /*********************************************/
1513
1514 BOOLEAN
1515 SiS_SearchModeID(struct SiS_Private *SiS_Pr, unsigned short *ModeNo,
1516 unsigned short *ModeIdIndex)
1517 {
1518 unsigned char VGAINFO = SiS_Pr->SiS_VGAINFO;
1519
1520 if((*ModeNo) <= 0x13) {
1521
1522 if((*ModeNo) <= 0x05) (*ModeNo) |= 0x01;
1523
1524 for((*ModeIdIndex) = 0; ;(*ModeIdIndex)++) {
1525 if(SiS_Pr->SiS_SModeIDTable[(*ModeIdIndex)].St_ModeID == (*ModeNo)) break;
1526 if(SiS_Pr->SiS_SModeIDTable[(*ModeIdIndex)].St_ModeID == 0xFF) return FALSE;
1527 }
1528
1529 if((*ModeNo) == 0x07) {
1530 if(VGAINFO & 0x10) (*ModeIdIndex)++; /* 400 lines */
1531 /* else 350 lines */
1532 }
1533 if((*ModeNo) <= 0x03) {
1534 if(!(VGAINFO & 0x80)) (*ModeIdIndex)++;
1535 if(VGAINFO & 0x10) (*ModeIdIndex)++; /* 400 lines */
1536 /* else 350 lines */
1537 }
1538 /* else 200 lines */
1539
1540 } else {
1541
1542 for((*ModeIdIndex) = 0; ;(*ModeIdIndex)++) {
1543 if(SiS_Pr->SiS_EModeIDTable[(*ModeIdIndex)].Ext_ModeID == (*ModeNo)) break;
1544 if(SiS_Pr->SiS_EModeIDTable[(*ModeIdIndex)].Ext_ModeID == 0xFF) return FALSE;
1545 }
1546
1547 }
1548 return TRUE;
1549 }
1550
1551 /*********************************************/
1552 /* HELPER: GetModePtr */
1553 /*********************************************/
1554
1555 unsigned short
1556 SiS_GetModePtr(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
1557 {
1558 unsigned short index;
1559
1560 if(ModeNo <= 0x13) {
1561 index = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_StTableIndex;
1562 } else {
1563 if(SiS_Pr->SiS_ModeType <= ModeEGA) index = 0x1B;
1564 else index = 0x0F;
1565 }
1566 return index;
1567 }
1568
1569 /*********************************************/
1570 /* HELPERS: Get some indices */
1571 /*********************************************/
1572
1573 unsigned short
1574 SiS_GetRefCRTVCLK(struct SiS_Private *SiS_Pr, unsigned short Index, int UseWide)
1575 {
1576 if(SiS_Pr->SiS_RefIndex[Index].Ext_InfoFlag & HaveWideTiming) {
1577 if(UseWide == 1) {
1578 return SiS_Pr->SiS_RefIndex[Index].Ext_CRTVCLK_WIDE;
1579 } else {
1580 return SiS_Pr->SiS_RefIndex[Index].Ext_CRTVCLK_NORM;
1581 }
1582 } else {
1583 return SiS_Pr->SiS_RefIndex[Index].Ext_CRTVCLK;
1584 }
1585 }
1586
1587 unsigned short
1588 SiS_GetRefCRT1CRTC(struct SiS_Private *SiS_Pr, unsigned short Index, int UseWide)
1589 {
1590 if(SiS_Pr->SiS_RefIndex[Index].Ext_InfoFlag & HaveWideTiming) {
1591 if(UseWide == 1) {
1592 return SiS_Pr->SiS_RefIndex[Index].Ext_CRT1CRTC_WIDE;
1593 } else {
1594 return SiS_Pr->SiS_RefIndex[Index].Ext_CRT1CRTC_NORM;
1595 }
1596 } else {
1597 return SiS_Pr->SiS_RefIndex[Index].Ext_CRT1CRTC;
1598 }
1599 }
1600
1601 /*********************************************/
1602 /* HELPER: LowModeTests */
1603 /*********************************************/
1604
1605 static BOOLEAN
1606 SiS_DoLowModeTest(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
1607 {
1608 unsigned short temp, temp1, temp2;
1609
1610 if((ModeNo != 0x03) && (ModeNo != 0x10) && (ModeNo != 0x12))
1611 return TRUE;
1612 temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x11);
1613 SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x11,0x80);
1614 temp1 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x00);
1615 SiS_SetReg(SiS_Pr->SiS_P3d4,0x00,0x55);
1616 temp2 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x00);
1617 SiS_SetReg(SiS_Pr->SiS_P3d4,0x00,temp1);
1618 SiS_SetReg(SiS_Pr->SiS_P3d4,0x11,temp);
1619 if((SiS_Pr->ChipType >= SIS_315H) ||
1620 (SiS_Pr->ChipType == SIS_300)) {
1621 if(temp2 == 0x55) return FALSE;
1622 else return TRUE;
1623 } else {
1624 if(temp2 != 0x55) return TRUE;
1625 else {
1626 SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x35,0x01);
1627 return FALSE;
1628 }
1629 }
1630 }
1631
1632 static void
1633 SiS_SetLowModeTest(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
1634 {
1635 if(SiS_DoLowModeTest(SiS_Pr, ModeNo)) {
1636 SiS_Pr->SiS_SetFlag |= LowModeTests;
1637 }
1638 }
1639
1640 /*********************************************/
1641 /* HELPER: OPEN/CLOSE CRT1 CRTC */
1642 /*********************************************/
1643
1644 static void
1645 SiS_OpenCRTC(struct SiS_Private *SiS_Pr)
1646 {
1647 if(IS_SIS650) {
1648 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x51,0x1f);
1649 if(IS_SIS651) SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x51,0x20);
1650 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x56,0xe7);
1651 } else if(IS_SIS661741660760) {
1652 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x61,0xf7);
1653 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x51,0x1f);
1654 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x56,0xe7);
1655 if(!SiS_Pr->SiS_ROMNew) {
1656 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x3a,0xef);
1657 }
1658 }
1659 }
1660
1661 static void
1662 SiS_CloseCRTC(struct SiS_Private *SiS_Pr)
1663 {
1664 #if 0 /* This locks some CRTC registers. We don't want that. */
1665 unsigned short temp1 = 0, temp2 = 0;
1666
1667 if(IS_SIS661741660760) {
1668 if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
1669 temp1 = 0xa0; temp2 = 0x08;
1670 }
1671 SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x51,0x1f,temp1);
1672 SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x56,0xe7,temp2);
1673 }
1674 #endif
1675 }
1676
1677 static void
1678 SiS_HandleCRT1(struct SiS_Private *SiS_Pr)
1679 {
1680 /* Enable CRT1 gating */
1681 SiS_SetRegAND(SiS_Pr->SiS_P3d4,SiS_Pr->SiS_MyCR63,0xbf);
1682 #if 0
1683 if(!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x15) & 0x01)) {
1684 if((SiS_GetReg(SiS_Pr->SiS_P3c4,0x15) & 0x0a) ||
1685 (SiS_GetReg(SiS_Pr->SiS_P3c4,0x16) & 0x01)) {
1686 SiS_SetRegOR(SiS_Pr->SiS_P3d4,SiS_Pr->SiS_MyCR63,0x40);
1687 }
1688 }
1689 #endif
1690 }
1691
1692 /*********************************************/
1693 /* HELPER: GetColorDepth */
1694 /*********************************************/
1695
1696 unsigned short
1697 SiS_GetColorDepth(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
1698 unsigned short ModeIdIndex)
1699 {
1700 static const unsigned short ColorDepth[6] = { 1, 2, 4, 4, 6, 8 };
1701 unsigned short modeflag;
1702 short index;
1703
1704 /* Do NOT check UseCustomMode, will skrew up FIFO */
1705 if(ModeNo == 0xfe) {
1706 modeflag = SiS_Pr->CModeFlag;
1707 } else if(ModeNo <= 0x13) {
1708 modeflag = SiS_Pr->SiS_SModeIDTable[ModeIdIndex].St_ModeFlag;
1709 } else {
1710 modeflag = SiS_Pr->SiS_EModeIDTable[ModeIdIndex].Ext_ModeFlag;
1711 }
1712
1713 index = (modeflag & ModeTypeMask) - ModeEGA;
1714 if(index < 0) index = 0;
1715 return ColorDepth[index];
1716 }
1717
1718 /*********************************************/
1719 /* HELPER: GetOffset */
1720 /*********************************************/
1721
1722 unsigned short
1723 SiS_GetOffset(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
1724 unsigned short ModeIdIndex, unsigned short RRTI)
1725 {
1726 unsigned short xres, temp, colordepth, infoflag;
1727
1728 if(SiS_Pr->UseCustomMode) {
1729 infoflag = SiS_Pr->CInfoFlag;
1730 xres = SiS_Pr->CHDisplay;
1731 } else {
1732 infoflag = SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag;
1733 xres = SiS_Pr->SiS_RefIndex[RRTI].XRes;
1734 }
1735
1736 colordepth = SiS_GetColorDepth(SiS_Pr, ModeNo, ModeIdIndex);
1737
1738 temp = xres / 16;
1739 if(infoflag & InterlaceMode) temp <<= 1;
1740 temp *= colordepth;
1741 if(xres % 16) temp += (colordepth >> 1);
1742
1743 return temp;
1744 }
1745
1746 /*********************************************/
1747 /* SEQ */
1748 /*********************************************/
1749
1750 static void
1751 SiS_SetSeqRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
1752 {
1753 unsigned char SRdata;
1754 int i;
1755
1756 SiS_SetReg(SiS_Pr->SiS_P3c4,0x00,0x03);
1757
1758 /* or "display off" */
1759 SRdata = SiS_Pr->SiS_StandTable[StandTableIndex].SR[0] | 0x20;
1760
1761 /* determine whether to force x8 dotclock */
1762 if((SiS_Pr->SiS_VBType & VB_SISVB) || (SiS_Pr->SiS_IF_DEF_LVDS)) {
1763
1764 if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToTV)) {
1765 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) SRdata |= 0x01;
1766 } else if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) SRdata |= 0x01;
1767
1768 }
1769
1770 SiS_SetReg(SiS_Pr->SiS_P3c4,0x01,SRdata);
1771
1772 for(i = 2; i <= 4; i++) {
1773 SRdata = SiS_Pr->SiS_StandTable[StandTableIndex].SR[i - 1];
1774 SiS_SetReg(SiS_Pr->SiS_P3c4,i,SRdata);
1775 }
1776 }
1777
1778 /*********************************************/
1779 /* MISC */
1780 /*********************************************/
1781
1782 static void
1783 SiS_SetMiscRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
1784 {
1785 unsigned char Miscdata;
1786
1787 Miscdata = SiS_Pr->SiS_StandTable[StandTableIndex].MISC;
1788
1789 if(SiS_Pr->ChipType < SIS_661) {
1790 if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
1791 if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
1792 Miscdata |= 0x0C;
1793 }
1794 }
1795 }
1796
1797 SiS_SetRegByte(SiS_Pr->SiS_P3c2,Miscdata);
1798 }
1799
1800 /*********************************************/
1801 /* CRTC */
1802 /*********************************************/
1803
1804 static void
1805 SiS_SetCRTCRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
1806 {
1807 unsigned char CRTCdata;
1808 unsigned short i;
1809
1810 /* Unlock CRTC */
1811 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x11,0x7f);
1812
1813 for(i = 0; i <= 0x18; i++) {
1814 CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i];
1815 SiS_SetReg(SiS_Pr->SiS_P3d4,i,CRTCdata);
1816 }
1817
1818 if(SiS_Pr->ChipType >= SIS_661) {
1819 SiS_OpenCRTC(SiS_Pr);
1820 for(i = 0x13; i <= 0x14; i++) {
1821 CRTCdata = SiS_Pr->SiS_StandTable[StandTableIndex].CRTC[i];
1822 SiS_SetReg(SiS_Pr->SiS_P3d4,i,CRTCdata);
1823 }
1824 } else if( ( (SiS_Pr->ChipType == SIS_630) ||
1825 (SiS_Pr->ChipType == SIS_730) ) &&
1826 (SiS_Pr->ChipRevision >= 0x30) ) {
1827 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
1828 if(SiS_Pr->SiS_VBInfo & (SetCRT2ToLCD | SetCRT2ToTV)) {
1829 SiS_SetReg(SiS_Pr->SiS_P3d4,0x18,0xFE);
1830 }
1831 }
1832 }
1833 }
1834
1835 /*********************************************/
1836 /* ATT */
1837 /*********************************************/
1838
1839 static void
1840 SiS_SetATTRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
1841 {
1842 unsigned char ARdata;
1843 unsigned short i;
1844
1845 for(i = 0; i <= 0x13; i++) {
1846 ARdata = SiS_Pr->SiS_StandTable[StandTableIndex].ATTR[i];
1847
1848 if(i == 0x13) {
1849 /* Pixel shift. If screen on LCD or TV is shifted left or right,
1850 * this might be the cause.
1851 */
1852 if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
1853 if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) ARdata = 0;
1854 }
1855 if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
1856 if(SiS_Pr->SiS_IF_DEF_CH70xx != 0) {
1857 if(SiS_Pr->SiS_VBInfo & SetCRT2ToTV) {
1858 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) ARdata = 0;
1859 }
1860 }
1861 }
1862 if(SiS_Pr->ChipType >= SIS_661) {
1863 if(SiS_Pr->SiS_VBInfo & (SetCRT2ToTV | SetCRT2ToLCD)) {
1864 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) ARdata = 0;
1865 }
1866 } else if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
1867 if(SiS_Pr->ChipType >= SIS_315H) {
1868 if(IS_SIS550650740660) {
1869 /* 315, 330 don't do this */
1870 if(SiS_Pr->SiS_VBType & VB_SIS30xB) {
1871 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) ARdata = 0;
1872 } else {
1873 ARdata = 0;
1874 }
1875 }
1876 } else {
1877 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) ARdata = 0;
1878 }
1879 }
1880 }
1881 SiS_GetRegByte(SiS_Pr->SiS_P3da); /* reset 3da */
1882 SiS_SetRegByte(SiS_Pr->SiS_P3c0,i); /* set index */
1883 SiS_SetRegByte(SiS_Pr->SiS_P3c0,ARdata); /* set data */
1884 }
1885
1886 SiS_GetRegByte(SiS_Pr->SiS_P3da); /* reset 3da */
1887 SiS_SetRegByte(SiS_Pr->SiS_P3c0,0x14); /* set index */
1888 SiS_SetRegByte(SiS_Pr->SiS_P3c0,0x00); /* set data */
1889
1890 SiS_GetRegByte(SiS_Pr->SiS_P3da);
1891 SiS_SetRegByte(SiS_Pr->SiS_P3c0,0x20); /* Enable Attribute */
1892 SiS_GetRegByte(SiS_Pr->SiS_P3da);
1893 }
1894
1895 /*********************************************/
1896 /* GRC */
1897 /*********************************************/
1898
1899 static void
1900 SiS_SetGRCRegs(struct SiS_Private *SiS_Pr, unsigned short StandTableIndex)
1901 {
1902 unsigned char GRdata;
1903 unsigned short i;
1904
1905 for(i = 0; i <= 0x08; i++) {
1906 GRdata = SiS_Pr->SiS_StandTable[StandTableIndex].GRC[i];
1907 SiS_SetReg(SiS_Pr->SiS_P3ce,i,GRdata);
1908 }
1909
1910 if(SiS_Pr->SiS_ModeType > ModeVGA) {
1911 /* 256 color disable */
1912 SiS_SetRegAND(SiS_Pr->SiS_P3ce,0x05,0xBF);
1913 }
1914 }
1915
1916 /*********************************************/
1917 /* CLEAR EXTENDED REGISTERS */
1918 /*********************************************/
1919
1920 static void
1921 SiS_ClearExt1Regs(struct SiS_Private *SiS_Pr, unsigned short ModeNo)
1922 {
1923 unsigned short i;
1924
1925 for(i = 0x0A; i <= 0x0E; i++) {
1926 SiS_SetReg(SiS_Pr->SiS_P3c4,i,0x00);
1927 }
1928
1929 if(SiS_Pr->ChipType >= SIS_315H) {
1930 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x37,0xFE);
1931 if(ModeNo <= 0x13) {
1932 if(ModeNo == 0x06 || ModeNo >= 0x0e) {
1933 SiS_SetReg(SiS_Pr->SiS_P3c4,0x0e,0x20);
1934 }
1935 }
1936 }
1937 }
1938
1939 /*********************************************/
1940 /* RESET VCLK */
1941 /*********************************************/
1942
1943 static void
1944 SiS_ResetCRT1VCLK(struct SiS_Private *SiS_Pr)
1945 {
1946 if(SiS_Pr->ChipType >= SIS_315H) {
1947 if(SiS_Pr->ChipType < SIS_661) {
1948 if(SiS_Pr->SiS_IF_DEF_LVDS == 0) return;
1949 }
1950 } else {
1951 if((SiS_Pr->SiS_IF_DEF_LVDS == 0) &&
1952 (!(SiS_Pr->SiS_VBType & VB_SIS30xBLV)) ) {
1953 return;
1954 }
1955 }
1956
1957 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x31,0xcf,0x20);
1958 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2B,SiS_Pr->SiS_VCLKData[1].SR2B);
1959 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2C,SiS_Pr->SiS_VCLKData[1].SR2C);
1960 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2D,0x80);
1961 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x31,0xcf,0x10);
1962 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2B,SiS_Pr->SiS_VCLKData[0].SR2B);
1963 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2C,SiS_Pr->SiS_VCLKData[0].SR2C);
1964 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2D,0x80);
1965 }
1966
1967 /*********************************************/
1968 /* SYNC */
1969 /*********************************************/
1970
1971 static void
1972 SiS_SetCRT1Sync(struct SiS_Private *SiS_Pr, unsigned short RRTI)
1973 {
1974 unsigned short sync;
1975
1976 if(SiS_Pr->UseCustomMode) {
1977 sync = SiS_Pr->CInfoFlag >> 8;
1978 } else {
1979 sync = SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag >> 8;
1980 }
1981
1982 sync &= 0xC0;
1983 sync |= 0x2f;
1984 SiS_SetRegByte(SiS_Pr->SiS_P3c2,sync);
1985 }
1986
1987 /*********************************************/
1988 /* CRTC/2 */
1989 /*********************************************/
1990
1991 static void
1992 SiS_SetCRT1CRTC(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
1993 unsigned short ModeIdIndex, unsigned short RRTI)
1994 {
1995 unsigned short temp, i, j, modeflag;
1996 unsigned char *crt1data = NULL;
1997
1998 modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
1999
2000 if(SiS_Pr->UseCustomMode) {
2001
2002 crt1data = &SiS_Pr->CCRT1CRTC[0];
2003
2004 } else {
2005
2006 temp = SiS_GetRefCRT1CRTC(SiS_Pr, RRTI, SiS_Pr->SiS_UseWide);
2007
2008 /* Alternate for 1600x1200 LCDA */
2009 if((temp == 0x20) && (SiS_Pr->Alternate1600x1200)) temp = 0x57;
2010
2011 crt1data = (unsigned char *)&SiS_Pr->SiS_CRT1Table[temp].CR[0];
2012
2013 }
2014
2015 /* unlock cr0-7 */
2016 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x11,0x7f);
2017
2018 for(i = 0, j = 0; i <= 7; i++, j++) {
2019 SiS_SetReg(SiS_Pr->SiS_P3d4,j,crt1data[i]);
2020 }
2021 for(j = 0x10; i <= 10; i++, j++) {
2022 SiS_SetReg(SiS_Pr->SiS_P3d4,j,crt1data[i]);
2023 }
2024 for(j = 0x15; i <= 12; i++, j++) {
2025 SiS_SetReg(SiS_Pr->SiS_P3d4,j,crt1data[i]);
2026 }
2027 for(j = 0x0A; i <= 15; i++, j++) {
2028 SiS_SetReg(SiS_Pr->SiS_P3c4,j,crt1data[i]);
2029 }
2030
2031 SiS_SetReg(SiS_Pr->SiS_P3c4,0x0E,crt1data[16] & 0xE0);
2032
2033 temp = (crt1data[16] & 0x01) << 5;
2034 if(modeflag & DoubleScanMode) temp |= 0x80;
2035 SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x09,0x5F,temp);
2036
2037 if(SiS_Pr->SiS_ModeType > ModeVGA) {
2038 SiS_SetReg(SiS_Pr->SiS_P3d4,0x14,0x4F);
2039 }
2040
2041 if(SiS_Pr->ChipType == XGI_20) {
2042 SiS_SetReg(SiS_Pr->SiS_P3d4,0x04,crt1data[4] - 1);
2043 if(!(temp = crt1data[5] & 0x1f)) {
2044 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x0c,0xfb);
2045 }
2046 SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x05,0xe0,((temp - 1) & 0x1f));
2047 temp = (crt1data[16] >> 5) + 3;
2048 if(temp > 7) temp -= 7;
2049 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0e,0x1f,(temp << 5));
2050 }
2051 }
2052
2053 /*********************************************/
2054 /* OFFSET & PITCH */
2055 /*********************************************/
2056 /* (partly overruled by SetPitch() in XF86) */
2057 /*********************************************/
2058
2059 static void
2060 SiS_SetCRT1Offset(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
2061 unsigned short ModeIdIndex, unsigned short RRTI)
2062 {
2063 unsigned short temp, DisplayUnit, infoflag;
2064
2065 if(SiS_Pr->UseCustomMode) {
2066 infoflag = SiS_Pr->CInfoFlag;
2067 } else {
2068 infoflag = SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag;
2069 }
2070
2071 DisplayUnit = SiS_GetOffset(SiS_Pr, ModeNo, ModeIdIndex, RRTI);
2072
2073 temp = (DisplayUnit >> 8) & 0x0f;
2074 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0E,0xF0,temp);
2075
2076 SiS_SetReg(SiS_Pr->SiS_P3d4,0x13,DisplayUnit & 0xFF);
2077
2078 if(infoflag & InterlaceMode) DisplayUnit >>= 1;
2079
2080 DisplayUnit <<= 5;
2081 temp = (DisplayUnit >> 8) + 1;
2082 if(DisplayUnit & 0xff) temp++;
2083 if(SiS_Pr->ChipType == XGI_20) {
2084 if(ModeNo == 0x4a || ModeNo == 0x49) temp--;
2085 }
2086 SiS_SetReg(SiS_Pr->SiS_P3c4,0x10,temp);
2087 }
2088
2089 /*********************************************/
2090 /* VCLK */
2091 /*********************************************/
2092
2093 static void
2094 SiS_SetCRT1VCLK(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
2095 unsigned short ModeIdIndex, unsigned short RRTI)
2096 {
2097 unsigned short index = 0, clka, clkb;
2098
2099 if(SiS_Pr->UseCustomMode) {
2100 clka = SiS_Pr->CSR2B;
2101 clkb = SiS_Pr->CSR2C;
2102 } else {
2103 index = SiS_GetVCLK2Ptr(SiS_Pr, ModeNo, ModeIdIndex, RRTI);
2104 if((SiS_Pr->SiS_VBType & VB_SIS30xBLV) &&
2105 (SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
2106 /* Alternate for 1600x1200 LCDA */
2107 if((index == 0x21) && (SiS_Pr->Alternate1600x1200)) index = 0x72;
2108 clka = SiS_Pr->SiS_VBVCLKData[index].Part4_A;
2109 clkb = SiS_Pr->SiS_VBVCLKData[index].Part4_B;
2110 } else {
2111 clka = SiS_Pr->SiS_VCLKData[index].SR2B;
2112 clkb = SiS_Pr->SiS_VCLKData[index].SR2C;
2113 }
2114 }
2115
2116 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x31,0xCF);
2117
2118 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2b,clka);
2119 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2c,clkb);
2120
2121 if(SiS_Pr->ChipType >= SIS_315H) {
2122 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2D,0x01);
2123 if(SiS_Pr->ChipType == XGI_20) {
2124 unsigned short mf = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
2125 if(mf & HalfDCLK) {
2126 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2b,SiS_GetReg(SiS_Pr->SiS_P3c4,0x2b));
2127 clkb = SiS_GetReg(SiS_Pr->SiS_P3c4,0x2c);
2128 clkb = (((clkb & 0x1f) << 1) + 1) | (clkb & 0xe0);
2129 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2c,clkb);
2130 }
2131 }
2132 } else {
2133 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2D,0x80);
2134 }
2135 }
2136
2137 /*********************************************/
2138 /* FIFO */
2139 /*********************************************/
2140
2141 void
2142 SiS_GetFIFOThresholdIndex300(struct SiS_Private *SiS_Pr, unsigned short *idx1,
2143 unsigned short *idx2)
2144 {
2145 unsigned short temp1, temp2;
2146 static const unsigned char ThTiming[8] = {
2147 1, 2, 2, 3, 0, 1, 1, 2
2148 };
2149
2150 temp1 = temp2 = (SiS_GetReg(SiS_Pr->SiS_P3c4,0x18) & 0x62) >> 1;
2151 (*idx2) = (unsigned short)(ThTiming[((temp2 >> 3) | temp1) & 0x07]);
2152 (*idx1) = (unsigned short)(SiS_GetReg(SiS_Pr->SiS_P3c4,0x16) >> 6) & 0x03;
2153 (*idx1) |= (unsigned short)(((SiS_GetReg(SiS_Pr->SiS_P3c4,0x14) >> 4) & 0x0c));
2154 (*idx1) <<= 1;
2155 }
2156
2157 static unsigned short
2158 SiS_GetFIFOThresholdA300(unsigned short idx1, unsigned short idx2)
2159 {
2160 static const unsigned char ThLowA[8 * 3] = {
2161 61, 3,52, 5,68, 7,100,11,
2162 43, 3,42, 5,54, 7, 78,11,
2163 34, 3,37, 5,47, 7, 67,11
2164 };
2165
2166 return (unsigned short)((ThLowA[idx1 + 1] * idx2) + ThLowA[idx1]);
2167 }
2168
2169 unsigned short
2170 SiS_GetFIFOThresholdB300(unsigned short idx1, unsigned short idx2)
2171 {
2172 static const unsigned char ThLowB[8 * 3] = {
2173 81, 4,72, 6,88, 8,120,12,
2174 55, 4,54, 6,66, 8, 90,12,
2175 42, 4,45, 6,55, 8, 75,12
2176 };
2177
2178 return (unsigned short)((ThLowB[idx1 + 1] * idx2) + ThLowB[idx1]);
2179 }
2180
2181 static unsigned short
2182 SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK,
2183 unsigned short colordepth, unsigned short key)
2184 {
2185 unsigned short idx1, idx2;
2186 unsigned int longtemp = VCLK * colordepth;
2187
2188 SiS_GetFIFOThresholdIndex300(SiS_Pr, &idx1, &idx2);
2189
2190 if(key == 0) {
2191 longtemp *= SiS_GetFIFOThresholdA300(idx1, idx2);
2192 } else {
2193 longtemp *= SiS_GetFIFOThresholdB300(idx1, idx2);
2194 }
2195 idx1 = longtemp % (MCLK * 16);
2196 longtemp /= (MCLK * 16);
2197 if(idx1) longtemp++;
2198 return (unsigned short)longtemp;
2199 }
2200
2201 static unsigned short
2202 SiS_CalcDelay(struct SiS_Private *SiS_Pr, unsigned short VCLK,
2203 unsigned short colordepth, unsigned short MCLK)
2204 {
2205 unsigned short temp1, temp2;
2206
2207 temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0);
2208 temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1);
2209 if(temp1 < 4) temp1 = 4;
2210 temp1 -= 4;
2211 if(temp2 < temp1) temp2 = temp1;
2212 return temp2;
2213 }
2214
2215 static void
2216 SiS_SetCRT1FIFO_300(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
2217 unsigned short RefreshRateTableIndex)
2218 {
2219 unsigned short ThresholdLow = 0;
2220 unsigned short temp, index, VCLK, MCLK, colorth;
2221 static const unsigned short colortharray[6] = { 1, 1, 2, 2, 3, 4 };
2222
2223 if(ModeNo > 0x13) {
2224
2225 /* Get VCLK */
2226 if(SiS_Pr->UseCustomMode) {
2227 VCLK = SiS_Pr->CSRClock;
2228 } else {
2229 index = SiS_GetRefCRTVCLK(SiS_Pr, RefreshRateTableIndex, SiS_Pr->SiS_UseWide);
2230 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK;
2231 }
2232
2233 /* Get half colordepth */
2234 colorth = colortharray[(SiS_Pr->SiS_ModeType - ModeEGA)];
2235
2236 /* Get MCLK */
2237 index = SiS_GetReg(SiS_Pr->SiS_P3c4,0x3A) & 0x07;
2238 MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK;
2239
2240 temp = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35) & 0xc3;
2241 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x16,0x3c,temp);
2242
2243 do {
2244 ThresholdLow = SiS_CalcDelay(SiS_Pr, VCLK, colorth, MCLK) + 1;
2245 if(ThresholdLow < 0x13) break;
2246 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x16,0xfc);
2247 ThresholdLow = 0x13;
2248 temp = SiS_GetReg(SiS_Pr->SiS_P3c4,0x16) >> 6;
2249 if(!temp) break;
2250 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x16,0x3f,((temp - 1) << 6));
2251 } while(0);
2252
2253 } else ThresholdLow = 2;
2254
2255 /* Write CRT/CPU threshold low, CRT/Engine threshold high */
2256 temp = (ThresholdLow << 4) | 0x0f;
2257 SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,temp);
2258
2259 temp = (ThresholdLow & 0x10) << 1;
2260 if(ModeNo > 0x13) temp |= 0x40;
2261 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0f,0x9f,temp);
2262
2263 /* What is this? */
2264 SiS_SetReg(SiS_Pr->SiS_P3c4,0x3B,0x09);
2265
2266 /* Write CRT/CPU threshold high */
2267 temp = ThresholdLow + 3;
2268 if(temp > 0x0f) temp = 0x0f;
2269 SiS_SetReg(SiS_Pr->SiS_P3c4,0x09,temp);
2270 }
2271
2272 unsigned short
2273 SiS_GetLatencyFactor630(struct SiS_Private *SiS_Pr, unsigned short index)
2274 {
2275 static const unsigned char LatencyFactor[] = {
2276 97, 88, 86, 79, 77, 0, /* 64 bit BQ=2 */
2277 0, 87, 85, 78, 76, 54, /* 64 bit BQ=1 */
2278 97, 88, 86, 79, 77, 0, /* 128 bit BQ=2 */
2279 0, 79, 77, 70, 68, 48, /* 128 bit BQ=1 */
2280 80, 72, 69, 63, 61, 0, /* 64 bit BQ=2 */
2281 0, 70, 68, 61, 59, 37, /* 64 bit BQ=1 */
2282 86, 77, 75, 68, 66, 0, /* 128 bit BQ=2 */
2283 0, 68, 66, 59, 57, 37 /* 128 bit BQ=1 */
2284 };
2285 static const unsigned char LatencyFactor730[] = {
2286 69, 63, 61,
2287 86, 79, 77,
2288 103, 96, 94,
2289 120,113,111,
2290 137,130,128
2291 };
2292
2293 if(SiS_Pr->ChipType == SIS_730) {
2294 return (unsigned short)LatencyFactor730[index];
2295 } else {
2296 return (unsigned short)LatencyFactor[index];
2297 }
2298 }
2299
2300 static unsigned short
2301 SiS_CalcDelay2(struct SiS_Private *SiS_Pr, unsigned char key)
2302 {
2303 unsigned short index;
2304
2305 if(SiS_Pr->ChipType == SIS_730) {
2306 index = ((key & 0x0f) * 3) + ((key & 0xc0) >> 6);
2307 } else {
2308 index = (key & 0xe0) >> 5;
2309 if(key & 0x10) index += 6;
2310 if(!(key & 0x01)) index += 24;
2311 if(SiS_GetReg(SiS_Pr->SiS_P3c4,0x14) & 0x80) index += 12;
2312 }
2313 return SiS_GetLatencyFactor630(SiS_Pr, index);
2314 }
2315
2316 static void
2317 SiS_SetCRT1FIFO_630(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
2318 unsigned short RefreshRateTableIndex)
2319 {
2320 unsigned short ThresholdLow = 0;
2321 unsigned short i, data, VCLK, MCLK16, colorth = 0;
2322 unsigned int templ, datal;
2323 const unsigned char *queuedata = NULL;
2324 static const unsigned char FQBQData[21] = {
2325 0x01,0x21,0x41,0x61,0x81,
2326 0x31,0x51,0x71,0x91,0xb1,
2327 0x00,0x20,0x40,0x60,0x80,
2328 0x30,0x50,0x70,0x90,0xb0,
2329 0xff
2330 };
2331 static const unsigned char FQBQData730[16] = {
2332 0x34,0x74,0xb4,
2333 0x23,0x63,0xa3,
2334 0x12,0x52,0x92,
2335 0x01,0x41,0x81,
2336 0x00,0x40,0x80,
2337 0xff
2338 };
2339 static const unsigned short colortharray[6] = {
2340 1, 1, 2, 2, 3, 4
2341 };
2342
2343 i = 0;
2344
2345 if(ModeNo > 0x13) {
2346
2347 /* Get VCLK */
2348 if(SiS_Pr->UseCustomMode) {
2349 VCLK = SiS_Pr->CSRClock;
2350 } else {
2351 data = SiS_GetRefCRTVCLK(SiS_Pr, RefreshRateTableIndex, SiS_Pr->SiS_UseWide);
2352 VCLK = SiS_Pr->SiS_VCLKData[data].CLOCK;
2353 }
2354
2355 /* Get MCLK * 16 */
2356 data = SiS_GetReg(SiS_Pr->SiS_P3c4,0x1A) & 0x07;
2357 MCLK16 = SiS_Pr->SiS_MCLKData_0[data].CLOCK * 16;
2358
2359 /* Get half colordepth */
2360 colorth = colortharray[(SiS_Pr->SiS_ModeType - ModeEGA)];
2361
2362 if(SiS_Pr->ChipType == SIS_730) {
2363 queuedata = &FQBQData730[0];
2364 } else {
2365 queuedata = &FQBQData[0];
2366 }
2367
2368 do {
2369 templ = SiS_CalcDelay2(SiS_Pr, queuedata[i]) * VCLK * colorth;
2370
2371 datal = templ % MCLK16;
2372 templ = (templ / MCLK16) + 1;
2373 if(datal) templ++;
2374
2375 if(templ > 0x13) {
2376 if(queuedata[i + 1] == 0xFF) {
2377 ThresholdLow = 0x13;
2378 break;
2379 }
2380 i++;
2381 } else {
2382 ThresholdLow = templ;
2383 break;
2384 }
2385 } while(queuedata[i] != 0xFF);
2386
2387 } else {
2388
2389 if(SiS_Pr->ChipType != SIS_730) i = 9;
2390 ThresholdLow = 0x02;
2391
2392 }
2393
2394 /* Write CRT/CPU threshold low, CRT/Engine threshold high */
2395 data = ((ThresholdLow & 0x0f) << 4) | 0x0f;
2396 SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,data);
2397
2398 data = (ThresholdLow & 0x10) << 1;
2399 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0F,0xDF,data);
2400
2401 /* What is this? */
2402 SiS_SetReg(SiS_Pr->SiS_P3c4,0x3B,0x09);
2403
2404 /* Write CRT/CPU threshold high (gap = 3) */
2405 data = ThresholdLow + 3;
2406 if(data > 0x0f) data = 0x0f;
2407 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x09,0x80,data);
2408
2409 /* Write foreground and background queue */
2410 templ = sis_pci_read_host_bridge_u32(0x50);
2411
2412 if(SiS_Pr->ChipType == SIS_730) {
2413
2414 templ &= 0xfffff9ff;
2415 templ |= ((queuedata[i] & 0xc0) << 3);
2416
2417 } else {
2418
2419 templ &= 0xf0ffffff;
2420 if( (ModeNo <= 0x13) &&
2421 (SiS_Pr->ChipType == SIS_630) &&
2422 (SiS_Pr->ChipRevision >= 0x30) ) {
2423 templ |= 0x0b000000;
2424 } else {
2425 templ |= ((queuedata[i] & 0xf0) << 20);
2426 }
2427
2428 }
2429
2430 sis_pci_write_host_bridge_u32(0x50, templ);
2431 templ = sis_pci_read_host_bridge_u32(0xA0);
2432
2433 /* GUI grant timer (PCI config 0xA3) */
2434 if(SiS_Pr->ChipType == SIS_730) {
2435
2436 templ &= 0x00ffffff;
2437 datal = queuedata[i] << 8;
2438 templ |= (((datal & 0x0f00) | ((datal & 0x3000) >> 8)) << 20);
2439
2440 } else {
2441
2442 templ &= 0xf0ffffff;
2443 templ |= ((queuedata[i] & 0x0f) << 24);
2444
2445 }
2446
2447 sis_pci_write_host_bridge_u32(0xA0, templ);
2448 }
2449
2450 static void
2451 SiS_SetCRT1FIFO_310(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
2452 {
2453 unsigned short modeflag;
2454
2455 /* disable auto-threshold */
2456 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x3D,0xFE);
2457
2458 modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
2459
2460 SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,0xAE);
2461 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x09,0xF0);
2462 if(ModeNo > 0x13) {
2463 if(SiS_Pr->ChipType >= XGI_20) {
2464 SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,0x34);
2465 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x3D,0x01);
2466 } else if(SiS_Pr->ChipType >= SIS_661) {
2467 if(!(modeflag & HalfDCLK)) {
2468 SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,0x34);
2469 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x3D,0x01);
2470 }
2471 } else {
2472 if((!(modeflag & DoubleScanMode)) || (!(modeflag & HalfDCLK))) {
2473 SiS_SetReg(SiS_Pr->SiS_P3c4,0x08,0x34);
2474 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x3D,0x01);
2475 }
2476 }
2477 }
2478 }
2479
2480 /*********************************************/
2481 /* MODE REGISTERS */
2482 /*********************************************/
2483
2484 static void
2485 SiS_SetVCLKState(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
2486 unsigned short RefreshRateTableIndex, unsigned short ModeIdIndex)
2487 {
2488 unsigned short data = 0, VCLK = 0, index = 0;
2489
2490 if(ModeNo > 0x13) {
2491 if(SiS_Pr->UseCustomMode) {
2492 VCLK = SiS_Pr->CSRClock;
2493 } else {
2494 index = SiS_GetVCLK2Ptr(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
2495 VCLK = SiS_Pr->SiS_VCLKData[index].CLOCK;
2496 }
2497 }
2498
2499 if(SiS_Pr->ChipType < SIS_315H) {
2500 if(VCLK > 150) data |= 0x80;
2501 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x07,0x7B,data);
2502
2503 data = 0x00;
2504 if(VCLK >= 150) data |= 0x08;
2505 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x32,0xF7,data);
2506 } else if(SiS_Pr->ChipType < XGI_20) {
2507 if(VCLK >= 166) data |= 0x0c;
2508 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x32,0xf3,data);
2509
2510 if(VCLK >= 166) {
2511 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x1f,0xe7);
2512 }
2513 } else {
2514 if(VCLK >= 200) data |= 0x0c;
2515 if(SiS_Pr->ChipType == XGI_20) data &= ~0x04;
2516 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x32,0xf3,data);
2517 if(SiS_Pr->ChipType != XGI_20) {
2518 data = SiS_GetReg(SiS_Pr->SiS_P3c4,0x1f) & 0xe7;
2519 if(VCLK < 200) data |= 0x10;
2520 SiS_SetReg(SiS_Pr->SiS_P3c4,0x1f,data);
2521 }
2522 }
2523
2524 /* DAC speed */
2525 if(SiS_Pr->ChipType >= SIS_661) {
2526
2527 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x07,0xE8,0x10);
2528
2529 } else {
2530
2531 data = 0x03;
2532 if(VCLK >= 260) data = 0x00;
2533 else if(VCLK >= 160) data = 0x01;
2534 else if(VCLK >= 135) data = 0x02;
2535
2536 if(SiS_Pr->ChipType == SIS_540) {
2537 if((VCLK == 203) || (VCLK < 234)) data = 0x02;
2538 }
2539
2540 if(SiS_Pr->ChipType < SIS_315H) {
2541 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x07,0xFC,data);
2542 } else {
2543 if(SiS_Pr->ChipType > SIS_315PRO) {
2544 if(ModeNo > 0x13) data &= 0xfc;
2545 }
2546 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x07,0xF8,data);
2547 }
2548
2549 }
2550 }
2551
2552 static void
2553 SiS_SetCRT1ModeRegs(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
2554 unsigned short ModeIdIndex, unsigned short RRTI)
2555 {
2556 unsigned short data, infoflag = 0, modeflag;
2557 unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
2558 unsigned short data2, data3;
2559
2560 modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
2561
2562 if(SiS_Pr->UseCustomMode) {
2563 infoflag = SiS_Pr->CInfoFlag;
2564 } else {
2565 if(ModeNo > 0x13) {
2566 infoflag = SiS_Pr->SiS_RefIndex[RRTI].Ext_InfoFlag;
2567 }
2568 }
2569
2570 /* Disable DPMS */
2571 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x1F,0x3F);
2572
2573 data = 0;
2574 if(ModeNo > 0x13) {
2575 if(SiS_Pr->SiS_ModeType > ModeEGA) {
2576 data |= 0x02;
2577 data |= ((SiS_Pr->SiS_ModeType - ModeVGA) << 2);
2578 }
2579 if(infoflag & InterlaceMode) data |= 0x20;
2580 }
2581 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x06,0xC0,data);
2582
2583 if(SiS_Pr->ChipType != SIS_300) {
2584 data = 0;
2585 if(infoflag & InterlaceMode) {
2586 /* data = (Hsync / 8) - ((Htotal / 8) / 2) + 3 */
2587 int hrs = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x04) |
2588 ((SiS_GetReg(SiS_Pr->SiS_P3c4,0x0b) & 0xc0) << 2)) - 3;
2589 int hto = (SiS_GetReg(SiS_Pr->SiS_P3d4,0x00) |
2590 ((SiS_GetReg(SiS_Pr->SiS_P3c4,0x0b) & 0x03) << 8)) + 5;
2591 data = hrs - (hto >> 1) + 3;
2592 }
2593 SiS_SetReg(SiS_Pr->SiS_P3d4,0x19,data);
2594 SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x1a,0xFC,((data >> 8) & 0x03));
2595 }
2596
2597 if(modeflag & HalfDCLK) {
2598 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x01,0x08);
2599 }
2600
2601 data = 0;
2602 if(modeflag & LineCompareOff) data = 0x08;
2603 if(SiS_Pr->ChipType == SIS_300) {
2604 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0F,0xF7,data);
2605 } else {
2606 if(SiS_Pr->ChipType >= XGI_20) data |= 0x20;
2607 if(SiS_Pr->SiS_ModeType == ModeEGA) {
2608 if(ModeNo > 0x13) {
2609 data |= 0x40;
2610 }
2611 }
2612 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0F,0xB7,data);
2613 }
2614
2615 if(SiS_Pr->ChipType >= SIS_315H) {
2616 SiS_SetRegAND(SiS_Pr->SiS_P3c4,0x31,0xfb);
2617 }
2618
2619 if(SiS_Pr->ChipType == SIS_315PRO) {
2620
2621 data = SiS_Pr->SiS_SR15[(2 * 4) + SiS_Get310DRAMType(SiS_Pr)];
2622 if(SiS_Pr->SiS_ModeType == ModeText) {
2623 data &= 0xc7;
2624 } else {
2625 data2 = SiS_GetOffset(SiS_Pr, ModeNo, ModeIdIndex, RRTI) >> 1;
2626 if(infoflag & InterlaceMode) data2 >>= 1;
2627 data3 = SiS_GetColorDepth(SiS_Pr, ModeNo, ModeIdIndex) >> 1;
2628 if(data3) data2 /= data3;
2629 if(data2 >= 0x50) {
2630 data &= 0x0f;
2631 data |= 0x50;
2632 }
2633 }
2634 SiS_SetReg(SiS_Pr->SiS_P3c4,0x17,data);
2635
2636 } else if((SiS_Pr->ChipType == SIS_330) || (SiS_Pr->SiS_SysFlags & SF_760LFB)) {
2637
2638 data = SiS_Get310DRAMType(SiS_Pr);
2639 if(SiS_Pr->ChipType == SIS_330) {
2640 data = SiS_Pr->SiS_SR15[(2 * 4) + data];
2641 } else {
2642 if(SiS_Pr->SiS_ROMNew) data = ROMAddr[0xf6];
2643 else if(SiS_Pr->SiS_UseROM) data = ROMAddr[0x100 + data];
2644 else data = 0xba;
2645 }
2646 if(SiS_Pr->SiS_ModeType <= ModeEGA) {
2647 data &= 0xc7;
2648 } else {
2649 if(SiS_Pr->UseCustomMode) {
2650 data2 = SiS_Pr->CSRClock;
2651 } else {
2652 data2 = SiS_GetVCLK2Ptr(SiS_Pr, ModeNo, ModeIdIndex, RRTI);
2653 data2 = SiS_Pr->SiS_VCLKData[data2].CLOCK;
2654 }
2655
2656 data3 = SiS_GetColorDepth(SiS_Pr, ModeNo, ModeIdIndex) >> 1;
2657 if(data3) data2 *= data3;
2658
2659 data2 = ((unsigned int)(SiS_GetMCLK(SiS_Pr) * 1024)) / data2;
2660
2661 if(SiS_Pr->ChipType == SIS_330) {
2662 if(SiS_Pr->SiS_ModeType != Mode16Bpp) {
2663 if (data2 >= 0x19c) data = 0xba;
2664 else if(data2 >= 0x140) data = 0x7a;
2665 else if(data2 >= 0x101) data = 0x3a;
2666 else if(data2 >= 0xf5) data = 0x32;
2667 else if(data2 >= 0xe2) data = 0x2a;
2668 else if(data2 >= 0xc4) data = 0x22;
2669 else if(data2 >= 0xac) data = 0x1a;
2670 else if(data2 >= 0x9e) data = 0x12;
2671 else if(data2 >= 0x8e) data = 0x0a;
2672 else data = 0x02;
2673 } else {
2674 if(data2 >= 0x127) data = 0xba;
2675 else data = 0x7a;
2676 }
2677 } else { /* 76x+LFB */
2678 if (data2 >= 0x190) data = 0xba;
2679 else if(data2 >= 0xff) data = 0x7a;
2680 else if(data2 >= 0xd3) data = 0x3a;
2681 else if(data2 >= 0xa9) data = 0x1a;
2682 else if(data2 >= 0x93) data = 0x0a;
2683 else data = 0x02;
2684 }
2685 }
2686 SiS_SetReg(SiS_Pr->SiS_P3c4,0x17,data);
2687
2688 }
2689 /* XGI: Nothing. */
2690 /* TODO: Check SiS340 */
2691
2692 data = 0x60;
2693 if(SiS_Pr->SiS_ModeType != ModeText) {
2694 data ^= 0x60;
2695 if(SiS_Pr->SiS_ModeType != ModeEGA) {
2696 data ^= 0xA0;
2697 }
2698 }
2699 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x21,0x1F,data);
2700
2701 SiS_SetVCLKState(SiS_Pr, ModeNo, RRTI, ModeIdIndex);
2702
2703 if(((SiS_Pr->ChipType >= SIS_315H) && (SiS_Pr->ChipType < SIS_661)) ||
2704 (SiS_Pr->ChipType == XGI_40)) {
2705 if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) & 0x40) {
2706 SiS_SetReg(SiS_Pr->SiS_P3d4,0x52,0x2c);
2707 } else {
2708 SiS_SetReg(SiS_Pr->SiS_P3d4,0x52,0x6c);
2709 }
2710 } else if(SiS_Pr->ChipType == XGI_20) {
2711 if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) & 0x40) {
2712 SiS_SetReg(SiS_Pr->SiS_P3d4,0x52,0x33);
2713 } else {
2714 SiS_SetReg(SiS_Pr->SiS_P3d4,0x52,0x73);
2715 }
2716 SiS_SetReg(SiS_Pr->SiS_P3d4,0x51,0x02);
2717 }
2718 }
2719
2720 static void
2721 SiS_SetupDualChip(struct SiS_Private *SiS_Pr)
2722 {
2723 #if 0
2724 /* TODO: Find out about IOAddress2 */
2725 SISIOADDRESS P2_3c2 = SiS_Pr->IOAddress2 + 0x12;
2726 SISIOADDRESS P2_3c4 = SiS_Pr->IOAddress2 + 0x14;
2727 SISIOADDRESS P2_3ce = SiS_Pr->IOAddress2 + 0x1e;
2728 int i;
2729
2730 if((SiS_Pr->ChipRevision != 0) ||
2731 (!(SiS_GetReg(SiS_Pr->SiS_P3c4,0x3a) & 0x04)))
2732 return;
2733
2734 for(i = 0; i <= 4; i++) { /* SR00 - SR04 */
2735 SiS_SetReg(P2_3c4,i,SiS_GetReg(SiS_Pr->SiS_P3c4,i));
2736 }
2737 for(i = 0; i <= 8; i++) { /* GR00 - GR08 */
2738 SiS_SetReg(P2_3ce,i,SiS_GetReg(SiS_Pr->SiS_P3ce,i));
2739 }
2740 SiS_SetReg(P2_3c4,0x05,0x86);
2741 SiS_SetReg(P2_3c4,0x06,SiS_GetReg(SiS_Pr->SiS_P3c4,0x06)); /* SR06 */
2742 SiS_SetReg(P2_3c4,0x21,SiS_GetReg(SiS_Pr->SiS_P3c4,0x21)); /* SR21 */
2743 SiS_SetRegByte(P2_3c2,SiS_GetRegByte(SiS_Pr->SiS_P3cc)); /* MISC */
2744 SiS_SetReg(P2_3c4,0x05,0x00);
2745 #endif
2746 }
2747
2748 /*********************************************/
2749 /* LOAD DAC */
2750 /*********************************************/
2751
2752 static void
2753 SiS_WriteDAC(struct SiS_Private *SiS_Pr, SISIOADDRESS DACData, unsigned short shiftflag,
2754 unsigned short dl, unsigned short ah, unsigned short al, unsigned short dh)
2755 {
2756 unsigned short d1, d2, d3;
2757
2758 switch(dl) {
2759 case 0: d1 = dh; d2 = ah; d3 = al; break;
2760 case 1: d1 = ah; d2 = al; d3 = dh; break;
2761 default: d1 = al; d2 = dh; d3 = ah;
2762 }
2763 SiS_SetRegByte(DACData, (d1 << shiftflag));
2764 SiS_SetRegByte(DACData, (d2 << shiftflag));
2765 SiS_SetRegByte(DACData, (d3 << shiftflag));
2766 }
2767
2768 void
2769 SiS_LoadDAC(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
2770 {
2771 unsigned short data, data2, time, i, j, k, m, n, o;
2772 unsigned short si, di, bx, sf;
2773 SISIOADDRESS DACAddr, DACData;
2774 const unsigned char *table = NULL;
2775
2776 data = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex) & DACInfoFlag;
2777
2778 j = time = 64;
2779 if(data == 0x00) table = SiS_MDA_DAC;
2780 else if(data == 0x08) table = SiS_CGA_DAC;
2781 else if(data == 0x10) table = SiS_EGA_DAC;
2782 else if(data == 0x18) {
2783 j = 16;
2784 time = 256;
2785 table = SiS_VGA_DAC;
2786 }
2787
2788 if( ( (SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) && /* 301B-DH LCD */
2789 (SiS_Pr->SiS_VBType & VB_NoLCD) ) ||
2790 (SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) || /* LCDA */
2791 (!(SiS_Pr->SiS_SetFlag & ProgrammingCRT2)) ) { /* Programming CRT1 */
2792 SiS_SetRegByte(SiS_Pr->SiS_P3c6,0xFF);
2793 DACAddr = SiS_Pr->SiS_P3c8;
2794 DACData = SiS_Pr->SiS_P3c9;
2795 sf = 0;
2796 } else {
2797 DACAddr = SiS_Pr->SiS_Part5Port;
2798 DACData = SiS_Pr->SiS_Part5Port + 1;
2799 sf = 2;
2800 }
2801
2802 SiS_SetRegByte(DACAddr,0x00);
2803
2804 for(i = 0; i < j; i++) {
2805 data = table[i];
2806 for(k = 0; k < 3; k++) {
2807 data2 = 0;
2808 if(data & 0x01) data2 += 0x2A;
2809 if(data & 0x02) data2 += 0x15;
2810 SiS_SetRegByte(DACData, (data2 << sf));
2811 data >>= 2;
2812 }
2813 }
2814
2815 if(time == 256) {
2816 for(i = 16; i < 32; i++) {
2817 data = table[i] << sf;
2818 for(k = 0; k < 3; k++) SiS_SetRegByte(DACData, data);
2819 }
2820 si = 32;
2821 for(m = 0; m < 9; m++) {
2822 di = si;
2823 bx = si + 4;
2824 for(n = 0; n < 3; n++) {
2825 for(o = 0; o < 5; o++) {
2826 SiS_WriteDAC(SiS_Pr, DACData, sf, n, table[di], table[bx], table[si]);
2827 si++;
2828 }
2829 si -= 2;
2830 for(o = 0; o < 3; o++) {
2831 SiS_WriteDAC(SiS_Pr, DACData, sf, n, table[di], table[si], table[bx]);
2832 si--;
2833 }
2834 } /* for n < 3 */
2835 si += 5;
2836 } /* for m < 9 */
2837 }
2838 }
2839
2840 /*********************************************/
2841 /* SET CRT1 REGISTER GROUP */
2842 /*********************************************/
2843
2844 static void
2845 SiS_SetCRT1Group(struct SiS_Private *SiS_Pr, unsigned short ModeNo, unsigned short ModeIdIndex)
2846 {
2847 unsigned short StandTableIndex, RefreshRateTableIndex;
2848
2849 SiS_Pr->SiS_CRT1Mode = ModeNo;
2850
2851 StandTableIndex = SiS_GetModePtr(SiS_Pr, ModeNo, ModeIdIndex);
2852
2853 if(SiS_Pr->SiS_SetFlag & LowModeTests) {
2854 if(SiS_Pr->SiS_VBInfo & (SetSimuScanMode | SwitchCRT2)) {
2855 SiS_DisableBridge(SiS_Pr);
2856 }
2857 }
2858
2859 SiS_ResetSegmentRegisters(SiS_Pr);
2860
2861 SiS_SetSeqRegs(SiS_Pr, StandTableIndex);
2862 SiS_SetMiscRegs(SiS_Pr, StandTableIndex);
2863 SiS_SetCRTCRegs(SiS_Pr, StandTableIndex);
2864 SiS_SetATTRegs(SiS_Pr, StandTableIndex);
2865 SiS_SetGRCRegs(SiS_Pr, StandTableIndex);
2866 SiS_ClearExt1Regs(SiS_Pr, ModeNo);
2867 SiS_ResetCRT1VCLK(SiS_Pr);
2868
2869 SiS_Pr->SiS_SelectCRT2Rate = 0;
2870 SiS_Pr->SiS_SetFlag &= (~ProgrammingCRT2);
2871
2872 xf86DrvMsgVerb(0, X_PROBED, 4, "(init: VBType=0x%04x, VBInfo=0x%04x)\n",
2873 SiS_Pr->SiS_VBType, SiS_Pr->SiS_VBInfo);
2874
2875 if(SiS_Pr->SiS_VBInfo & SetSimuScanMode) {
2876 if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) {
2877 SiS_Pr->SiS_SetFlag |= ProgrammingCRT2;
2878 }
2879 }
2880
2881 if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
2882 SiS_Pr->SiS_SetFlag |= ProgrammingCRT2;
2883 }
2884
2885 RefreshRateTableIndex = SiS_GetRatePtr(SiS_Pr, ModeNo, ModeIdIndex);
2886
2887 if(!(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA)) {
2888 SiS_Pr->SiS_SetFlag &= ~ProgrammingCRT2;
2889 }
2890
2891 if(RefreshRateTableIndex != 0xFFFF) {
2892 SiS_SetCRT1Sync(SiS_Pr, RefreshRateTableIndex);
2893 SiS_SetCRT1CRTC(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
2894 SiS_SetCRT1Offset(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
2895 SiS_SetCRT1VCLK(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
2896 }
2897
2898 switch(SiS_Pr->ChipType) {
2899 case SIS_300:
2900 SiS_SetCRT1FIFO_300(SiS_Pr, ModeNo, RefreshRateTableIndex);
2901 break;
2902 case SIS_540:
2903 case SIS_630:
2904 case SIS_730:
2905 SiS_SetCRT1FIFO_630(SiS_Pr, ModeNo, RefreshRateTableIndex);
2906 break;
2907 default:
2908 if(SiS_Pr->ChipType == XGI_20) {
2909 unsigned char sr2b = 0, sr2c = 0;
2910 switch(ModeNo) {
2911 case 0x00:
2912 case 0x01: sr2b = 0x4e; sr2c = 0xe9; break;
2913 case 0x04:
2914 case 0x05:
2915 case 0x0d: sr2b = 0x1b; sr2c = 0xe3; break;
2916 }
2917 if(sr2b) {
2918 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2b,sr2b);
2919 SiS_SetReg(SiS_Pr->SiS_P3c4,0x2c,sr2c);
2920 SiS_SetRegByte(SiS_Pr->SiS_P3c2,(SiS_GetRegByte(SiS_Pr->SiS_P3cc) | 0x0c));
2921 }
2922 }
2923 SiS_SetCRT1FIFO_310(SiS_Pr, ModeNo, ModeIdIndex);
2924 break;
2925 }
2926
2927 SiS_SetCRT1ModeRegs(SiS_Pr, ModeNo, ModeIdIndex, RefreshRateTableIndex);
2928
2929 if(SiS_Pr->ChipType == XGI_40) {
2930 SiS_SetupDualChip(SiS_Pr);
2931 }
2932
2933 SiS_LoadDAC(SiS_Pr, ModeNo, ModeIdIndex);
2934
2935 if(!(SiS_Pr->SiS_VBInfo & (SetSimuScanMode | SwitchCRT2 | SetCRT2ToLCDA))) {
2936 SiS_WaitRetrace1(SiS_Pr);
2937 SiS_DisplayOn(SiS_Pr);
2938 }
2939 }
2940
2941 /*********************************************/
2942 /* HELPER: VIDEO BRIDGE PROG CLK */
2943 /*********************************************/
2944
2945 static void
2946 SiS_InitVB(struct SiS_Private *SiS_Pr)
2947 {
2948 unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
2949
2950 SiS_Pr->Init_P4_0E = 0;
2951 if(SiS_Pr->SiS_ROMNew) {
2952 SiS_Pr->Init_P4_0E = ROMAddr[0x82];
2953 } else if(SiS_Pr->ChipType >= XGI_40) {
2954 if(SiS_Pr->SiS_XGIROM) {
2955 SiS_Pr->Init_P4_0E = ROMAddr[0x80];
2956 }
2957 }
2958 }
2959
2960 static void
2961 SiS_ResetVB(struct SiS_Private *SiS_Pr)
2962 {
2963 unsigned char *ROMAddr = SiS_Pr->VirtualRomBase;
2964 unsigned short temp;
2965
2966 /* VB programming clock */
2967 if(SiS_Pr->SiS_UseROM) {
2968 if(SiS_Pr->ChipType < SIS_330) {
2969 temp = ROMAddr[VB310Data_1_2_Offset] | 0x40;
2970 if(SiS_Pr->SiS_ROMNew) temp = ROMAddr[0x80] | 0x40;
2971 SiS_SetReg(SiS_Pr->SiS_Part1Port,0x02,temp);
2972 } else if(SiS_Pr->ChipType >= SIS_661 && SiS_Pr->ChipType < XGI_20) {
2973 temp = ROMAddr[0x7e] | 0x40;
2974 if(SiS_Pr->SiS_ROMNew) temp = ROMAddr[0x80] | 0x40;
2975 SiS_SetReg(SiS_Pr->SiS_Part1Port,0x02,temp);
2976 }
2977 } else if(SiS_Pr->ChipType >= XGI_40) {
2978 temp = 0x40;
2979 if(SiS_Pr->SiS_XGIROM) temp |= ROMAddr[0x7e];
2980 /* Can we do this on any chipset? */
2981 SiS_SetReg(SiS_Pr->SiS_Part1Port,0x02,temp);
2982 }
2983 }
2984
2985 /*********************************************/
2986 /* HELPER: SET VIDEO/CAPTURE REGISTERS */
2987 /*********************************************/
2988
2989 static void
2990 SiS_StrangeStuff(struct SiS_Private *SiS_Pr)
2991 {
2992 /* SiS65x and XGI set up some sort of "lock mode" for text
2993 * which locks CRT2 in some way to CRT1 timing. Disable
2994 * this here.
2995 */
2996 if((IS_SIS651) || (IS_SISM650) ||
2997 SiS_Pr->ChipType == SIS_340 ||
2998 SiS_Pr->ChipType == XGI_40) {
2999 SiS_SetReg(SiS_Pr->SiS_VidCapt, 0x3f, 0x00); /* Fiddle with capture regs */
3000 SiS_SetReg(SiS_Pr->SiS_VidCapt, 0x00, 0x00);
3001 SiS_SetReg(SiS_Pr->SiS_VidPlay, 0x00, 0x86); /* (BIOS does NOT unlock) */
3002 SiS_SetRegAND(SiS_Pr->SiS_VidPlay, 0x30, 0xfe); /* Fiddle with video regs */
3003 SiS_SetRegAND(SiS_Pr->SiS_VidPlay, 0x3f, 0xef);
3004 }
3005 /* !!! This does not support modes < 0x13 !!! */
3006 }
3007
3008 /*********************************************/
3009 /* HELPER: SET AGP TIMING FOR SiS760 */
3010 /*********************************************/
3011
3012 static void
3013 SiS_Handle760(struct SiS_Private *SiS_Pr)
3014 {
3015 unsigned int somebase;
3016 unsigned char temp1, temp2, temp3;
3017
3018 if( (SiS_Pr->ChipType != SIS_760) ||
3019 ((SiS_GetReg(SiS_Pr->SiS_P3d4, 0x5c) & 0xf8) != 0x80) ||
3020 (!(SiS_Pr->SiS_SysFlags & SF_760LFB)) ||
3021 (!(SiS_Pr->SiS_SysFlags & SF_760UMA)) )
3022 return;
3023
3024 somebase = sis_pci_read_device_u32(2, 0x74);
3025 somebase &= 0xffff;
3026
3027 if(somebase == 0) return;
3028
3029 temp3 = SiS_GetRegByte((somebase + 0x85)) & 0xb7;
3030
3031 if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x31) & 0x40) {
3032 temp1 = 0x21;
3033 temp2 = 0x03;
3034 temp3 |= 0x08;
3035 } else {
3036 temp1 = 0x25;
3037 temp2 = 0x0b;
3038 }
3039
3040 sis_pci_write_host_bridge_u8(0x7e, temp1);
3041 sis_pci_write_host_bridge_u8(0x8d, temp2);
3042
3043 SiS_SetRegByte((somebase + 0x85), temp3);
3044 }
3045
3046 /*********************************************/
3047 /* X.org/XFree86: SET SCREEN PITCH */
3048 /*********************************************/
3049
3050 static void
3051 SiS_SetPitchCRT1(struct SiS_Private *SiS_Pr, ScrnInfoPtr pScrn)
3052 {
3053 SISPtr pSiS = SISPTR(pScrn);
3054 unsigned short HDisplay = pSiS->scrnPitch >> 3;
3055
3056 SiS_SetReg(SiS_Pr->SiS_P3d4,0x13,(HDisplay & 0xFF));
3057 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0E,0xF0,(HDisplay >> 8));
3058 }
3059
3060 static void
3061 SiS_SetPitchCRT2(struct SiS_Private *SiS_Pr, ScrnInfoPtr pScrn)
3062 {
3063 SISPtr pSiS = SISPTR(pScrn);
3064 unsigned short HDisplay = pSiS->scrnPitch2 >> 3;
3065
3066 /* Unlock CRT2 */
3067 if(pSiS->VGAEngine == SIS_315_VGA)
3068 SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x2F, 0x01);
3069 else
3070 SiS_SetRegOR(SiS_Pr->SiS_Part1Port,0x24, 0x01);
3071
3072 SiS_SetReg(SiS_Pr->SiS_Part1Port,0x07,(HDisplay & 0xFF));
3073 SiS_SetRegANDOR(SiS_Pr->SiS_Part1Port,0x09,0xF0,(HDisplay >> 8));
3074 }
3075
3076 static void
3077 SiS_SetPitch(struct SiS_Private *SiS_Pr, ScrnInfoPtr pScrn)
3078 {
3079 SISPtr pSiS = SISPTR(pScrn);
3080 BOOLEAN isslavemode = FALSE;
3081
3082 if( (pSiS->VBFlags2 & VB2_VIDEOBRIDGE) &&
3083 ( ((pSiS->VGAEngine == SIS_300_VGA) &&
3084 (SiS_GetReg(SiS_Pr->SiS_Part1Port,0x00) & 0xa0) == 0x20) ||
3085 ((pSiS->VGAEngine == SIS_315_VGA) &&
3086 (SiS_GetReg(SiS_Pr->SiS_Part1Port,0x00) & 0x50) == 0x10) ) ) {
3087 isslavemode = TRUE;
3088 }
3089
3090 /* We need to set pitch for CRT1 if bridge is in slave mode, too */
3091 if((pSiS->VBFlags & DISPTYPE_DISP1) || (isslavemode)) {
3092 SiS_SetPitchCRT1(SiS_Pr, pScrn);
3093 }
3094 /* We must not set the pitch for CRT2 if bridge is in slave mode */
3095 if((pSiS->VBFlags & DISPTYPE_DISP2) && (!isslavemode)) {
3096 SiS_SetPitchCRT2(SiS_Pr, pScrn);
3097 }
3098 }
3099
3100 /*********************************************/
3101 /* SiSSetMode() */
3102 /*********************************************/
3103
3104 /* We need pScrn for setting the pitch correctly */
3105 BOOLEAN
3106 SiSSetMode(struct SiS_Private *SiS_Pr, ScrnInfoPtr pScrn, unsigned short ModeNo, BOOLEAN dosetpitch)
3107 {
3108 SISIOADDRESS BaseAddr = SiS_Pr->IOAddress;
3109 unsigned short RealModeNo, ModeIdIndex;
3110 unsigned char backupreg = 0;
3111
3112 SiS_Pr->SiS_flag_clearbuffer = 0;
3113
3114 if(SiS_Pr->UseCustomMode) {
3115 ModeNo = 0xfe;
3116 } else {
3117 ModeNo &= 0x7f;
3118 }
3119
3120 /* Don't use FSTN mode for CRT1 */
3121 RealModeNo = ModeNo;
3122 if(ModeNo == 0x5b) ModeNo = 0x56;
3123
3124 SiSInitPtr(SiS_Pr);
3125 SiSRegInit(SiS_Pr, BaseAddr);
3126 SiS_GetSysFlags(SiS_Pr);
3127
3128 SiS_Pr->SiS_VGAINFO = 0x11;
3129 #if (defined(i386) || defined(__i386) || defined(__i386__) || defined(__AMD64__) || defined(__amd64__) || defined(__x86_64__))
3130 if(pScrn) SiS_Pr->SiS_VGAINFO = SiS_GetSetBIOSScratch(pScrn, 0x489, 0xff);
3131 #endif
3132
3133 SiS_SetReg(SiS_Pr->SiS_P3c4,0x05,0x86);
3134
3135 SiSInitPCIetc(SiS_Pr);
3136 SiSSetLVDSetc(SiS_Pr);
3137 SiSDetermineROMUsage(SiS_Pr);
3138
3139 SiS_UnLockCRT2(SiS_Pr);
3140
3141 if(!SiS_Pr->UseCustomMode) {
3142 if(!(SiS_SearchModeID(SiS_Pr, &ModeNo, &ModeIdIndex))) return FALSE;
3143 } else {
3144 ModeIdIndex = 0;
3145 }
3146
3147 SiS_GetVBType(SiS_Pr);
3148
3149 /* Init/restore some VB registers */
3150 SiS_InitVB(SiS_Pr);
3151 if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
3152 if(SiS_Pr->ChipType >= SIS_315H) {
3153 SiS_ResetVB(SiS_Pr);
3154 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x32,0x10);
3155 SiS_SetRegOR(SiS_Pr->SiS_Part2Port,0x00,0x0c);
3156 backupreg = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
3157 } else {
3158 backupreg = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35);
3159 }
3160 }
3161
3162 /* Get VB information (connectors, connected devices) */
3163 SiS_GetVBInfo(SiS_Pr, ModeNo, ModeIdIndex, (SiS_Pr->UseCustomMode) ? 0 : 1);
3164 SiS_SetYPbPr(SiS_Pr);
3165 SiS_SetTVMode(SiS_Pr, ModeNo, ModeIdIndex);
3166 SiS_GetLCDResInfo(SiS_Pr, ModeNo, ModeIdIndex);
3167 SiS_SetLowModeTest(SiS_Pr, ModeNo);
3168
3169 SiS_OpenCRTC(SiS_Pr);
3170
3171 if(SiS_Pr->UseCustomMode) {
3172 SiS_Pr->CRT1UsesCustomMode = TRUE;
3173 SiS_Pr->CSRClock_CRT1 = SiS_Pr->CSRClock;
3174 SiS_Pr->CModeFlag_CRT1 = SiS_Pr->CModeFlag;
3175 } else {
3176 SiS_Pr->CRT1UsesCustomMode = FALSE;
3177 }
3178
3179 /* Set mode on CRT1 */
3180 if( (SiS_Pr->SiS_VBInfo & (SetSimuScanMode | SetCRT2ToLCDA)) ||
3181 (!(SiS_Pr->SiS_VBInfo & SwitchCRT2)) ) {
3182 SiS_SetCRT1Group(SiS_Pr, ModeNo, ModeIdIndex);
3183 }
3184
3185 /* Set mode on CRT2 */
3186 if(SiS_Pr->SiS_VBInfo & (SetSimuScanMode | SwitchCRT2 | SetCRT2ToLCDA)) {
3187 if( (SiS_Pr->SiS_VBType & VB_SISVB) ||
3188 (SiS_Pr->SiS_IF_DEF_LVDS == 1) ||
3189 (SiS_Pr->SiS_IF_DEF_CH70xx != 0) ||
3190 (SiS_Pr->SiS_IF_DEF_TRUMPION != 0) ) {
3191 SiS_SetCRT2Group(SiS_Pr, RealModeNo);
3192 }
3193 }
3194
3195 SiS_HandleCRT1(SiS_Pr);
3196
3197 SiS_StrangeStuff(SiS_Pr);
3198
3199 SiS_DisplayOn(SiS_Pr);
3200 SiS_SetRegByte(SiS_Pr->SiS_P3c6,0xFF);
3201
3202 if(SiS_Pr->ChipType >= SIS_315H) {
3203 if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
3204 if(!(SiS_IsDualEdge(SiS_Pr))) {
3205 SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x13,0xfb);
3206 }
3207 }
3208 }
3209
3210 if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
3211 if(SiS_Pr->ChipType >= SIS_315H) {
3212 if(!SiS_Pr->SiS_ROMNew) {
3213 if(SiS_IsVAMode(SiS_Pr)) {
3214 SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x35,0x01);
3215 } else {
3216 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x35,0xFE);
3217 }
3218 }
3219
3220 SiS_SetReg(SiS_Pr->SiS_P3d4,0x38,backupreg);
3221
3222 if((IS_SIS650) && (SiS_GetReg(SiS_Pr->SiS_P3d4,0x30) & 0xfc)) {
3223 if((ModeNo == 0x03) || (ModeNo == 0x10)) {
3224 SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x51,0x80);
3225 SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x56,0x08);
3226 }
3227 }
3228
3229 if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x30) & SetCRT2ToLCD) {
3230 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x38,0xfc);
3231 }
3232 } else if((SiS_Pr->ChipType == SIS_630) ||
3233 (SiS_Pr->ChipType == SIS_730)) {
3234 SiS_SetReg(SiS_Pr->SiS_P3d4,0x35,backupreg);
3235 }
3236 }
3237
3238 if(pScrn) {
3239 /* SetPitch: Adapt to virtual size & position */
3240 if((ModeNo > 0x13) && (dosetpitch)) {
3241 SiS_SetPitch(SiS_Pr, pScrn);
3242 }
3243
3244 /* Backup/Set ModeNo in BIOS scratch area */
3245 SiS_GetSetModeID(pScrn, ModeNo);
3246 }
3247
3248 SiS_CloseCRTC(SiS_Pr);
3249
3250 SiS_Handle760(SiS_Pr);
3251
3252 return TRUE;
3253 }
3254
3255 /*********************************************/
3256 /* X.org/XFree86: SiSBIOSSetMode() */
3257 /* for non-Dual-Head mode */
3258 /*********************************************/
3259
3260 BOOLEAN
3261 SiSBIOSSetMode(struct SiS_Private *SiS_Pr, ScrnInfoPtr pScrn,
3262 DisplayModePtr mode, BOOLEAN IsCustom)
3263 {
3264 SISPtr pSiS = SISPTR(pScrn);
3265 unsigned short ModeNo = 0;
3266
3267 SiS_Pr->UseCustomMode = FALSE;
3268
3269 if((IsCustom) && (SiS_CheckBuildCustomMode(pScrn, mode, pSiS->VBFlags))) {
3270
3271 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 3, "Setting custom mode %dx%d\n",
3272 SiS_Pr->CHDisplay,
3273 (mode->Flags & V_INTERLACE ? SiS_Pr->CVDisplay * 2 :
3274 (mode->Flags & V_DBLSCAN ? SiS_Pr->CVDisplay / 2 :
3275 SiS_Pr->CVDisplay)));
3276
3277 } else {
3278
3279 /* Don't need vbflags here; checks done earlier */
3280 ModeNo = SiS_GetModeNumber(pScrn, mode, pSiS->VBFlags);
3281 if(!ModeNo) return FALSE;
3282
3283 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 3, "Setting standard mode 0x%x\n", ModeNo);
3284
3285 }
3286
3287 return(SiSSetMode(SiS_Pr, pScrn, ModeNo, TRUE));
3288 }
3289
3290 /*********************************************/
3291 /* X.org/XFree86: SiSBIOSSetModeCRT2() */
3292 /* for Dual-Head modes */
3293 /*********************************************/
3294
3295 BOOLEAN
3296 SiSBIOSSetModeCRT2(struct SiS_Private *SiS_Pr, ScrnInfoPtr pScrn,
3297 DisplayModePtr mode, BOOLEAN IsCustom)
3298 {
3299 SISIOADDRESS BaseAddr = SiS_Pr->IOAddress;
3300 SISPtr pSiS = SISPTR(pScrn);
3301 #ifdef SISDUALHEAD
3302 SISEntPtr pSiSEnt = pSiS->entityPrivate;
3303 #endif
3304 unsigned short ModeIdIndex;
3305 unsigned short ModeNo = 0;
3306 unsigned char backupreg = 0;
3307
3308 SiS_Pr->UseCustomMode = FALSE;
3309
3310 /* Remember: Custom modes for CRT2 are ONLY supported
3311 * -) on the 30x/B/C, and
3312 * -) if CRT2 is LCD or VGA, or CRT1 is LCDA
3313 */
3314
3315 if((IsCustom) && (SiS_CheckBuildCustomMode(pScrn, mode, pSiS->VBFlags))) {
3316
3317 ModeNo = 0xfe;
3318
3319 } else {
3320
3321 ModeNo = SiS_GetModeNumber(pScrn, mode, pSiS->VBFlags);
3322 if(!ModeNo) return FALSE;
3323
3324 }
3325
3326 SiSRegInit(SiS_Pr, BaseAddr);
3327 SiSInitPtr(SiS_Pr);
3328 SiS_GetSysFlags(SiS_Pr);
3329 #if defined(i386) || defined(__i386) || defined(__i386__) || defined(__AMD64__) || defined(__amd64__) || defined(__x86_64__)
3330 SiS_Pr->SiS_VGAINFO = SiS_GetSetBIOSScratch(pScrn, 0x489, 0xff);
3331 #else
3332 SiS_Pr->SiS_VGAINFO = 0x11;
3333 #endif
3334
3335 SiS_SetReg(SiS_Pr->SiS_P3c4,0x05,0x86);
3336
3337 SiSInitPCIetc(SiS_Pr);
3338 SiSSetLVDSetc(SiS_Pr);
3339 SiSDetermineROMUsage(SiS_Pr);
3340
3341 /* Save mode info so we can set it from within SetMode for CRT1 */
3342 #ifdef SISDUALHEAD
3343 if(pSiS->DualHeadMode) {
3344 pSiSEnt->CRT2ModeNo = ModeNo;
3345 pSiSEnt->CRT2DMode = mode;
3346 pSiSEnt->CRT2IsCustom = IsCustom;
3347 pSiSEnt->CRT2CR30 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x30);
3348 pSiSEnt->CRT2CR31 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x31);
3349 pSiSEnt->CRT2CR35 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35);
3350 pSiSEnt->CRT2CR38 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
3351 #if 0
3352 /* We can't set CRT2 mode before CRT1 mode is set - says who...? */
3353 if(pSiSEnt->CRT1ModeNo == -1) {
3354 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 3,
3355 "Setting CRT2 mode delayed until after setting CRT1 mode\n");
3356 return TRUE;
3357 }
3358 #endif
3359 pSiSEnt->CRT2ModeSet = TRUE;
3360 }
3361 #endif
3362
3363 if(SiS_Pr->UseCustomMode) {
3364
3365 unsigned short temptemp = SiS_Pr->CVDisplay;
3366
3367 if(SiS_Pr->CModeFlag & DoubleScanMode) temptemp >>= 1;
3368 else if(SiS_Pr->CInfoFlag & InterlaceMode) temptemp <<= 1;
3369
3370 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 3,
3371 "Setting custom mode %dx%d on CRT2\n",
3372 SiS_Pr->CHDisplay, temptemp);
3373
3374 } else {
3375
3376 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 3,
3377 "Setting standard mode 0x%x on CRT2\n", ModeNo);
3378
3379 }
3380
3381 SiS_UnLockCRT2(SiS_Pr);
3382
3383 if(!SiS_Pr->UseCustomMode) {
3384 if(!(SiS_SearchModeID(SiS_Pr, &ModeNo, &ModeIdIndex))) return FALSE;
3385 } else {
3386 ModeIdIndex = 0;
3387 }
3388
3389 SiS_GetVBType(SiS_Pr);
3390
3391 SiS_InitVB(SiS_Pr);
3392 if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
3393 if(SiS_Pr->ChipType >= SIS_315H) {
3394 SiS_ResetVB(SiS_Pr);
3395 SiS_SetRegOR(SiS_Pr->SiS_P3c4,0x32,0x10);
3396 SiS_SetRegOR(SiS_Pr->SiS_Part2Port,0x00,0x0c);
3397 backupreg = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
3398 } else {
3399 backupreg = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35);
3400 }
3401 }
3402
3403 /* Get VB information (connectors, connected devices) */
3404 if(!SiS_Pr->UseCustomMode) {
3405 SiS_GetVBInfo(SiS_Pr, ModeNo, ModeIdIndex, 1);
3406 } else {
3407 /* If this is a custom mode, we don't check the modeflag for CRT2Mode */
3408 SiS_GetVBInfo(SiS_Pr, ModeNo, ModeIdIndex, 0);
3409 }
3410 SiS_SetYPbPr(SiS_Pr);
3411 SiS_SetTVMode(SiS_Pr, ModeNo, ModeIdIndex);
3412 SiS_GetLCDResInfo(SiS_Pr, ModeNo, ModeIdIndex);
3413 SiS_SetLowModeTest(SiS_Pr, ModeNo);
3414
3415 SiS_ResetSegmentRegisters(SiS_Pr);
3416
3417 /* Set mode on CRT2 */
3418 if( (SiS_Pr->SiS_VBType & VB_SISVB) ||
3419 (SiS_Pr->SiS_IF_DEF_LVDS == 1) ||
3420 (SiS_Pr->SiS_IF_DEF_CH70xx != 0) ||
3421 (SiS_Pr->SiS_IF_DEF_TRUMPION != 0) ) {
3422 SiS_SetCRT2Group(SiS_Pr, ModeNo);
3423 }
3424
3425 SiS_StrangeStuff(SiS_Pr);
3426
3427 SiS_DisplayOn(SiS_Pr);
3428 SiS_SetRegByte(SiS_Pr->SiS_P3c6,0xFF);
3429
3430 if(SiS_Pr->ChipType >= SIS_315H) {
3431 if(SiS_Pr->SiS_IF_DEF_LVDS == 1) {
3432 if(!(SiS_IsDualEdge(SiS_Pr))) {
3433 SiS_SetRegAND(SiS_Pr->SiS_Part1Port,0x13,0xfb);
3434 }
3435 }
3436 }
3437
3438 if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
3439 if(SiS_Pr->ChipType >= SIS_315H) {
3440 if(!SiS_Pr->SiS_ROMNew) {
3441 if(SiS_IsVAMode(SiS_Pr)) {
3442 SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x35,0x01);
3443 } else {
3444 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x35,0xFE);
3445 }
3446 }
3447
3448 SiS_SetReg(SiS_Pr->SiS_P3d4,0x38,backupreg);
3449
3450 if(SiS_GetReg(SiS_Pr->SiS_P3d4,0x30) & SetCRT2ToLCD) {
3451 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x38,0xfc);
3452 }
3453 } else if((SiS_Pr->ChipType == SIS_630) ||
3454 (SiS_Pr->ChipType == SIS_730)) {
3455 SiS_SetReg(SiS_Pr->SiS_P3d4,0x35,backupreg);
3456 }
3457 }
3458
3459 /* SetPitch: Adapt to virtual size & position */
3460 SiS_SetPitchCRT2(SiS_Pr, pScrn);
3461
3462 SiS_Handle760(SiS_Pr);
3463
3464 return TRUE;
3465 }
3466
3467 /*********************************************/
3468 /* X.org/XFree86: SiSBIOSSetModeCRT1() */
3469 /* for Dual-Head modes */
3470 /*********************************************/
3471
3472 BOOLEAN
3473 SiSBIOSSetModeCRT1(struct SiS_Private *SiS_Pr, ScrnInfoPtr pScrn,
3474 DisplayModePtr mode, BOOLEAN IsCustom)
3475 {
3476 SISIOADDRESS BaseAddr = SiS_Pr->IOAddress;
3477 SISPtr pSiS = SISPTR(pScrn);
3478 unsigned short ModeIdIndex, ModeNo = 0;
3479 unsigned char backupreg = 0;
3480 #ifdef SISDUALHEAD
3481 SISEntPtr pSiSEnt = pSiS->entityPrivate;
3482 unsigned char backupcr30, backupcr31, backupcr38, backupcr35, backupp40d=0;
3483 BOOLEAN backupcustom;
3484 #endif
3485
3486 SiS_Pr->UseCustomMode = FALSE;
3487
3488 if((IsCustom) && (SiS_CheckBuildCustomMode(pScrn, mode, pSiS->VBFlags))) {
3489
3490 unsigned short temptemp = SiS_Pr->CVDisplay;
3491
3492 if(SiS_Pr->CModeFlag & DoubleScanMode) temptemp >>= 1;
3493 else if(SiS_Pr->CInfoFlag & InterlaceMode) temptemp <<= 1;
3494
3495 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 3,
3496 "Setting custom mode %dx%d on CRT1\n",
3497 SiS_Pr->CHDisplay, temptemp);
3498 ModeNo = 0xfe;
3499
3500 } else {
3501
3502 ModeNo = SiS_GetModeNumber(pScrn, mode, 0); /* don't give VBFlags */
3503 if(!ModeNo) return FALSE;
3504
3505 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 3,
3506 "Setting standard mode 0x%x on CRT1\n", ModeNo);
3507 }
3508
3509 SiSInitPtr(SiS_Pr);
3510 SiSRegInit(SiS_Pr, BaseAddr);
3511 SiS_GetSysFlags(SiS_Pr);
3512 #if defined(i386) || defined(__i386) || defined(__i386__) || defined(__AMD64__) || defined(__amd64__) || defined(__x86_64__)
3513 SiS_Pr->SiS_VGAINFO = SiS_GetSetBIOSScratch(pScrn, 0x489, 0xff);
3514 #else
3515 SiS_Pr->SiS_VGAINFO = 0x11;
3516 #endif
3517
3518 SiS_SetReg(SiS_Pr->SiS_P3c4,0x05,0x86);
3519
3520 SiSInitPCIetc(SiS_Pr);
3521 SiSSetLVDSetc(SiS_Pr);
3522 SiSDetermineROMUsage(SiS_Pr);
3523
3524 SiS_UnLockCRT2(SiS_Pr);
3525
3526 if(!SiS_Pr->UseCustomMode) {
3527 if(!(SiS_SearchModeID(SiS_Pr, &ModeNo, &ModeIdIndex))) return FALSE;
3528 } else {
3529 ModeIdIndex = 0;
3530 }
3531
3532 /* Determine VBType */
3533 SiS_GetVBType(SiS_Pr);
3534
3535 SiS_InitVB(SiS_Pr);
3536 if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
3537 if(SiS_Pr->ChipType >= SIS_315H) {
3538 backupreg = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
3539 } else {
3540 backupreg = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35);
3541 }
3542 }
3543
3544 /* Get VB information (connectors, connected devices) */
3545 /* (We don't care if the current mode is a CRT2 mode) */
3546 SiS_GetVBInfo(SiS_Pr, ModeNo, ModeIdIndex, 0);
3547 SiS_SetYPbPr(SiS_Pr);
3548 SiS_SetTVMode(SiS_Pr, ModeNo, ModeIdIndex);
3549 SiS_GetLCDResInfo(SiS_Pr, ModeNo, ModeIdIndex);
3550 SiS_SetLowModeTest(SiS_Pr, ModeNo);
3551
3552 SiS_OpenCRTC(SiS_Pr);
3553
3554 /* Set mode on CRT1 */
3555 SiS_SetCRT1Group(SiS_Pr, ModeNo, ModeIdIndex);
3556 if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
3557 SiS_SetCRT2Group(SiS_Pr, ModeNo);
3558 }
3559
3560 /* SetPitch: Adapt to virtual size & position */
3561 SiS_SetPitchCRT1(SiS_Pr, pScrn);
3562
3563 SiS_HandleCRT1(SiS_Pr);
3564
3565 SiS_StrangeStuff(SiS_Pr);
3566
3567 SiS_CloseCRTC(SiS_Pr);
3568
3569 #ifdef SISDUALHEAD
3570 if(pSiS->DualHeadMode) {
3571 pSiSEnt->CRT1ModeNo = ModeNo;
3572 pSiSEnt->CRT1DMode = mode;
3573 }
3574 #endif
3575
3576 if(SiS_Pr->UseCustomMode) {
3577 SiS_Pr->CRT1UsesCustomMode = TRUE;
3578 SiS_Pr->CSRClock_CRT1 = SiS_Pr->CSRClock;
3579 SiS_Pr->CModeFlag_CRT1 = SiS_Pr->CModeFlag;
3580 } else {
3581 SiS_Pr->CRT1UsesCustomMode = FALSE;
3582 }
3583
3584 /* Reset CRT2 if changing mode on CRT1 */
3585 #ifdef SISDUALHEAD
3586 if(pSiS->DualHeadMode) {
3587 if(pSiSEnt->CRT2ModeNo != -1) {
3588 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, 3,
3589 "(Re-)Setting mode for CRT2\n");
3590 backupcustom = SiS_Pr->UseCustomMode;
3591 backupcr30 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x30);
3592 backupcr31 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x31);
3593 backupcr35 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x35);
3594 backupcr38 = SiS_GetReg(SiS_Pr->SiS_P3d4,0x38);
3595 if(SiS_Pr->SiS_VBType & VB_SISVB) {
3596 /* Backup LUT-enable */
3597 if(pSiSEnt->CRT2ModeSet) {
3598 backupp40d = SiS_GetReg(SiS_Pr->SiS_Part4Port,0x0d) & 0x08;
3599 }
3600 }
3601 if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
3602 SiS_SetReg(SiS_Pr->SiS_P3d4,0x30,pSiSEnt->CRT2CR30);
3603 SiS_SetReg(SiS_Pr->SiS_P3d4,0x31,pSiSEnt->CRT2CR31);
3604 SiS_SetReg(SiS_Pr->SiS_P3d4,0x35,pSiSEnt->CRT2CR35);
3605 SiS_SetReg(SiS_Pr->SiS_P3d4,0x38,pSiSEnt->CRT2CR38);
3606 }
3607
3608 SiSBIOSSetModeCRT2(SiS_Pr, pSiSEnt->pScrn_1,
3609 pSiSEnt->CRT2DMode, pSiSEnt->CRT2IsCustom);
3610
3611 SiS_SetReg(SiS_Pr->SiS_P3d4,0x30,backupcr30);
3612 SiS_SetReg(SiS_Pr->SiS_P3d4,0x31,backupcr31);
3613 SiS_SetReg(SiS_Pr->SiS_P3d4,0x35,backupcr35);
3614 SiS_SetReg(SiS_Pr->SiS_P3d4,0x38,backupcr38);
3615 if(SiS_Pr->SiS_VBType & VB_SISVB) {
3616 SiS_SetRegANDOR(SiS_Pr->SiS_Part4Port,0x0d, ~0x08, backupp40d);
3617 }
3618 SiS_Pr->UseCustomMode = backupcustom;
3619 }
3620 }
3621 #endif
3622
3623 /* Warning: From here, the custom mode entries in SiS_Pr are
3624 * possibly overwritten
3625 */
3626
3627 SiS_DisplayOn(SiS_Pr);
3628 SiS_SetRegByte(SiS_Pr->SiS_P3c6,0xFF);
3629
3630 if(SiS_Pr->SiS_VBType & VB_SIS30xBLV) {
3631 if(SiS_Pr->ChipType >= SIS_315H) {
3632 SiS_SetReg(SiS_Pr->SiS_P3d4,0x38,backupreg);
3633 } else if((SiS_Pr->ChipType == SIS_630) ||
3634 (SiS_Pr->ChipType == SIS_730)) {
3635 SiS_SetReg(SiS_Pr->SiS_P3d4,0x35,backupreg);
3636 }
3637 }
3638
3639 SiS_Handle760(SiS_Pr);
3640
3641 /* Backup/Set ModeNo in BIOS scratch area */
3642 SiS_GetSetModeID(pScrn,ModeNo);
3643
3644 return TRUE;
3645 }
3646
3647 #ifndef GETBITSTR
3648 #define BITMASK(h,l) (((unsigned)(1U << ((h)-(l)+1))-1)<<(l))
3649 #define GENMASK(mask) BITMASK(1?mask,0?mask)
3650 #define GETBITS(var,mask) (((var) & GENMASK(mask)) >> (0?mask))
3651 #define GETBITSTR(val,from,to) ((GETBITS(val,from)) << (0?to))
3652 #endif
3653
3654 void
3655 SiS_CalcCRRegisters(struct SiS_Private *SiS_Pr, int depth)
3656 {
3657 int x = 1; /* Fix sync */
3658
3659 SiS_Pr->CCRT1CRTC[0] = ((SiS_Pr->CHTotal >> 3) - 5) & 0xff; /* CR0 */
3660 SiS_Pr->CCRT1CRTC[1] = (SiS_Pr->CHDisplay >> 3) - 1; /* CR1 */
3661 SiS_Pr->CCRT1CRTC[2] = (SiS_Pr->CHBlankStart >> 3) - 1; /* CR2 */
3662 SiS_Pr->CCRT1CRTC[3] = (((SiS_Pr->CHBlankEnd >> 3) - 1) & 0x1F) | 0x80; /* CR3 */
3663 SiS_Pr->CCRT1CRTC[4] = (SiS_Pr->CHSyncStart >> 3) + 3; /* CR4 */
3664 SiS_Pr->CCRT1CRTC[5] = ((((SiS_Pr->CHBlankEnd >> 3) - 1) & 0x20) << 2) | /* CR5 */
3665 (((SiS_Pr->CHSyncEnd >> 3) + 3) & 0x1F);
3666
3667 SiS_Pr->CCRT1CRTC[6] = (SiS_Pr->CVTotal - 2) & 0xFF; /* CR6 */
3668 SiS_Pr->CCRT1CRTC[7] = (((SiS_Pr->CVTotal - 2) & 0x100) >> 8) /* CR7 */
3669 | (((SiS_Pr->CVDisplay - 1) & 0x100) >> 7)
3670 | (((SiS_Pr->CVSyncStart - x) & 0x100) >> 6)
3671 | (((SiS_Pr->CVBlankStart- 1) & 0x100) >> 5)
3672 | 0x10
3673 | (((SiS_Pr->CVTotal - 2) & 0x200) >> 4)
3674 | (((SiS_Pr->CVDisplay - 1) & 0x200) >> 3)
3675 | (((SiS_Pr->CVSyncStart - x) & 0x200) >> 2);
3676
3677 SiS_Pr->CCRT1CRTC[16] = ((((SiS_Pr->CVBlankStart - 1) & 0x200) >> 4) >> 5); /* CR9 */
3678
3679 if(depth != 8) {
3680 if(SiS_Pr->CHDisplay >= 1600) SiS_Pr->CCRT1CRTC[16] |= 0x60; /* SRE */
3681 else if(SiS_Pr->CHDisplay >= 640) SiS_Pr->CCRT1CRTC[16] |= 0x40;
3682 }
3683
3684 SiS_Pr->CCRT1CRTC[8] = (SiS_Pr->CVSyncStart - x) & 0xFF; /* CR10 */
3685 SiS_Pr->CCRT1CRTC[9] = ((SiS_Pr->CVSyncEnd - x) & 0x0F) | 0x80; /* CR11 */
3686 SiS_Pr->CCRT1CRTC[10] = (SiS_Pr->CVDisplay - 1) & 0xFF; /* CR12 */
3687 SiS_Pr->CCRT1CRTC[11] = (SiS_Pr->CVBlankStart - 1) & 0xFF; /* CR15 */
3688 SiS_Pr->CCRT1CRTC[12] = (SiS_Pr->CVBlankEnd - 1) & 0xFF; /* CR16 */
3689
3690 SiS_Pr->CCRT1CRTC[13] = /* SRA */
3691 GETBITSTR((SiS_Pr->CVTotal -2), 10:10, 0:0) |
3692 GETBITSTR((SiS_Pr->CVDisplay -1), 10:10, 1:1) |
3693 GETBITSTR((SiS_Pr->CVBlankStart-1), 10:10, 2:2) |
3694 GETBITSTR((SiS_Pr->CVSyncStart -x), 10:10, 3:3) |
3695 GETBITSTR((SiS_Pr->CVBlankEnd -1), 8:8, 4:4) |
3696 GETBITSTR((SiS_Pr->CVSyncEnd ), 4:4, 5:5) ;
3697
3698 SiS_Pr->CCRT1CRTC[14] = /* SRB */
3699 GETBITSTR((SiS_Pr->CHTotal >> 3) - 5, 9:8, 1:0) |
3700 GETBITSTR((SiS_Pr->CHDisplay >> 3) - 1, 9:8, 3:2) |
3701 GETBITSTR((SiS_Pr->CHBlankStart >> 3) - 1, 9:8, 5:4) |
3702 GETBITSTR((SiS_Pr->CHSyncStart >> 3) + 3, 9:8, 7:6) ;
3703
3704
3705 SiS_Pr->CCRT1CRTC[15] = /* SRC */
3706 GETBITSTR((SiS_Pr->CHBlankEnd >> 3) - 1, 7:6, 1:0) |
3707 GETBITSTR((SiS_Pr->CHSyncEnd >> 3) + 3, 5:5, 2:2) ;
3708 }
3709
3710 void
3711 SiS_CalcLCDACRT1Timing(struct SiS_Private *SiS_Pr, unsigned short ModeNo,
3712 unsigned short ModeIdIndex)
3713 {
3714 unsigned short modeflag, tempax, tempbx = 0, remaining = 0;
3715 unsigned short VGAHDE = SiS_Pr->SiS_VGAHDE;
3716 int i, j;
3717
3718 /* 1:1 data: use data set by setcrt1crtc() */
3719 if(SiS_Pr->SiS_LCDInfo & LCDPass11) return;
3720
3721 modeflag = SiS_GetModeFlag(SiS_Pr, ModeNo, ModeIdIndex);
3722
3723 if(modeflag & HalfDCLK) VGAHDE >>= 1;
3724
3725 SiS_Pr->CHDisplay = VGAHDE;
3726 SiS_Pr->CHBlankStart = VGAHDE;
3727
3728 SiS_Pr->CVDisplay = SiS_Pr->SiS_VGAVDE;
3729 SiS_Pr->CVBlankStart = SiS_Pr->SiS_VGAVDE;
3730
3731 if(SiS_Pr->ChipType < SIS_315H) {
3732 tempbx = SiS_Pr->SiS_VGAHT;
3733 if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
3734 tempbx = SiS_Pr->PanelHT;
3735 }
3736 if(modeflag & HalfDCLK) tempbx >>= 1;
3737 remaining = tempbx % 8;
3738 } else {
3739 /* OK for LCDA, LVDS */
3740 tempbx = SiS_Pr->PanelHT - SiS_Pr->PanelXRes;
3741 tempax = SiS_Pr->SiS_VGAHDE; /* not /2 ! */
3742 if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
3743 tempax = SiS_Pr->PanelXRes;
3744 }
3745 tempbx += tempax;
3746 if(modeflag & HalfDCLK) tempbx -= VGAHDE;
3747 }
3748 SiS_Pr->CHTotal = SiS_Pr->CHBlankEnd = tempbx;
3749
3750 if(SiS_Pr->ChipType < SIS_315H) {
3751 if(SiS_Pr->SiS_VGAHDE == SiS_Pr->PanelXRes) {
3752 SiS_Pr->CHSyncStart = SiS_Pr->SiS_VGAHDE + ((SiS_Pr->PanelHRS + 1) & ~1);
3753 SiS_Pr->CHSyncEnd = SiS_Pr->CHSyncStart + SiS_Pr->PanelHRE;
3754 if(modeflag & HalfDCLK) {
3755 SiS_Pr->CHSyncStart >>= 1;
3756 SiS_Pr->CHSyncEnd >>= 1;
3757 }
3758 } else if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
3759 tempax = (SiS_Pr->PanelXRes - SiS_Pr->SiS_VGAHDE) >> 1;
3760 tempbx = (SiS_Pr->PanelHRS + 1) & ~1;
3761 if(modeflag & HalfDCLK) {
3762 tempax >>= 1;
3763 tempbx >>= 1;
3764 }
3765 SiS_Pr->CHSyncStart = (VGAHDE + tempax + tempbx + 7) & ~7;
3766 tempax = SiS_Pr->PanelHRE + 7;
3767 if(modeflag & HalfDCLK) tempax >>= 1;
3768 SiS_Pr->CHSyncEnd = (SiS_Pr->CHSyncStart + tempax) & ~7;
3769 } else {
3770 SiS_Pr->CHSyncStart = SiS_Pr->SiS_VGAHDE;
3771 if(modeflag & HalfDCLK) {
3772 SiS_Pr->CHSyncStart >>= 1;
3773 tempax = ((SiS_Pr->CHTotal - SiS_Pr->CHSyncStart) / 3) << 1;
3774 SiS_Pr->CHSyncEnd = SiS_Pr->CHSyncStart + tempax;
3775 } else {
3776 SiS_Pr->CHSyncEnd = (SiS_Pr->CHSyncStart + (SiS_Pr->CHTotal / 10) + 7) & ~7;
3777 SiS_Pr->CHSyncStart += 8;
3778 }
3779 }
3780 } else {
3781 tempax = VGAHDE;
3782 if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
3783 tempbx = SiS_Pr->PanelXRes;
3784 if(modeflag & HalfDCLK) tempbx >>= 1;
3785 tempax += ((tempbx - tempax) >> 1);
3786 }
3787 tempax += SiS_Pr->PanelHRS;
3788 SiS_Pr->CHSyncStart = tempax;
3789 tempax += SiS_Pr->PanelHRE;
3790 SiS_Pr->CHSyncEnd = tempax;
3791 }
3792
3793 tempbx = SiS_Pr->PanelVT - SiS_Pr->PanelYRes;
3794 tempax = SiS_Pr->SiS_VGAVDE;
3795 if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
3796 tempax = SiS_Pr->PanelYRes;
3797 } else if(SiS_Pr->ChipType < SIS_315H) {
3798 /* Stupid hack for 640x400/320x200 */
3799 if(SiS_Pr->SiS_LCDResInfo == Panel_1024x768) {
3800 if((tempax + tempbx) == 438) tempbx += 16;
3801 } else if((SiS_Pr->SiS_LCDResInfo == Panel_800x600) ||
3802 (SiS_Pr->SiS_LCDResInfo == Panel_1024x600)) {
3803 tempax = 0;
3804 tempbx = SiS_Pr->SiS_VGAVT;
3805 }
3806 }
3807 SiS_Pr->CVTotal = SiS_Pr->CVBlankEnd = tempbx + tempax;
3808
3809 tempax = SiS_Pr->SiS_VGAVDE;
3810 if(SiS_Pr->SiS_LCDInfo & DontExpandLCD) {
3811 tempax += (SiS_Pr->PanelYRes - tempax) >> 1;
3812 }
3813 tempax += SiS_Pr->PanelVRS;
3814 SiS_Pr->CVSyncStart = tempax;
3815 tempax += SiS_Pr->PanelVRE;
3816 SiS_Pr->CVSyncEnd = tempax;
3817 if(SiS_Pr->ChipType < SIS_315H) {
3818 SiS_Pr->CVSyncStart--;
3819 SiS_Pr->CVSyncEnd--;
3820 }
3821
3822 SiS_CalcCRRegisters(SiS_Pr, 8);
3823 SiS_Pr->CCRT1CRTC[15] &= ~0xF8;
3824 SiS_Pr->CCRT1CRTC[15] |= (remaining << 4);
3825 SiS_Pr->CCRT1CRTC[16] &= ~0xE0;
3826
3827 SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x11,0x7f);
3828
3829 for(i = 0, j = 0; i <= 7; i++, j++) {
3830 SiS_SetReg(SiS_Pr->SiS_P3d4,j,SiS_Pr->CCRT1CRTC[i]);
3831 }
3832 for(j = 0x10; i <= 10; i++, j++) {
3833 SiS_SetReg(SiS_Pr->SiS_P3d4,j,SiS_Pr->CCRT1CRTC[i]);
3834 }
3835 for(j = 0x15; i <= 12; i++, j++) {
3836 SiS_SetReg(SiS_Pr->SiS_P3d4,j,SiS_Pr->CCRT1CRTC[i]);
3837 }
3838 for(j = 0x0A; i <= 15; i++, j++) {
3839 SiS_SetReg(SiS_Pr->SiS_P3c4,j,SiS_Pr->CCRT1CRTC[i]);
3840 }
3841
3842 tempax = SiS_Pr->CCRT1CRTC[16] & 0xE0;
3843 SiS_SetRegANDOR(SiS_Pr->SiS_P3c4,0x0E,0x1F,tempax);
3844
3845 tempax = (SiS_Pr->CCRT1CRTC[16] & 0x01) << 5;
3846 if(modeflag & DoubleScanMode) tempax |= 0x80;
3847 SiS_SetRegANDOR(SiS_Pr->SiS_P3d4,0x09,0x5F,tempax);
3848
3849 #ifdef TWDEBUG
3850 xf86DrvMsg(0, X_INFO, "%d %d %d %d %d %d %d %d (%d %d %d %d)\n",
3851 SiS_Pr->CHDisplay, SiS_Pr->CHSyncStart, SiS_Pr->CHSyncEnd, SiS_Pr->CHTotal,
3852 SiS_Pr->CVDisplay, SiS_Pr->CVSyncStart, SiS_Pr->CVSyncEnd, SiS_Pr->CVTotal,
3853 SiS_Pr->CHBlankStart, SiS_Pr->CHBlankEnd, SiS_Pr->CVBlankStart, SiS_Pr->CVBlankEnd);
3854 xf86DrvMsg(0, X_INFO, " {{0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,\n",
3855 SiS_Pr->CCRT1CRTC[0], SiS_Pr->CCRT1CRTC[1],
3856 SiS_Pr->CCRT1CRTC[2], SiS_Pr->CCRT1CRTC[3],
3857 SiS_Pr->CCRT1CRTC[4], SiS_Pr->CCRT1CRTC[5],
3858 SiS_Pr->CCRT1CRTC[6], SiS_Pr->CCRT1CRTC[7]);
3859 xf86DrvMsg(0, X_INFO, " 0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,\n",
3860 SiS_Pr->CCRT1CRTC[8], SiS_Pr->CCRT1CRTC[9],
3861 SiS_Pr->CCRT1CRTC[10], SiS_Pr->CCRT1CRTC[11],
3862 SiS_Pr->CCRT1CRTC[12], SiS_Pr->CCRT1CRTC[13],
3863 SiS_Pr->CCRT1CRTC[14], SiS_Pr->CCRT1CRTC[15]);
3864 xf86DrvMsg(0, X_INFO, " 0x%02x}},\n", SiS_Pr->CCRT1CRTC[16]);
3865 #endif
3866 }
3867
3868 void
3869 SiS_Generic_ConvertCRData(struct SiS_Private *SiS_Pr, unsigned char *crdata,
3870 int xres, int yres,
3871 DisplayModePtr current
3872 )
3873 {
3874 unsigned short HRE, HBE, HRS, HBS, HDE, HT;
3875 unsigned short VRE, VBE, VRS, VBS, VDE, VT;
3876 unsigned char sr_data, cr_data, cr_data2;
3877 int A, B, C, D, E, F, temp;
3878
3879 sr_data = crdata[14];
3880
3881 /* Horizontal total */
3882 HT = crdata[0] | ((unsigned short)(sr_data & 0x03) << 8);
3883 A = HT + 5;
3884
3885 /* Horizontal display enable end */
3886 HDE = crdata[1] | ((unsigned short)(sr_data & 0x0C) << 6);
3887 E = HDE + 1;
3888
3889 /* Horizontal retrace (=sync) start */
3890 HRS = crdata[4] | ((unsigned short)(sr_data & 0xC0) << 2);
3891 F = HRS - E - 3;
3892
3893 /* Horizontal blank start */
3894 HBS = crdata[2] | ((unsigned short)(sr_data & 0x30) << 4);
3895
3896 sr_data = crdata[15];
3897 cr_data = crdata[5];
3898
3899 /* Horizontal blank end */
3900 HBE = (crdata[3] & 0x1f) |
3901 ((unsigned short)(cr_data & 0x80) >> 2) |
3902 ((unsigned short)(sr_data & 0x03) << 6);
3903
3904 /* Horizontal retrace (=sync) end */
3905 HRE = (cr_data & 0x1f) | ((sr_data & 0x04) << 3);
3906
3907 temp = HBE - ((E - 1) & 255);
3908 B = (temp > 0) ? temp : (temp + 256);
3909
3910 temp = HRE - ((E + F + 3) & 63);
3911 C = (temp > 0) ? temp : (temp + 64);
3912
3913 D = B - F - C;
3914
3915 current->HDisplay = (E * 8);
3916 current->HSyncStart = (E * 8) + (F * 8);
3917 current->HSyncEnd = (E * 8) + (F * 8) + (C * 8);
3918 current->HTotal = (E * 8) + (F * 8) + (C * 8) + (D * 8);
3919 #ifdef TWDEBUG
3920 xf86DrvMsg(0, X_INFO,
3921 "H: A %d B %d C %d D %d E %d F %d HT %d HDE %d HRS %d HBS %d HBE %d HRE %d\n",
3922 A, B, C, D, E, F, HT, HDE, HRS, HBS, HBE, HRE);
3923 #else
3924 (void)VBS; (void)HBS; (void)A;
3925 #endif
3926
3927 /* Vertical */
3928 sr_data = crdata[13];
3929 cr_data = crdata[7];
3930
3931 /* Vertical total */
3932 VT = crdata[6] |
3933 ((unsigned short)(cr_data & 0x01) << 8) |
3934 ((unsigned short)(cr_data & 0x20) << 4) |
3935 ((unsigned short)(sr_data & 0x01) << 10);
3936 A = VT + 2;
3937
3938 /* Vertical display enable end */
3939 VDE = crdata[10] |
3940 ((unsigned short)(cr_data & 0x02) << 7) |
3941 ((unsigned short)(cr_data & 0x40) << 3) |
3942 ((unsigned short)(sr_data & 0x02) << 9);
3943 E = VDE + 1;
3944
3945 /* Vertical retrace (=sync) start */
3946 VRS = crdata[8] |
3947 ((unsigned short)(cr_data & 0x04) << 6) |
3948 ((unsigned short)(cr_data & 0x80) << 2) |
3949 ((unsigned short)(sr_data & 0x08) << 7);
3950 F = VRS + 1 - E;
3951
3952 cr_data2 = (crdata[16] & 0x01) << 5;
3953
3954 /* Vertical blank start */
3955 VBS = crdata[11] |
3956 ((unsigned short)(cr_data & 0x08) << 5) |
3957 ((unsigned short)(cr_data2 & 0x20) << 4) |
3958 ((unsigned short)(sr_data & 0x04) << 8);
3959
3960 /* Vertical blank end */
3961 VBE = crdata[12] | ((unsigned short)(sr_data & 0x10) << 4);
3962 temp = VBE - ((E - 1) & 511);
3963 B = (temp > 0) ? temp : (temp + 512);
3964
3965 /* Vertical retrace (=sync) end */
3966 VRE = (crdata[9] & 0x0f) | ((sr_data & 0x20) >> 1);
3967 temp = VRE - ((E + F - 1) & 31);
3968 C = (temp > 0) ? temp : (temp + 32);
3969
3970 D = B - F - C;
3971
3972 current->VDisplay = VDE + 1;
3973 current->VSyncStart = VRS + 1;
3974 current->VSyncEnd = ((VRS & ~0x1f) | VRE) + 1;
3975 if(VRE <= (VRS & 0x1f)) current->VSyncEnd += 32;
3976 current->VTotal = E + D + C + F;
3977 #if 0
3978 current->VDisplay = E;
3979 current->VSyncStart = E + D;
3980 current->VSyncEnd = E + D + C;
3981 current->VTotal = E + D + C + F;
3982 #endif
3983 #ifdef TWDEBUG
3984 xf86DrvMsg(0, X_INFO,
3985 "V: A %d B %d C %d D %d E %d F %d VT %d VDE %d VRS %d VBS %d VBE %d VRE %d\n",
3986 A, B, C, D, E, F, VT, VDE, VRS, VBS, VBE, VRE);
3987 #endif
3988
3989 if((xres == 320) && ((yres == 200) || (yres == 240))) {
3990 /* Terrible hack, but correct CRTC data for
3991 * these modes only produces a black screen...
3992 * (HRE is 0, leading into a too large C and
3993 * a negative D. The CRT controller does not
3994 * seem to like correcting HRE to 50)
3995 */
3996 current->HDisplay = 320;
3997 current->HSyncStart = 328;
3998 current->HSyncEnd = 376;
3999 current->HTotal = 400;
4000 }
4001 }