src/sis_regs.h

   1 /*
   2  * Register access macros and register definitions
   3  *
   4  * Copyright (C) 2001-2005 by Thomas Winischhofer, Vienna, Austria
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1) Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2) Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3) The name of the author may not be used to endorse or promote products
  15  *    derived from this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  */
  29
  30 #ifndef _SIS_REGS_H_
  31 #define _SIS_REGS_H_
  32
  33 /*
  34 #define SIS_NEED_inSISREG
  35 #define SIS_NEED_inSISREGW
  36 #define SIS_NEED_inSISREGL
  37 #define SIS_NEED_outSISREG
  38 #define SIS_NEED_outSISREGW
  39 #define SIS_NEED_outSISREGL
  40 #define SIS_NEED_orSISREG
  41 #define SIS_NEED_andSISREG
  42 #define SIS_NEED_inSISIDXREG
  43 #define SIS_NEED_outSISIDXREG
  44 #define SIS_NEED_orSISIDXREG
  45 #define SIS_NEED_andSISIDXREG
  46 #define SIS_NEED_setSISIDXREG
  47 #define SIS_NEED_setSISIDXREGmask
  48 */
  49
  50 /* Video RAM access macros */
  51
  52 /* (Currently, these are use on all platforms; USB2VGA is handled
  53  * entirely different in a dedicated driver)
  54  */
  55
  56 /* dest is video RAM, src is system RAM */
  57 #define sisfbwritel(dest, data)         *(dest)     = (data)
  58 #define sisfbwritelinc(dest, data)      *((dest)++) = (data)
  59 #define sisfbwritelp(dest, dataptr)     *(dest)     = *(dataptr)
  60 #define sisfbwritelpinc(dest, dataptr)  *((dest)++) = *((dataptr)++)
  61
  62 #define sisfbwritew(dest, data)         *(dest)     = (data)
  63 #define sisfbwritewinc(dest, data)      *((dest)++) = (data)
  64 #define sisfbwritewp(dest, dataptr)     *(dest)     = *(dataptr)
  65 #define sisfbwritewpinc(dest, dataptr)  *((dest)++) = *((dataptr)++)
  66
  67 #define sisfbwriteb(dest, data)         *(dest)     = (data)
  68 #define sisfbwritebinc(dest, data)      *((dest)++) = (data)
  69 #define sisfbwritebp(dest, dataptr)     *(dest)     = *(dataptr)
  70 #define sisfbwritebpinc(dest, dataptr)  *((dest)++) = *((dataptr)++)
  71
  72 /* Source is video RAM */
  73 #define sisfbreadl(src)                 *(src)
  74 #define sisfbreadlinc(src)              *((src)++)
  75
  76 #define sisfbreadw(src)                 *(src)
  77 #define sisfbreadwinc(src)              *((src)++)
  78
  79 #define sisfbreadb(src)                 *(src)
  80 #define sisfbreadbinc(src)              *((src)++)
  81
  82 /* Register access macros  --------------- */
  83
  84 #ifndef SISUSEDEVPORT
  85
  86 #define inSISREG(base)          inb(base)
  87 #define inSISREGW(base)         inw(base)
  88 #define inSISREGL(base)         inl(base)
  89
  90 #define outSISREG(base,val)     outb(base,val)
  91 #define outSISREGW(base,val)    outw(base,val)
  92 #define outSISREGL(base,val)    outl(base,val)
  93
  94 #define orSISREG(base,val)                              \
  95                     do {                                \
  96                       UChar __Temp = inSISREG(base);    \
  97                       outSISREG(base, __Temp | (val));  \
  98                     } while (0)
  99
 100 #define andSISREG(base,val)                             \
 101                     do {                                \
 102                       UChar __Temp = inSISREG(base);    \
 103                       outSISREG(base, __Temp & (val));  \
 104                     } while (0)
 105
 106 #define inSISIDXREG(base,idx,var)               \
 107                     do {                        \
 108                       outSISREG(base, idx);     \
 109                       var = inSISREG((base)+1); \
 110                     } while (0)
 111
 112 #define outSISIDXREG(base,idx,val)              \
 113                     do {                        \
 114                       outSISREG(base, idx);     \
 115                       outSISREG((base)+1, val); \
 116                     } while (0)
 117
 118 #define orSISIDXREG(base,idx,val)                               \
 119                     do {                                        \
 120                       UChar __Temp;                             \
 121                       outSISREG(base, idx);                     \
 122                       __Temp = inSISREG((base)+1) | (val);      \
 123                       outSISREG((base)+1, __Temp);              \
 124                     } while (0)
 125
 126 #define andSISIDXREG(base,idx,and)                              \
 127                     do {                                        \
 128                       UChar __Temp;                             \
 129                       outSISREG(base, idx);                     \
 130                       __Temp = inSISREG((base)+1) & (and);      \
 131                       outSISREG((base)+1, __Temp);              \
 132                     } while (0)
 133
 134 #define setSISIDXREG(base,idx,and,or)                                   \
 135                     do {                                                \
 136                       UChar __Temp;                                     \
 137                       outSISREG(base, idx);                             \
 138                       __Temp = (inSISREG((base)+1) & (and)) | (or);     \
 139                       outSISREG((base)+1, __Temp);                      \
 140                     } while (0)
 141
 142 #define setSISIDXREGmask(base,idx,data,mask)                    \
 143                     do {                                        \
 144                       UChar __Temp;                             \
 145                       outSISREG(base, idx);                     \
 146                       __Temp = (inSISREG((base)+1)) & (~(mask));\
 147                       __Temp |= ((data) & (mask));              \
 148                       outSISREG((base)+1, __Temp);              \
 149                     } while(0)
 150
 151 #else /* USEDEVPORT */
 152
 153 extern int sisdevport;
 154
 155 /* Note to self: SEEK_SET is faster than SEEK_CUR */
 156
 157 #ifdef SIS_NEED_inSISREG
 158 static UChar inSISREG(ULong base)
 159 {
 160     UChar tmp;
 161     lseek(sisdevport, base, SEEK_SET);
 162     read(sisdevport, &tmp, 1);
 163     return tmp;
 164 }
 165 #endif
 166
 167 #ifdef SIS_NEED_inSISREGW
 168 static __inline UShort inSISREGW(ULong base)
 169 {
 170     UShort tmp;
 171     lseek(sisdevport, base, SEEK_SET);
 172     read(sisdevport, &tmp, 2);
 173     return tmp;
 174 }
 175 #endif
 176
 177 #ifdef SIS_NEED_inSISREGL
 178 static __inline unsigned int inSISREGL(ULong base)
 179 {
 180     ULong tmp;
 181     lseek(sisdevport, base, SEEK_SET);
 182     read(sisdevport, &tmp, 4);
 183     return tmp;
 184 }
 185 #endif
 186
 187 #ifdef SIS_NEED_outSISREG
 188 static void outSISREG(ULong base, UChar val)
 189 {
 190     lseek(sisdevport, base, SEEK_SET);
 191     write(sisdevport, &val, 1);
 192 }
 193 #endif
 194
 195 #ifdef SIS_NEED_outSISREGW
 196 static __inline void outSISREGW(ULong base, UShort val)
 197 {
 198     lseek(sisdevport, base, SEEK_SET);
 199     write(sisdevport, &val, 2);
 200 }
 201 #endif
 202
 203 #ifdef SIS_NEED_outSISREGL
 204 static __inline void outSISREGL(ULong base, unsigned int val)
 205 {
 206     lseek(sisdevport, base, SEEK_SET);
 207     write(sisdevport, &val, 4);
 208 }
 209 #endif
 210
 211 #ifdef SIS_NEED_orSISREG
 212 static void orSISREG(ULong base, UChar val)
 213 {
 214     UChar tmp;
 215     lseek(sisdevport, base, SEEK_SET);
 216     read(sisdevport, &tmp, 1);
 217     tmp |= val;
 218     lseek(sisdevport, base, SEEK_SET);
 219     write(sisdevport, &tmp, 1);
 220 }
 221 #endif
 222
 223 #ifdef SIS_NEED_andSISREG
 224 static void andSISREG(ULong base, UChar val)
 225 {
 226     UChar tmp;
 227     lseek(sisdevport, base, SEEK_SET);
 228     read(sisdevport, &tmp, 1);
 229     tmp &= val;
 230     lseek(sisdevport, base, SEEK_SET);
 231     write(sisdevport, &tmp, 1);
 232 }
 233 #endif
 234
 235 #ifdef SIS_NEED_outSISIDXREG
 236 static void outSISIDXREG(ULong base, UChar idx, UChar val)
 237 {
 238     UChar value[2];
 239     value[0] = idx;     /* sic! reads/writes bytewise! */
 240     value[1] = val;
 241     lseek(sisdevport, base, SEEK_SET);
 242     write(sisdevport, &value[0], 2);
 243 }
 244 #endif
 245
 246 #ifdef SIS_NEED_inSISIDXREG
 247 static UChar __inSISIDXREG(ULong base, UChar idx)
 248 {
 249     UChar tmp;
 250     lseek(sisdevport, base, SEEK_SET);
 251     write(sisdevport, &idx, 1);
 252     read(sisdevport, &tmp, 1);
 253     return tmp;
 254 }
 255 #define inSISIDXREG(base,idx,var)  var = __inSISIDXREG(base, idx);
 256 #endif
 257
 258 #ifdef SIS_NEED_orSISIDXREG
 259 static void orSISIDXREG(ULong base, UChar idx, UChar val)
 260 {
 261     UChar tmp;
 262     lseek(sisdevport, base, SEEK_SET);
 263     write(sisdevport, &idx, 1);
 264     read(sisdevport, &tmp, 1);
 265     tmp |= val;
 266     lseek(sisdevport, base + 1, SEEK_SET);
 267     write(sisdevport, &tmp, 1);
 268 }
 269 #endif
 270
 271 #ifdef SIS_NEED_andSISIDXREG
 272 static void andSISIDXREG(ULong base, UChar idx, UChar val)
 273 {
 274     UChar tmp;
 275     lseek(sisdevport, base, SEEK_SET);
 276     write(sisdevport, &idx, 1);
 277     read(sisdevport, &tmp, 1);
 278     tmp &= val;
 279     lseek(sisdevport, base + 1, SEEK_SET);
 280     write(sisdevport, &tmp, 1);
 281 }
 282 #endif
 283
 284 #ifdef SIS_NEED_setSISIDXREG
 285 static void setSISIDXREG(ULong base, UChar idx,
 286                          UChar myand, UChar myor)
 287 {
 288     UChar tmp;
 289     lseek(sisdevport, base, SEEK_SET);
 290     write(sisdevport, &idx, 1);
 291     read(sisdevport, &tmp, 1);
 292     tmp &= myand;
 293     tmp |= myor;
 294     lseek(sisdevport, base + 1, SEEK_SET);
 295     write(sisdevport, &tmp, 1);
 296 }
 297 #endif
 298
 299 #ifdef SIS_NEED_setSISIDXREGmask
 300 static void setSISIDXREGmask(ULong base, UChar idx,
 301                              UChar data, UChar mask)
 302 {
 303     UChar tmp;
 304     lseek(sisdevport, base, SEEK_SET);
 305     write(sisdevport, &idx, 1);
 306     read(sisdevport, &tmp, 1);
 307     tmp &= ~(mask);
 308     tmp |= (data & mask);
 309     lseek(sisdevport, base + 1, SEEK_SET);
 310     write(sisdevport, &tmp, 1);
 311 }
 312 #endif
 313
 314 #endif  /* SISUSEDEVPORT */
 315
 316 /* Video RAM and MMIO access macros ----- */
 317
 318 #define sisclearvram(where, howmuch)    bzero(where, howmuch)
 319
 320 /* MMIO */
 321 #define SIS_MMIO_OUT8   MMIO_OUT8
 322 #define SIS_MMIO_OUT16  MMIO_OUT16
 323 #define SIS_MMIO_OUT32  MMIO_OUT32
 324
 325 #define SIS_MMIO_IN8    MMIO_IN8
 326 #define SIS_MMIO_IN16   MMIO_IN16
 327 #define SIS_MMIO_IN32   MMIO_IN32
 328
 329 /* VRAM queue acceleration */
 330
 331 #define SiSWriteQueue(tt)
 332
 333 #define SIS_WQINDEX(i)  ((CARD32 *)(tt))[(i)]
 334
 335 #define SIS_RQINDEX(i)  ((volatile CARD32 *)(tt))[(i)]
 336
 337 /* Port offsets  --------------- */
 338
 339 #define AROFFSET        0x40
 340 #define ARROFFSET       0x41
 341 #define GROFFSET        0x4e
 342 #define SROFFSET        0x44
 343 #define CROFFSET        0x54
 344 #define MISCROFFSET     0x4c
 345 #define MISCWOFFSET     0x42
 346 #define INPUTSTATOFFSET 0x5A
 347 #define PART1OFFSET     0x04
 348 #define PART2OFFSET     0x10
 349 #define PART3OFFSET     0x12
 350 #define PART4OFFSET     0x14
 351 #define PART5OFFSET     0x16
 352 #define CAPTUREOFFSET   0x00
 353 #define VIDEOOFFSET     0x02
 354 #define COLREGOFFSET    0x48
 355 #define PELMASKOFFSET   0x46
 356
 357 #define SISAR       pSiS->RelIO + AROFFSET
 358 #define SISARR      pSiS->RelIO + ARROFFSET
 359 #define SISGR       pSiS->RelIO + GROFFSET
 360 #define SISSR       pSiS->RelIO + SROFFSET
 361 #define SISCR       pSiS->RelIO + CROFFSET
 362 #define SISMISCR    pSiS->RelIO + MISCROFFSET
 363 #define SISMISCW    pSiS->RelIO + MISCWOFFSET
 364 #define SISINPSTAT  pSiS->RelIO + INPUTSTATOFFSET
 365 #define SISPART1    pSiS->RelIO + PART1OFFSET
 366 #define SISPART2    pSiS->RelIO + PART2OFFSET
 367 #define SISPART3    pSiS->RelIO + PART3OFFSET
 368 #define SISPART4    pSiS->RelIO + PART4OFFSET
 369 #define SISPART5    pSiS->RelIO + PART5OFFSET
 370 #define SISCAP      pSiS->RelIO + CAPTUREOFFSET
 371 #define SISVID      pSiS->RelIO + VIDEOOFFSET
 372 #define SISCOLIDXR  pSiS->RelIO + COLREGOFFSET - 1
 373 #define SISCOLIDX   pSiS->RelIO + COLREGOFFSET
 374 #define SISCOLDATA  pSiS->RelIO + COLREGOFFSET + 1
 375 #define SISCOL2IDX  SISPART5
 376 #define SISCOL2DATA SISPART5 + 1
 377 #define SISPEL      pSiS->RelIO + PELMASKOFFSET
 378
 379 /* Video registers (300/315/330/340 series only)  --------------- */
 380 #define  Index_VI_Passwd                        0x00
 381
 382 /* Video overlay horizontal start/end, unit=screen pixels */
 383 #define  Index_VI_Win_Hor_Disp_Start_Low        0x01
 384 #define  Index_VI_Win_Hor_Disp_End_Low          0x02
 385 #define  Index_VI_Win_Hor_Over                  0x03 /* Overflow */
 386
 387 /* Video overlay vertical start/end, unit=screen pixels */
 388 #define  Index_VI_Win_Ver_Disp_Start_Low        0x04
 389 #define  Index_VI_Win_Ver_Disp_End_Low          0x05
 390 #define  Index_VI_Win_Ver_Over                  0x06 /* Overflow */
 391
 392 /* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=word */
 393 #define  Index_VI_Disp_Y_Buf_Start_Low          0x07
 394 #define  Index_VI_Disp_Y_Buf_Start_Middle       0x08
 395 #define  Index_VI_Disp_Y_Buf_Start_High         0x09
 396
 397 /* U Plane (4:2:0) buffer start address, unit=word */
 398 #define  Index_VI_U_Buf_Start_Low               0x0A
 399 #define  Index_VI_U_Buf_Start_Middle            0x0B
 400 #define  Index_VI_U_Buf_Start_High              0x0C
 401
 402 /* V Plane (4:2:0) buffer start address, unit=word */
 403 #define  Index_VI_V_Buf_Start_Low               0x0D
 404 #define  Index_VI_V_Buf_Start_Middle            0x0E
 405 #define  Index_VI_V_Buf_Start_High              0x0F
 406
 407 /* Pitch for Y, UV Planes, unit=word */
 408 #define  Index_VI_Disp_Y_Buf_Pitch_Low          0x10
 409 #define  Index_VI_Disp_UV_Buf_Pitch_Low         0x11
 410 #define  Index_VI_Disp_Y_UV_Buf_Pitch_Middle    0x12
 411
 412 /* What is this ? */
 413 #define  Index_VI_Disp_Y_Buf_Preset_Low         0x13
 414 #define  Index_VI_Disp_Y_Buf_Preset_Middle      0x14
 415
 416 #define  Index_VI_UV_Buf_Preset_Low             0x15
 417 #define  Index_VI_UV_Buf_Preset_Middle          0x16
 418 #define  Index_VI_Disp_Y_UV_Buf_Preset_High     0x17
 419
 420 /* Scaling control registers */
 421 #define  Index_VI_Hor_Post_Up_Scale_Low         0x18
 422 #define  Index_VI_Hor_Post_Up_Scale_High        0x19
 423 #define  Index_VI_Ver_Up_Scale_Low              0x1A
 424 #define  Index_VI_Ver_Up_Scale_High             0x1B
 425 #define  Index_VI_Scale_Control                 0x1C
 426
 427 /* Playback line buffer control */
 428 #define  Index_VI_Play_Threshold_Low            0x1D
 429 #define  Index_VI_Play_Threshold_High           0x1E
 430 #define  Index_VI_Line_Buffer_Size              0x1F
 431
 432 /* Destination color key */
 433 #define  Index_VI_Overlay_ColorKey_Red_Min      0x20
 434 #define  Index_VI_Overlay_ColorKey_Green_Min    0x21
 435 #define  Index_VI_Overlay_ColorKey_Blue_Min     0x22
 436 #define  Index_VI_Overlay_ColorKey_Red_Max      0x23
 437 #define  Index_VI_Overlay_ColorKey_Green_Max    0x24
 438 #define  Index_VI_Overlay_ColorKey_Blue_Max     0x25
 439
 440 /* Source color key, YUV color space */
 441 #define  Index_VI_Overlay_ChromaKey_Red_Y_Min   0x26
 442 #define  Index_VI_Overlay_ChromaKey_Green_U_Min 0x27
 443 #define  Index_VI_Overlay_ChromaKey_Blue_V_Min  0x28
 444 #define  Index_VI_Overlay_ChromaKey_Red_Y_Max   0x29
 445 #define  Index_VI_Overlay_ChromaKey_Green_U_Max 0x2A
 446 #define  Index_VI_Overlay_ChromaKey_Blue_V_Max  0x2B
 447
 448 /* Contrast enhancement and brightness control */
 449 #define  Index_VI_Contrast_Factor               0x2C    /* obviously unused/undefined */
 450 #define  Index_VI_Brightness                    0x2D
 451 #define  Index_VI_Contrast_Enh_Ctrl             0x2E
 452
 453 #define  Index_VI_Key_Overlay_OP                0x2F
 454
 455 #define  Index_VI_Control_Misc0                 0x30
 456 #define  Index_VI_Control_Misc1                 0x31
 457 #define  Index_VI_Control_Misc2                 0x32
 458
 459 /* Subpicture registers */
 460 #define  Index_VI_SubPict_Buf_Start_Low         0x33
 461 #define  Index_VI_SubPict_Buf_Start_Middle      0x34
 462 #define  Index_VI_SubPict_Buf_Start_High        0x35
 463
 464 /* What is this ? */
 465 #define  Index_VI_SubPict_Buf_Preset_Low        0x36
 466 #define  Index_VI_SubPict_Buf_Preset_Middle     0x37
 467
 468 /* Subpicture pitch, unit=16 bytes */
 469 #define  Index_VI_SubPict_Buf_Pitch             0x38
 470
 471 /* Subpicture scaling control */
 472 #define  Index_VI_SubPict_Hor_Scale_Low         0x39
 473 #define  Index_VI_SubPict_Hor_Scale_High        0x3A
 474 #define  Index_VI_SubPict_Vert_Scale_Low        0x3B
 475 #define  Index_VI_SubPict_Vert_Scale_High       0x3C
 476
 477 #define  Index_VI_SubPict_Scale_Control         0x3D
 478 /* (0x40 = enable/disable subpicture) */
 479
 480 /* Subpicture line buffer control */
 481 #define  Index_VI_SubPict_Threshold             0x3E
 482
 483 /* What is this? */
 484 #define  Index_VI_FIFO_Max                      0x3F
 485
 486 /* Subpicture palette; 16 colors, total 32 bytes address space */
 487 #define  Index_VI_SubPict_Pal_Base_Low          0x40
 488 #define  Index_VI_SubPict_Pal_Base_High         0x41
 489
 490 /* I wish I knew how to use these ... */
 491 #define  Index_MPEG_Read_Ctrl0                  0x60    /* MPEG auto flip */
 492 #define  Index_MPEG_Read_Ctrl1                  0x61    /* MPEG auto flip */
 493 #define  Index_MPEG_Read_Ctrl2                  0x62    /* MPEG auto flip */
 494 #define  Index_MPEG_Read_Ctrl3                  0x63    /* MPEG auto flip */
 495
 496 /* MPEG AutoFlip scale */
 497 #define  Index_MPEG_Ver_Up_Scale_Low            0x64
 498 #define  Index_MPEG_Ver_Up_Scale_High           0x65
 499
 500 #define  Index_MPEG_Y_Buf_Preset_Low            0x66
 501 #define  Index_MPEG_Y_Buf_Preset_Middle         0x67
 502 #define  Index_MPEG_UV_Buf_Preset_Low           0x68
 503 #define  Index_MPEG_UV_Buf_Preset_Middle        0x69
 504 #define  Index_MPEG_Y_UV_Buf_Preset_High        0x6A
 505
 506 /* The following registers only exist on the 315/330/340 series */
 507
 508 /* Bit 16:24 of Y_U_V buf start address */
 509 #define  Index_VI_Y_Buf_Start_Over              0x6B
 510 #define  Index_VI_U_Buf_Start_Over              0x6C
 511 #define  Index_VI_V_Buf_Start_Over              0x6D
 512
 513 #define  Index_VI_Disp_Y_Buf_Pitch_High         0x6E
 514 #define  Index_VI_Disp_UV_Buf_Pitch_High        0x6F
 515
 516 /* Hue and saturation */
 517 #define  Index_VI_Hue                           0x70
 518 #define  Index_VI_Saturation                    0x71
 519
 520 #define  Index_VI_SubPict_Start_Over            0x72
 521 #define  Index_VI_SubPict_Buf_Pitch_High        0x73
 522
 523 #define  Index_VI_Control_Misc3                 0x74
 524
 525 /* 340 and later: */
 526 /* DDA registers 0x75 - 0xb4 */
 527 /* threshold high 0xb5, 0xb6 */
 528 #define  Index_VI_Line_Buffer_Size_High         0xb7
 529
 530
 531 /* Bits in Scale control (0x1c) */
 532 #define  VI_Scale_Ctrl_Horiz_DDA                0x20
 533 #define  VI_Scale_Ctrl_Vert_DDA                 0x40
 534
 535 /* Bits (and helpers) for Index_VI_Control_Misc0 */
 536 #define  VI_Misc0_Enable_Capture_AutoFlip       0x01 /* 340 only? */
 537 #define  VI_Misc0_Enable_Overlay                0x02
 538 #define  VI_Misc0_420_Plane_Enable              0x04 /* Select Plane or Packed mode */
 539 #define  VI_Misc0_422_Enable                    0x20 /* Select 422 or 411 mode */
 540 #define  VI_Misc0_Fmt_YVU420P                   0x0C /* YUV420 Planar (I420, YV12) */
 541 #define  VI_Misc0_Fmt_YUYV                      0x28 /* YUYV Packed (=YUY2) */
 542 #define  VI_Misc0_Fmt_UYVY                      0x08 /* (UYVY) */
 543 #define  VI_Misc0_Fmt_YVYU                      0x38 /* (YVYU) (315 series only?) */
 544 #define  VI_Misc0_Fmt_NV21                      0x5c /* (330 series only?) */
 545 #define  VI_Misc0_Fmt_NV12                      0x4c /* (330 series only?) */
 546 #define  VI_Misc0_ChromaKeyRGBYUV               0x40 /* 300 series only: 0 = RGB, 1 = YUV */
 547
 548 /* Bits for Index_VI_Control_Misc1 */
 549 #define  VI_Misc1_DisableGraphicsAtOverlay      0x01 /* Disables graphics display in overlay area */
 550 #define  VI_Misc1_BOB_Enable                    0x02 /* Enable BOB de-interlacer */
 551 #define  VI_Misc1_Line_Merge                    0x04
 552 #define  VI_Misc1_Field_Mode                    0x08 /* ? Assume even/odd fields interleaved in memory ? */
 553 #define  VI_Misc1_Non_Interleave                0x10 /* ? Odd and Even fields are not interleaved ? */
 554 #define  VI_Misc1_Buf_Addr_Lock                 0x20 /* 315 series only? */
 555 /* #define  VI_Misc1_?                          0x40  */
 556 /* #define  VI_Misc1_?                          0x80  */
 557
 558 /* Bits for Index_VI_Control_Misc2 */
 559 #define  VI_Misc2_Select_Video2                 0x01
 560 #define  VI_Misc2_Video2_On_Top                 0x02
 561 #define  VI_Misc2_DisableGraphics               0x04 /* Disable graphics display entirely (<= 650 only, not >= M650, 651) */
 562 #define  VI_Misc2_Vertical_Interpol             0x08
 563 #define  VI_Misc2_Dual_Line_Merge               0x10  /* dual-overlay chips only; "dual video windows relative line buffer merge" */
 564 #define  VI_Misc2_All_Line_Merge                0x20  /* > 315 only */
 565 #define  VI_Misc2_Auto_Flip_Enable              0x40
 566 #define  VI_Misc2_Video_Reg_Write_Enable        0x80  /* 315 series only? */
 567
 568 /* Bits for Index_VI_Control_Misc3 */
 569 #define  VI_Misc3_Submit_Video_1                0x01  /* AKA "address ready" */
 570 #define  VI_Misc3_Submit_Video_2                0x02  /* AKA "address ready" */
 571 #define  VI_Misc3_Submit_SubPict                0x04  /* AKA "address ready" */
 572
 573 /* Values for Index_VI_Key_Overlay_OP (0x2F) */
 574 #define  VI_ROP_Never                           0x00
 575 #define  VI_ROP_DestKey                         0x03
 576 #define  VI_ROP_ChromaKey                       0x05
 577 #define  VI_ROP_NotChromaKey                    0x0A
 578 #define  VI_ROP_Always                          0x0F
 579
 580
 581 /* Video registers (559x, 6326 and 530/620) --------------- */
 582 #define  Index_VI6326_Passwd                        0x80
 583
 584 /* Video overlay horizontal start/end, unit=screen pixels */
 585 #define  Index_VI6326_Win_Hor_Disp_Start_Low        0x81
 586 #define  Index_VI6326_Win_Hor_Disp_End_Low          0x82
 587 #define  Index_VI6326_Win_Hor_Over                  0x83 /* Overflow */
 588
 589 /* Video overlay vertical start/end, unit=screen pixels */
 590 #define  Index_VI6326_Win_Ver_Disp_Start_Low        0x84
 591 #define  Index_VI6326_Win_Ver_Disp_End_Low          0x85
 592 #define  Index_VI6326_Win_Ver_Over                  0x86 /* Overflow */
 593
 594 /* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=dword */
 595 #define  Index_VI6326_Disp_Y_Buf_Start_Low          0x8A
 596 #define  Index_VI6326_Disp_Y_Buf_Start_Middle       0x8B
 597 #define  Index_VI6326_Disp_Capt_Y_Buf_Start_High    0x89 /* 6326: 7:4 display, 3:0 capture */
 598                                                          /* 530/620: 7:3 display. 2:0 reserved */
 599 /* End address of Y plane (in 16k unit) - 6326 ONLY */
 600 #define  Index_VI6326_Disp_Y_End                    0x8D
 601
 602 /* U Plane (4:2:0) buffer start address, unit=dword */
 603 #define  Index_VI6326_U_Buf_Start_Low               0xB7
 604 #define  Index_VI6326_U_Buf_Start_Middle            0xB8
 605
 606 /* V Plane (4:2:0) buffer start address, unit=dword */
 607 #define  Index_VI6326_V_Buf_Start_Low               0xBA
 608 #define  Index_VI6326_V_Buf_Start_Middle            0xBB
 609
 610 /* U/V plane start address overflow bits 19:16 */
 611 #define  Index_VI6326_UV_Buf_Start_High             0xB9
 612
 613 /* Pitch for Y, UV Planes, unit=dword(6326 & 530/620) */
 614 #define  Index_VI6326_Disp_Y_Buf_Pitch_Low          0x8C  /* 7:0 */
 615 #define  Index_VI6326_Disp_Y_Buf_Pitch_High         0x8E  /* 11:8 (3:0 here) */
 616
 617 #define  Index_VI6326_Disp_UV_Buf_Pitch_Low         0xBC  /* 7:0 */
 618 #define  Index_VI6326_Disp_UV_Buf_Pitch_High        0xBD  /* 11:8 (3:0 here) */
 619
 620 /* Scaling control registers */
 621 #define  Index_VI6326_Hor_Scale                     0x92
 622 #define  Index_VI6326_Hor_Scale_Integer             0x94
 623 #define  Index_VI6326_Ver_Scale                     0x93
 624
 625 /* Playback line buffer control */
 626 #define  Index_VI6326_Play_Threshold_Low            0x9E
 627 #define  Index_VI6326_Play_Threshold_High           0x9F
 628 #define  Index_VI6326_Line_Buffer_Size              0xA0 /* 530 & 6326: quad-word */
 629
 630 /* Destination color key */
 631 #define  Index_VI6326_Overlay_ColorKey_Red_Min      0x97
 632 #define  Index_VI6326_Overlay_ColorKey_Green_Min    0x96
 633 #define  Index_VI6326_Overlay_ColorKey_Blue_Min     0x95
 634 #define  Index_VI6326_Overlay_ColorKey_Red_Max      0xA3
 635 #define  Index_VI6326_Overlay_ColorKey_Green_Max    0xA2
 636 #define  Index_VI6326_Overlay_ColorKey_Blue_Max     0xA1
 637
 638 /* Source color key */
 639 #define  Index_VI6326_Overlay_ChromaKey_Red_Y_Min   0x9C
 640 #define  Index_VI6326_Overlay_ChromaKey_Green_U_Min 0x9B
 641 #define  Index_VI6326_Overlay_ChromaKey_Blue_V_Min  0x9A
 642 #define  Index_VI6326_Overlay_ChromaKey_Red_Y_Max   0xA6
 643 #define  Index_VI6326_Overlay_ChromaKey_Green_U_Max 0xA5
 644 #define  Index_VI6326_Overlay_ChromaKey_Blue_V_Max  0xA4
 645
 646 /* Contrast enhancement and brightness control */
 647 #define  Index_VI6326_Contrast_Factor               0xB3
 648 #define  Index_VI6326_Brightness                    0xB4
 649 #define  Index_VI6326_Contrast_Enh_Ctrl             0xB5
 650
 651 /* Alpha */
 652 #define  Index_VI6326_AlphaGraph                    0xA7
 653 #define  Index_VI6326_AlphaVideo                    0xA8
 654
 655 #define  Index_VI6326_Key_Overlay_OP                0xA9
 656
 657 #define  Index_VI6326_Control_Misc0                 0x98
 658 #define  Index_VI6326_Control_Misc1                 0x99  /* (Datasheet: 6326 ONLY - not correct?) */
 659 #define  Index_VI6326_Control_Misc3                 0x9D
 660 #define  Index_VI6326_Control_Misc4                 0xB6
 661 #define  Index_VI6326_VideoFormatSelect             Index_VI6326_Ver_Scale
 662 #define  Index_VI6326_Control_Misc5                 0xBE  /* (Datasheet: 530/620 ONLY - not correct) */
 663 #define  Index_VI6326_Control_Misc6                 0xB2  /* 5597 and 6326 only! */
 664
 665 /* What is this?  not a register, obviously */
 666 #define  Index_VI6326_FIFO_Max                      0x3F
 667
 668 /* Bits (and helpers) for Index_VI6326_Control_Misc0 */
 669 #define  VI6326_Misc0_EnableCapture             0x01  /* 1 = on, 0 = off (6326 only) */
 670 #define  VI6326_Misc0_EnableOverlay             0x02  /* 1 = on, 0 = off */
 671 #define  VI6326_Misc0_VideoOnly                 0x10  /* 1 = video only, 0 = gfx + video */
 672 #define  VI6326_Misc0_CaptureInterlace          0x20  /* 1 = capture data is interlace, 0 = not (6326 only) */
 673 #define  VI6326_Misc0_VideoFormat               0x40  /* 1 = YUV, 0 = RGB */
 674 #define  VI6326_Misc0_FieldPolarity             0x80  /* 1 = *Odd / Even, 0 = Odd / *Even (6326 only) */
 675
 676 /* Bits for Index_VI6326_Control_Misc1 (ALL 6326 ONLY) */
 677 #define  VI6326_Misc1_EnableYUVCapture          0x01  /* 0 = RGB, 1 = YUV */
 678 #define  VI6326_Misc1_EnableCaptureDithering    0x02  /* 0 = disable, 1 = enable */
 679 #define  VI6326_Misc1_CaptureFormat555          0x04  /* 1 = 555, 0 = 565 */
 680 #define  VI6326_Misc1_FilterModeMask            0x38
 681 #define  VI6326_Misc1_FilterMode0               0x00  /* 1 */
 682 #define  VI6326_Misc1_FilterMode1               0x08  /* 1/8(1+3z^-1+3z^-2+z^-3)*/
 683 #define  VI6326_Misc1_FilterMode2               0x10  /* 1/4(1+2z^-1+z^-2) */
 684 #define  VI6326_Misc1_FilterMode3               0x18  /* 1/2(1+z^-1) */
 685 #define  VI6326_Misc1_FilterMode4               0x20  /* 1/8(1+2z^-1+2z^-2+2z^-3+z^-4) */
 686 #define  VI6326_Misc1_EnableVBSyncIRQ           0x40  /* 1 = Enable IRQ on vertical blank */
 687 #define  VI6326_Misc1_ClearVBSyncIRQ            0x80  /* Clear pending irq */
 688
 689 /* Bits for Index_VI6326_Control_Misc3 */
 690 #define  VI6326_Misc3_UVCaptureFormat           0x01  /* 1 = 2's complement, 0 = CCIR 601 (6326 only) */
 691 #define  VI6326_Misc3_UVOverlayFormat           0x02  /* 1 = 2's complement, 0 = CCIR 601 */
 692 #define  VI6326_Misc3_ChromaKeyFormat           0x04  /* 1 = YUV, 0 = RGB */
 693 #define  VI6326_Misc3_VMIAccess                 0x08  /* 1 = enable, 0 = disable (6326 only) */
 694 #define  VI6326_Misc3_VMIEnable                 0x10  /* 1 = enable, 0 = disable (6326 only) */
 695 #define  VI6326_Misc3_VMIIRQ                    0x20  /* 1 = enable, 0 = disable (6326 only) */
 696 #define  VI6326_Misc3_BT819A                    0x40  /* 1 = enable, 0 = disable (6326 only) */
 697 #define  VI6326_Misc3_SystemMemFB               0x80  /* 1 = enable, 0 = disable (6326 only) */
 698
 699 /* Bits for Index_VI6326_Control_Misc4 */
 700 #define  VI6326_Misc4_CPUVideoFormatMask        0x03
 701 #define  VI6326_Misc4_CPUVideoFormatRGB555      0x00
 702 #define  VI6326_Misc4_CPUVideoFormatYUV422      0x01
 703 #define  VI6326_Misc4_CPUVideoFormatRGB565      0x02
 704 #define  VI6326_Misc4_EnableYUV420              0x04  /* 1 = enable, 0 = disable */
 705 /* #define WHATISTHIS                           0x40  */
 706
 707 /* Bits for Index_VI6326_Control_Misc5 (all 530/620 only) */
 708 #define  VI6326_Misc5_LineBufferMerge           0x10  /* 0 = disable, 1=enable */
 709 #define  VI6326_Misc5_VPlaneBit20               0x04
 710 #define  VI6326_Misc5_UPlaneBit20               0x02
 711
 712 /* Bits for Index_VI6326_Control_Misc6  (5597 and 6326 only) */
 713 #define  VI6326_Misc6_Decimation                0x80  /* 0=disable 1=enable video decimation */
 714
 715 /* Video format selection */
 716 #define  VI_6326_VideoUYVY422                   0x00
 717 #define  VI_6326_VideoVYUY422                   0x40
 718 #define  VI_6326_VideoYUYV422                   0x80
 719 #define  VI_6326_VideoYVYU422                   0xC0
 720 #define  VI_6326_VideoRGB555                    0x00
 721 #define  VI_6326_VideoRGB565                    0x40
 722
 723 /* Values for Index_VI6326_Key_Overlay_OP */
 724 #define  VI6326_ROP_Never                       0x00
 725 #define  VI6326_ROP_DestKey                     0x03
 726 #define  VI6326_ROP_Always                      0x0F
 727
 728 /* --- end of 6326 video registers ---------------------------------- */
 729
 730 /* TV register base (6326 only) */
 731 #define  Index_TV6326_TVOutIndex                    0xE0
 732 #define  Index_TV6326_TVOutData                     0xE1
 733
 734 /* mmio registers for video */
 735 #define REG_PRIM_CRT_COUNTER    0x8514
 736
 737 /* MPEG MMIO registers (630 and later) ----------------------------------------- */
 738
 739 /* Not public (yet?) */
 740
 741
 742 #endif  /* SIS_REGS_H_ */
 743
 744