src/sis_regs.h

   1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/sis/sis_regs.h,v 1.27 2004/01/23 22:29:05 twini Exp $ */
   2 /*
   3  * Register definitions for old and 300 series
   4  *
   5  * Copyright (C) 2001-2004 by Thomas Winischhofer, Vienna, Austria
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1) Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2) Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3) All advertising materials mentioning features or use of this software
  16  *    must display the following acknowledgement: "This product includes
  17  *    software developed by Thomas Winischhofer, Vienna, Austria."
  18  * 4) The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESSED OR
  22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  23  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  * Old series register definitions
  33  * Copyright (C) 1998, 1999 by Alan Hourihane, Wigan, England.
  34  *
  35  * Authors:     Thomas Winischhofer <thomas@winischhofer.net>
  36  *              Alan Hourihane
  37  *
  38  */
  39
  40 /* For general use --------------------------------------------------------------- */
  41
  42 #define inSISREG(base)          inb(base)
  43 #define outSISREG(base,val)     outb(base,val)
  44 #define orSISREG(base,val)      do { \
  45                       unsigned char __Temp = inb(base); \
  46                       outSISREG(base, __Temp | (val)); \
  47                     } while (0)
  48 #define andSISREG(base,val)     do { \
  49                       unsigned char __Temp = inb(base); \
  50                       outSISREG(base, __Temp & (val)); \
  51                     } while (0)
  52
  53 #define inSISIDXREG(base,idx,var)   do { \
  54                       outb(base,idx); var=inb((base)+1); \
  55                     } while (0)
  56 #define outSISIDXREG(base,idx,val)  do { \
  57                       outb(base,idx); outb((base)+1,val); \
  58                     } while (0)
  59 #define orSISIDXREG(base,idx,val)   do { \
  60                       unsigned char __Temp; \
  61                       outb(base,idx);   \
  62                       __Temp = inb((base)+1)|(val); \
  63                       outSISIDXREG(base,idx,__Temp); \
  64                     } while (0)
  65 #define andSISIDXREG(base,idx,and)  do { \
  66                       unsigned char __Temp; \
  67                       outb(base,idx);   \
  68                       __Temp = inb((base)+1)&(and); \
  69                       outSISIDXREG(base,idx,__Temp); \
  70                     } while (0)
  71 #define setSISIDXREG(base,idx,and,or)   do { \
  72                       unsigned char __Temp; \
  73                       outb(base,idx);   \
  74                       __Temp = (inb((base)+1)&(and))|(or); \
  75                       outSISIDXREG(base,idx,__Temp); \
  76                     } while (0)
  77
  78 #define BITMASK(h,l)    (((unsigned)(1U << ((h)-(l)+1))-1)<<(l))
  79 #define GENMASK(mask)   BITMASK(1?mask,0?mask)
  80
  81 #define GETBITS(var,mask)       (((var) & GENMASK(mask)) >> (0?mask))
  82 #define SETBITS(val,mask)       ((val) << (0?mask))
  83 #define SETBIT(n)               (1<<(n))
  84
  85 #define GETBITSTR(val,from,to)  ((GETBITS(val,from)) << (0?to))
  86 #define SETVARBITS(var,val,from,to) (((var)&(~(GENMASK(to)))) | \
  87                                     GETBITSTR(val,from,to))
  88 #define GETVAR8(var)        ((var)&0xFF)
  89 #define SETVAR8(var,val)    (var) =  GETVAR8(val)
  90
  91 #define AROFFSET        0x40
  92 #define ARROFFSET       0x41
  93 #define GROFFSET        0x4e
  94 #define SROFFSET        0x44
  95 #define CROFFSET        0x54
  96 #define MISCROFFSET     0x4c
  97 #define MISCWOFFSET     0x42
  98 #define INPUTSTATOFFSET 0x5A
  99 #define PART1OFFSET     0x04
 100 #define PART2OFFSET     0x10
 101 #define PART3OFFSET     0x12
 102 #define PART4OFFSET     0x14
 103 #define PART5OFFSET     0x16
 104 #define CAPTUREOFFSET   0x00
 105 #define VIDEOOFFSET     0x02
 106 #define COLREGOFFSET    0x48
 107 #define PELMASKOFFSET   0x46
 108
 109 #define SISAR       pSiS->RelIO + AROFFSET
 110 #define SISARR      pSiS->RelIO + ARROFFSET
 111 #define SISGR       pSiS->RelIO + GROFFSET
 112 #define SISSR       pSiS->RelIO + SROFFSET
 113 #define SISCR       pSiS->RelIO + CROFFSET
 114 #define SISMISCR    pSiS->RelIO + MISCROFFSET
 115 #define SISMISCW    pSiS->RelIO + MISCWOFFSET
 116 #define SISINPSTAT  pSiS->RelIO + INPUTSTATOFFSET
 117 #define SISPART1    pSiS->RelIO + PART1OFFSET
 118 #define SISPART2    pSiS->RelIO + PART2OFFSET
 119 #define SISPART3    pSiS->RelIO + PART3OFFSET
 120 #define SISPART4    pSiS->RelIO + PART4OFFSET
 121 #define SISPART5    pSiS->RelIO + PART5OFFSET
 122 #define SISCAP      pSiS->RelIO + CAPTUREOFFSET
 123 #define SISVID      pSiS->RelIO + VIDEOOFFSET
 124 #define SISCOLIDX   pSiS->RelIO + COLREGOFFSET
 125 #define SISCOLDATA  pSiS->RelIO + COLREGOFFSET + 1
 126 #define SISCOL2IDX  SISPART5
 127 #define SISCOL2DATA SISPART5 + 1
 128 #define SISPEL      pSiS->RelIO + PELMASKOFFSET
 129
 130 #define vc_index_offset    CAPTUREOFFSET  /* Video capture - unused */
 131 #define vc_data_offset     (CAPTUREOFFSET + 1)
 132 #define vi_index_offset    VIDEOOFFSET
 133 #define vi_data_offset     (VIDEOOFFSET + 1)
 134 #define crt2_index_offset  PART1OFFSET
 135 #define crt2_port_offset   (PART1OFFSET + 1)
 136 #define sr_index_offset    SROFFSET
 137 #define sr_data_offset     (SROFFSET + 1)
 138 #define cr_index_offset    CROFFSET
 139 #define cr_data_offset     (CROFFSET + 1)
 140 #define input_stat         INPUTSTATOFFSET
 141
 142 /* For old chipsets (5597/5598, 6326, 530/620) ------------ */
 143 /* SR (3C4) */
 144 #define BankReg 0x06
 145 #define ClockReg 0x07
 146 #define CPUThreshold 0x08
 147 #define CRTThreshold 0x09
 148 #define CRTCOff 0x0A
 149 #define DualBanks 0x0B
 150 #define MMIOEnable 0x0B
 151 #define RAMSize 0x0C
 152 #define Mode64 0x0C
 153 #define ExtConfStatus1 0x0E
 154 #define ClockBase 0x13
 155 #define LinearAdd0 0x20
 156 #define LinearAdd1 0x21
 157 #define GraphEng 0x27
 158 #define MemClock0 0x28
 159 #define MemClock1 0x29
 160 #define XR2A 0x2A
 161 #define XR2B 0x2B
 162 #define TurboQueueBase 0x2C
 163 #define FBSize 0x2F
 164 #define ExtMiscCont5 0x34
 165 #define ExtMiscCont9 0x3C
 166
 167 /* 3x4 */
 168 #define Offset 0x13
 169
 170 /* SiS Registers for 300, 540, 630, 730, 315, 550, 650, 740 ---------------------- */
 171
 172 /* VGA standard register */
 173 #define  Index_SR_Graphic_Mode                  0x06
 174 #define  Index_SR_RAMDAC_Ctrl                   0x07
 175 #define  Index_SR_Threshold_Ctrl1               0x08
 176 #define  Index_SR_Threshold_Ctrl2               0x09
 177 #define  Index_SR_Misc_Ctrl                     0x0F
 178 #define  Index_SR_DDC                           0x11
 179 #define  Index_SR_Feature_Connector_Ctrl        0x12
 180 #define  Index_SR_DRAM_Sizing                   0x14
 181 #define  Index_SR_DRAM_State_Machine_Ctrl       0x15
 182 #define  Index_SR_AGP_PCI_State_Machine         0x21
 183 #define  Index_SR_Internal_MCLK0                0x28
 184 #define  Index_SR_Internal_MCLK1                0x29
 185 #define  Index_SR_Internal_DCLK1                0x2B
 186 #define  Index_SR_Internal_DCLK2                0x2C
 187 #define  Index_SR_Internal_DCLK3                0x2D
 188 #define  Index_SR_Ext_Clock_Sel                 0x32
 189 #define  Index_SR_Int_Status                    0x34
 190 #define  Index_SR_Int_Enable                    0x35
 191 #define  Index_SR_Int_Reset                     0x36
 192 #define  Index_SR_Power_On_Trap                 0x38
 193 #define  Index_SR_Power_On_Trap2                0x39
 194 #define  Index_SR_Power_On_Trap3                0x3A
 195
 196 /* video registers (300/630/730/315/550/650/740 only) */
 197 #define  Index_VI_Passwd                        0x00
 198
 199 /* Video overlay horizontal start/end, unit=screen pixels */
 200 #define  Index_VI_Win_Hor_Disp_Start_Low        0x01
 201 #define  Index_VI_Win_Hor_Disp_End_Low          0x02
 202 #define  Index_VI_Win_Hor_Over                  0x03 /* Overflow */
 203
 204 /* Video overlay vertical start/end, unit=screen pixels */
 205 #define  Index_VI_Win_Ver_Disp_Start_Low        0x04
 206 #define  Index_VI_Win_Ver_Disp_End_Low          0x05
 207 #define  Index_VI_Win_Ver_Over                  0x06 /* Overflow */
 208
 209 /* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=word */
 210 #define  Index_VI_Disp_Y_Buf_Start_Low          0x07
 211 #define  Index_VI_Disp_Y_Buf_Start_Middle       0x08
 212 #define  Index_VI_Disp_Y_Buf_Start_High         0x09
 213
 214 /* U Plane (4:2:0) buffer start address, unit=word */
 215 #define  Index_VI_U_Buf_Start_Low               0x0A
 216 #define  Index_VI_U_Buf_Start_Middle            0x0B
 217 #define  Index_VI_U_Buf_Start_High              0x0C
 218
 219 /* V Plane (4:2:0) buffer start address, unit=word */
 220 #define  Index_VI_V_Buf_Start_Low               0x0D
 221 #define  Index_VI_V_Buf_Start_Middle            0x0E
 222 #define  Index_VI_V_Buf_Start_High              0x0F
 223
 224 /* Pitch for Y, UV Planes, unit=word */
 225 #define  Index_VI_Disp_Y_Buf_Pitch_Low          0x10
 226 #define  Index_VI_Disp_UV_Buf_Pitch_Low         0x11
 227 #define  Index_VI_Disp_Y_UV_Buf_Pitch_Middle    0x12
 228
 229 /* What is this ? */
 230 #define  Index_VI_Disp_Y_Buf_Preset_Low         0x13
 231 #define  Index_VI_Disp_Y_Buf_Preset_Middle      0x14
 232
 233 #define  Index_VI_UV_Buf_Preset_Low             0x15
 234 #define  Index_VI_UV_Buf_Preset_Middle          0x16
 235 #define  Index_VI_Disp_Y_UV_Buf_Preset_High     0x17
 236
 237 /* Scaling control registers */
 238 #define  Index_VI_Hor_Post_Up_Scale_Low         0x18
 239 #define  Index_VI_Hor_Post_Up_Scale_High        0x19
 240 #define  Index_VI_Ver_Up_Scale_Low              0x1A
 241 #define  Index_VI_Ver_Up_Scale_High             0x1B
 242 #define  Index_VI_Scale_Control                 0x1C
 243
 244 /* Playback line buffer control */
 245 #define  Index_VI_Play_Threshold_Low            0x1D
 246 #define  Index_VI_Play_Threshold_High           0x1E
 247 #define  Index_VI_Line_Buffer_Size              0x1F
 248
 249 /* Destination color key */
 250 #define  Index_VI_Overlay_ColorKey_Red_Min      0x20
 251 #define  Index_VI_Overlay_ColorKey_Green_Min    0x21
 252 #define  Index_VI_Overlay_ColorKey_Blue_Min     0x22
 253 #define  Index_VI_Overlay_ColorKey_Red_Max      0x23
 254 #define  Index_VI_Overlay_ColorKey_Green_Max    0x24
 255 #define  Index_VI_Overlay_ColorKey_Blue_Max     0x25
 256
 257 /* Source color key, YUV color space */
 258 #define  Index_VI_Overlay_ChromaKey_Red_Y_Min   0x26
 259 #define  Index_VI_Overlay_ChromaKey_Green_U_Min 0x27
 260 #define  Index_VI_Overlay_ChromaKey_Blue_V_Min  0x28
 261 #define  Index_VI_Overlay_ChromaKey_Red_Y_Max   0x29
 262 #define  Index_VI_Overlay_ChromaKey_Green_U_Max 0x2A
 263 #define  Index_VI_Overlay_ChromaKey_Blue_V_Max  0x2B
 264
 265 /* Contrast enhancement and brightness control */
 266 #define  Index_VI_Contrast_Factor               0x2C    /* obviously unused/undefined */
 267 #define  Index_VI_Brightness                    0x2D
 268 #define  Index_VI_Contrast_Enh_Ctrl             0x2E
 269
 270 #define  Index_VI_Key_Overlay_OP                0x2F
 271
 272 #define  Index_VI_Control_Misc0                 0x30
 273 #define  Index_VI_Control_Misc1                 0x31
 274 #define  Index_VI_Control_Misc2                 0x32
 275
 276 /* TW: Subpicture registers */
 277 #define  Index_VI_SubPict_Buf_Start_Low         0x33
 278 #define  Index_VI_SubPict_Buf_Start_Middle      0x34
 279 #define  Index_VI_SubPict_Buf_Start_High        0x35
 280
 281 /* TW: What is this ? */
 282 #define  Index_VI_SubPict_Buf_Preset_Low        0x36
 283 #define  Index_VI_SubPict_Buf_Preset_Middle     0x37
 284
 285 /* TW: Subpicture pitch, unit=16 bytes */
 286 #define  Index_VI_SubPict_Buf_Pitch             0x38
 287
 288 /* TW: Subpicture scaling control */
 289 #define  Index_VI_SubPict_Hor_Scale_Low         0x39
 290 #define  Index_VI_SubPict_Hor_Scale_High        0x3A
 291 #define  Index_VI_SubPict_Vert_Scale_Low        0x3B
 292 #define  Index_VI_SubPict_Vert_Scale_High       0x3C
 293
 294 #define  Index_VI_SubPict_Scale_Control         0x3D
 295 /* (0x40 = enable/disable subpicture) */
 296
 297 /* TW: Subpicture line buffer control */
 298 #define  Index_VI_SubPict_Threshold             0x3E
 299
 300 /* TW: What is this? */
 301 #define  Index_VI_FIFO_Max                      0x3F
 302
 303 /* TW: Subpicture palette; 16 colors, total 32 bytes address space */
 304 #define  Index_VI_SubPict_Pal_Base_Low          0x40
 305 #define  Index_VI_SubPict_Pal_Base_High         0x41
 306
 307 /* I wish I knew how to use these ... */
 308 #define  Index_MPEG_Read_Ctrl0                  0x60    /* MPEG auto flip */
 309 #define  Index_MPEG_Read_Ctrl1                  0x61    /* MPEG auto flip */
 310 #define  Index_MPEG_Read_Ctrl2                  0x62    /* MPEG auto flip */
 311 #define  Index_MPEG_Read_Ctrl3                  0x63    /* MPEG auto flip */
 312
 313 /* TW: MPEG AutoFlip scale */
 314 #define  Index_MPEG_Ver_Up_Scale_Low            0x64
 315 #define  Index_MPEG_Ver_Up_Scale_High           0x65
 316
 317 #define  Index_MPEG_Y_Buf_Preset_Low            0x66
 318 #define  Index_MPEG_Y_Buf_Preset_Middle         0x67
 319 #define  Index_MPEG_UV_Buf_Preset_Low           0x68
 320 #define  Index_MPEG_UV_Buf_Preset_Middle        0x69
 321 #define  Index_MPEG_Y_UV_Buf_Preset_High        0x6A
 322
 323 /* TW: The following registers only exist on the 315 series */
 324
 325 /* TW: Bit 16:24 of Y_U_V buf start address */
 326 #define  Index_VI_Y_Buf_Start_Over              0x6B
 327 #define  Index_VI_U_Buf_Start_Over              0x6C
 328 #define  Index_VI_V_Buf_Start_Over              0x6D
 329
 330 #define  Index_VI_Disp_Y_Buf_Pitch_High         0x6E
 331 #define  Index_VI_Disp_UV_Buf_Pitch_High        0x6F
 332
 333 /* Hue and saturation */
 334 #define  Index_VI_Hue                           0x70
 335 #define  Index_VI_Saturation                    0x71
 336
 337 #define  Index_VI_SubPict_Start_Over            0x72
 338 #define  Index_VI_SubPict_Buf_Pitch_High        0x73
 339
 340 #define  Index_VI_Control_Misc3                 0x74
 341
 342 /* Bits in Scale control (0x1c) */
 343 #define  VI_Scale_Ctrl_Horiz_DDA                0x20
 344 #define  VI_Scale_Ctrl_Vert_DDA                 0x40
 345
 346 /* TW: Bits (and helpers) for Index_VI_Control_Misc0 */
 347 #define  VI_Misc0_Enable_Overlay                0x02
 348 #define  VI_Misc0_420_Plane_Enable              0x04 /* Select Plane or Packed mode */
 349 #define  VI_Misc0_422_Enable                    0x20 /* Select 422 or 411 mode */
 350 #define  VI_Misc0_Fmt_YVU420P                   0x0C /* YUV420 Planar (I420, YV12) */
 351 #define  VI_Misc0_Fmt_YUYV                      0x28 /* YUYV Packed (=YUY2) */
 352 #define  VI_Misc0_Fmt_UYVY                      0x08 /* (UYVY) */
 353 #define  VI_Misc0_Fmt_YVYU                      0x38 /* (YVYU) (315 series only?) */
 354 #define  VI_Misc0_Fmt_NV21                      0x5c /* (330 series only?) */
 355 #define  VI_Misc0_Fmt_NV12                      0x4c /* (330 series only?) */
 356 #define  VI_Misc0_ChromaKeyRGBYUV               0x40 /* 300 series only: 0 = RGB, 1 = YUV */
 357
 358 /* TW: Bits for Index_VI_Control_Misc1 */
 359 #define  VI_Misc1_DisableGraphicsAtOverlay      0x01 /* Disables graphics display in overlay area */
 360 #define  VI_Misc1_BOB_Enable                    0x02 /* Enable BOB de-interlacer */
 361 #define  VI_Misc1_Line_Merge                    0x04
 362 #define  VI_Misc1_Field_Mode                    0x08 /* ? */
 363 #define  VI_Misc1_Non_Interleave                0x10 /* ? 0x20 ? - Odd and Even fields are not interleaved ? */
 364 #define  VI_Misc1_Buf_Addr_Lock                 0x20 /* 315 series only? */
 365 /* #define  VI_Misc1_?                          0x40  */
 366 /* #define  VI_Misc1_?                          0x80  */
 367
 368 /* TW: Bits for Index_VI_Control_Misc2 */
 369 #define  VI_Misc2_Select_Video2                 0x01
 370 #define  VI_Misc2_Video2_On_Top                 0x02
 371 #define  VI_Misc2_DisableGraphics               0x04 /* Disable graphics display entirely (<= 650 only, not >= M650, 651) */
 372 #define  VI_Misc2_Vertical_Interpol             0x08
 373 #define  VI_Misc2_Dual_Line_Merge               0x10  /* dual-overlay chips only; "dual video windows relative line buffer merge" */
 374 #define  VI_Misc2_All_Line_Merge                0x20  /* > 315 only */
 375 #define  VI_Misc2_Auto_Flip_Enable              0x40
 376 #define  VI_Misc2_Video_Reg_Write_Enable        0x80  /* 315 series only? */
 377
 378 /* TW: Bits for Index_VI_Control_Misc3 */
 379 #define  VI_Misc3_Submit_Video_1                0x01  /* AKA "address ready" */
 380 #define  VI_Misc3_Submit_Video_2                0x02  /* AKA "address ready" */
 381 #define  VI_Misc3_Submit_SubPict                0x04  /* AKA "address ready" */
 382
 383 /* TW: Values for Index_VI_Key_Overlay_OP (0x2F) */
 384 #define  VI_ROP_Never                           0x00
 385 #define  VI_ROP_DestKey                         0x03
 386 #define  VI_ROP_ChromaKey                       0x05
 387 #define  VI_ROP_NotChromaKey                    0x0A
 388 #define  VI_ROP_Always                          0x0F
 389
 390
 391 /* video registers (6326 and 530/620) --------------- */
 392 #define  Index_VI6326_Passwd                        0x80
 393
 394 /* Video overlay horizontal start/end, unit=screen pixels */
 395 #define  Index_VI6326_Win_Hor_Disp_Start_Low        0x81
 396 #define  Index_VI6326_Win_Hor_Disp_End_Low          0x82
 397 #define  Index_VI6326_Win_Hor_Over                  0x83 /* Overflow */
 398
 399 /* Video overlay vertical start/end, unit=screen pixels */
 400 #define  Index_VI6326_Win_Ver_Disp_Start_Low        0x84
 401 #define  Index_VI6326_Win_Ver_Disp_End_Low          0x85
 402 #define  Index_VI6326_Win_Ver_Over                  0x86 /* Overflow */
 403
 404 /* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=dword */
 405 #define  Index_VI6326_Disp_Y_Buf_Start_Low          0x8A
 406 #define  Index_VI6326_Disp_Y_Buf_Start_Middle       0x8B
 407 #define  Index_VI6326_Disp_Capt_Y_Buf_Start_High    0x89 /* 6326: 7:4 display, 3:0 capture */
 408                                                          /* 530/620: 7:3 display. 2:0 reserved */
 409 /* End address of Y plane (in 16k unit) - 6326 ONLY */
 410 #define  Index_VI6326_Disp_Y_End                    0x8D
 411
 412 /* U Plane (4:2:0) buffer start address, unit=dword */
 413 #define  Index_VI6326_U_Buf_Start_Low               0xB7
 414 #define  Index_VI6326_U_Buf_Start_Middle            0xB8
 415
 416 /* V Plane (4:2:0) buffer start address, unit=dword */
 417 #define  Index_VI6326_V_Buf_Start_Low               0xBA
 418 #define  Index_VI6326_V_Buf_Start_Middle            0xBB
 419
 420 /* U/V plane start address overflow bits 19:16 */
 421 #define  Index_VI6326_UV_Buf_Start_High             0xB9
 422
 423 /* Pitch for Y, UV Planes, unit=dword(6326 & 530/620) */
 424 #define  Index_VI6326_Disp_Y_Buf_Pitch_Low          0x8C  /* 7:0 */
 425 #define  Index_VI6326_Disp_Y_Buf_Pitch_High         0x8E  /* 11:8 (3:0 here) */
 426
 427 #define  Index_VI6326_Disp_UV_Buf_Pitch_Low         0xBC  /* 7:0 */
 428 #define  Index_VI6326_Disp_UV_Buf_Pitch_High        0xBD  /* 11:8 (3:0 here) */
 429
 430 /* Scaling control registers */
 431 #define  Index_VI6326_Hor_Scale                     0x92
 432 #define  Index_VI6326_Hor_Scale_Integer             0x94
 433 #define  Index_VI6326_Ver_Scale                     0x93
 434
 435 /* Playback line buffer control */
 436 #define  Index_VI6326_Play_Threshold_Low            0x9E
 437 #define  Index_VI6326_Play_Threshold_High           0x9F
 438 #define  Index_VI6326_Line_Buffer_Size              0xA0 /* 530 & 6326: quad-word */
 439
 440 /* Destination color key */
 441 #define  Index_VI6326_Overlay_ColorKey_Red_Min      0x97
 442 #define  Index_VI6326_Overlay_ColorKey_Green_Min    0x96
 443 #define  Index_VI6326_Overlay_ColorKey_Blue_Min     0x95
 444 #define  Index_VI6326_Overlay_ColorKey_Red_Max      0xA3
 445 #define  Index_VI6326_Overlay_ColorKey_Green_Max    0xA2
 446 #define  Index_VI6326_Overlay_ColorKey_Blue_Max     0xA1
 447
 448 /* Source color key */
 449 #define  Index_VI6326_Overlay_ChromaKey_Red_Y_Min   0x9C
 450 #define  Index_VI6326_Overlay_ChromaKey_Green_U_Min 0x9B
 451 #define  Index_VI6326_Overlay_ChromaKey_Blue_V_Min  0x9A
 452 #define  Index_VI6326_Overlay_ChromaKey_Red_Y_Max   0xA6
 453 #define  Index_VI6326_Overlay_ChromaKey_Green_U_Max 0xA5
 454 #define  Index_VI6326_Overlay_ChromaKey_Blue_V_Max  0xA4
 455
 456 /* Contrast enhancement and brightness control */
 457 #define  Index_VI6326_Contrast_Factor               0xB3
 458 #define  Index_VI6326_Brightness                    0xB4
 459 #define  Index_VI6326_Contrast_Enh_Ctrl             0xB5
 460
 461 /* Alpha */
 462 #define  Index_VI6326_AlphaGraph                    0xA7
 463 #define  Index_VI6326_AlphaVideo                    0xA8
 464
 465 #define  Index_VI6326_Key_Overlay_OP                0xA9
 466
 467 #define  Index_VI6326_Control_Misc0                 0x98
 468 #define  Index_VI6326_Control_Misc1                 0x99  /* (Datasheet: 6326 ONLY - not correct?) */
 469 #define  Index_VI6326_Control_Misc3                 0x9D
 470 #define  Index_VI6326_Control_Misc4                 0xB6
 471 #define  Index_VI6326_VideoFormatSelect             Index_VI6326_Ver_Scale
 472 #define  Index_VI6326_Control_Misc5                 0xBE  /* (Datasheet: 530/620 ONLY - not correct) */
 473 #define  Index_VI6326_Control_Misc6                 0xB2  /* 5597 and 6326 only! */
 474
 475 /* TW: What is this?  not a register, obviously */
 476 #define  Index_VI6326_FIFO_Max                      0x3F
 477
 478 /* TW: Bits (and helpers) for Index_VI6326_Control_Misc0 */
 479 #define  VI6326_Misc0_EnableCapture             0x01  /* 1 = on, 0 = off (6326 only) */
 480 #define  VI6326_Misc0_EnableOverlay             0x02  /* 1 = on, 0 = off */
 481 #define  VI6326_Misc0_VideoOnly                 0x10  /* 1 = video only, 0 = gfx + video */
 482 #define  VI6326_Misc0_CaptureInterlace          0x20  /* 1 = capture data is interlace, 0 = not (6326 only) */
 483 #define  VI6326_Misc0_VideoFormat               0x40  /* 1 = YUV, 0 = RGB */
 484 #define  VI6326_Misc0_FieldPolarity             0x80  /* 1 = *Odd / Even, 0 = Odd / *Even (6326 only) */
 485
 486 /* TW: Bits for Index_VI6326_Control_Misc1 (ALL 6326 ONLY) */
 487 #define  VI6326_Misc1_EnableYUVCapture          0x01  /* 0 = RGB, 1 = YUV */
 488 #define  VI6326_Misc1_EnableCaptureDithering    0x02  /* 0 = disable, 1 = enable */
 489 #define  VI6326_Misc1_CaptureFormat555          0x04  /* 1 = 555, 0 = 565 */
 490 #define  VI6326_Misc1_FilterModeMask            0x38
 491 #define  VI6326_Misc1_FilterMode0               0x00  /* 1 */
 492 #define  VI6326_Misc1_FilterMode1               0x08  /* 1/8(1+3z^-1+3z^-2+z^-3)*/
 493 #define  VI6326_Misc1_FilterMode2               0x10  /* 1/4(1+2z^-1+z^-2) */
 494 #define  VI6326_Misc1_FilterMode3               0x18  /* 1/2(1+z^-1) */
 495 #define  VI6326_Misc1_FilterMode4               0x20  /* 1/8(1+2z^-1+2z^-2+2z^-3+z^-4) */
 496 #define  VI6326_Misc1_EnableVBSyncIRQ           0x40  /* 1 = Enable IRQ on vertical blank */
 497 #define  VI6326_Misc1_ClearVBSyncIRQ            0x80  /* Clear pending irq */
 498
 499 /* TW: Bits for Index_VI6326_Control_Misc3 */
 500 #define  VI6326_Misc3_UVCaptureFormat           0x01  /* 1 = 2's complement, 0 = CCIR 601 (6326 only) */
 501 #define  VI6326_Misc3_UVOverlayFormat           0x02  /* 1 = 2's complement, 0 = CCIR 601 */
 502 #define  VI6326_Misc3_ChromaKeyFormat           0x04  /* 1 = YUV, 0 = RGB */
 503 #define  VI6326_Misc3_VMIAccess                 0x08  /* 1 = enable, 0 = disable (6326 only) */
 504 #define  VI6326_Misc3_VMIEnable                 0x10  /* 1 = enable, 0 = disable (6326 only) */
 505 #define  VI6326_Misc3_VMIIRQ                    0x20  /* 1 = enable, 0 = disable (6326 only) */
 506 #define  VI6326_Misc3_BT819A                    0x40  /* 1 = enable, 0 = disable (6326 only) */
 507 #define  VI6326_Misc3_SystemMemFB               0x80  /* 1 = enable, 0 = disable (6326 only) */
 508
 509 /* TW: Bits for Index_VI6326_Control_Misc4 */
 510 #define  VI6326_Misc4_CPUVideoFormatMask        0x03
 511 #define  VI6326_Misc4_CPUVideoFormatRGB555      0x00
 512 #define  VI6326_Misc4_CPUVideoFormatYUV422      0x01
 513 #define  VI6326_Misc4_CPUVideoFormatRGB565      0x02
 514 #define  VI6326_Misc4_EnableYUV420              0x04  /* 1 = enable, 0 = disable */
 515 /** #define WHATISTHIS                          0x40  */
 516
 517 /* TW: Bits for Index_VI6326_Control_Misc5 (all 530/620 only) */
 518 #define  VI6326_Misc5_LineBufferMerge           0x10  /* 0 = disable, 1=enable */
 519 #define  VI6326_Misc5_VPlaneBit20               0x04
 520 #define  VI6326_Misc5_UPlaneBit20               0x02
 521
 522 /* TW: Bits for Index_VI6326_Control_Misc6  (5597 and 6326 only) */
 523 #define  VI6326_Misc6_Decimation                0x80  /* 0=disable 1=enable video decimation */
 524
 525 /* Video format selection */
 526 #define  VI_6326_VideoUYVY422                   0x00
 527 #define  VI_6326_VideoVYUY422                   0x40
 528 #define  VI_6326_VideoYUYV422                   0x80
 529 #define  VI_6326_VideoYVYU422                   0xC0
 530 #define  VI_6326_VideoRGB555                    0x00
 531 #define  VI_6326_VideoRGB565                    0x40
 532
 533 /* TW: Values for Index_VI6326_Key_Overlay_OP */
 534 #define  VI6326_ROP_Never                       0x00
 535 #define  VI6326_ROP_DestKey                     0x03
 536 #define  VI6326_ROP_Always                      0x0F
 537
 538 /* --- end of 6326 video registers ---------------------------------- */
 539
 540 /* TW register base (6326 only) */
 541 #define  Index_TV6326_TVOutIndex                    0xE0
 542 #define  Index_TV6326_TVOutData                     0xE1
 543
 544 /*
 545  *  CRT_2 function control register ---------------------------------
 546  */
 547 #define  Index_CRT2_FC_CONTROL                  0x00
 548 #define  Index_CRT2_FC_SCREEN_HIGH              0x04
 549 #define  Index_CRT2_FC_SCREEN_MID               0x05
 550 #define  Index_CRT2_FC_SCREEN_LOW               0x06
 551 #define  Index_CRT2_FC_ENABLE_WRITE             0x24
 552 #define  Index_CRT2_FC_VR                       0x25
 553 #define  Index_CRT2_FC_VCount                   0x27
 554 #define  Index_CRT2_FC_VCount1                  0x28
 555
 556 #define  Index_310_CRT2_FC_VR                   0x30  /* d[1] = vertical retrace */
 557 #define  Index_310_CRT2_FC_RT                   0x33  /* d[7] = retrace in progress */
 558
 559 /* video attributes - these should probably be configurable on the fly
 560  *                    so users with different desktop sizes can keep
 561  *                    captured data off the desktop
 562  */
 563 #define _VINWID                                  704
 564 #define _VINHGT                         _VINHGT_NTSC
 565 #define _VINHGT_NTSC                             240
 566 #define _VINHGT_PAL                              290
 567 #define _VIN_WINDOW                  (704 * 291 * 2)
 568 #define _VBI_WINDOW                   (704 * 64 * 2)
 569
 570 #define _VIN_FIELD_EVEN                            1
 571 #define _VIN_FIELD_ODD                             2
 572 #define _VIN_FIELD_BOTH                            4
 573
 574
 575 /* i2c registers (TW; not on 300/315 series) */
 576 #define X_INDEXREG      0x14
 577 #define X_PORTREG       0x15
 578 #define X_DATA          0x0f
 579 #define I2C_SCL         0x00
 580 #define I2C_SDA         0x01
 581 #define I2C_DELAY       10
 582
 583 /* mmio registers for video */
 584 #define REG_PRIM_CRT_COUNTER    0x8514
 585
 586 /* TW: MPEG MMIO registers (630 and later) ----------------------------------------- */
 587
 588 /* Not public (yet?) */
 589