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DRI XFree86-4_3_99_12-merge import
[xf86-video-sis/mirage.git] / src / sis_driver.h
blob03d22f36dfe6188d023ddfd764978e88ef7b2af3
1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/sis/sis_driver.h,v 1.18 2003/09/08 14:20:39 twini Exp $ */
2 /*
3 * Global data and definitions
4 *
5 * Copyright 2002, 2003 by Thomas Winischhofer, Vienna, Austria
6 *
7 * Permission to use, copy, modify, distribute, and sell this software and its
8 * documentation for any purpose is hereby granted without fee, provided that
9 * the above copyright notice appear in all copies and that both that
10 * copyright notice and this permission notice appear in supporting
11 * documentation, and that the name of the copyright holder not be used in
12 * advertising or publicity pertaining to distribution of the software without
13 * specific, written prior permission. The copyright holder makes no representations
14 * about the suitability of this software for any purpose. It is provided
15 * "as is" without express or implied warranty.
16 *
17 * THE COPYRIGHT HOLDER DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
18 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
19 * EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY SPECIAL, INDIRECT OR
20 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
21 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
22 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
23 * PERFORMANCE OF THIS SOFTWARE.
24 *
25 * Author: Thomas Winischhofer <thomas@winischhofer.net>
26 *
27 */
28
29 /* Mode numbers for 300/315/330 series */
30 const UShort ModeIndex_320x200[] = {0x59, 0x41, 0x00, 0x4f};
31 const UShort ModeIndex_320x240[] = {0x50, 0x56, 0x00, 0x53};
32 const UShort ModeIndex_320x240_FSTN[] = {0x5a, 0x5b, 0x00, 0x00}; /* FSTN */
33 const UShort ModeIndex_400x300[] = {0x51, 0x57, 0x00, 0x54};
34 const UShort ModeIndex_512x384[] = {0x52, 0x58, 0x00, 0x5c};
35 const UShort ModeIndex_640x400[] = {0x2f, 0x5d, 0x00, 0x5e};
36 const UShort ModeIndex_640x480[] = {0x2e, 0x44, 0x00, 0x62};
37 const UShort ModeIndex_720x480[] = {0x31, 0x33, 0x00, 0x35};
38 const UShort ModeIndex_720x576[] = {0x32, 0x34, 0x00, 0x36};
39 const UShort ModeIndex_768x576[] = {0x5f, 0x60, 0x00, 0x61};
40 const UShort ModeIndex_800x480[] = {0x70, 0x7a, 0x00, 0x76};
41 const UShort ModeIndex_800x600[] = {0x30, 0x47, 0x00, 0x63};
42 const UShort ModeIndex_848x480[] = {0x39, 0x3b, 0x00, 0x3e};
43 const UShort ModeIndex_856x480[] = {0x3f, 0x42, 0x00, 0x45};
44 const UShort ModeIndex_1024x768[] = {0x38, 0x4a, 0x00, 0x64};
45 const UShort ModeIndex_1024x576[] = {0x71, 0x74, 0x00, 0x77};
46 const UShort ModeIndex_1024x600[] = {0x20, 0x21, 0x00, 0x22}; /* 300 series only */
47 const UShort ModeIndex_1280x1024[] = {0x3a, 0x4d, 0x00, 0x65};
48 const UShort ModeIndex_1280x960[] = {0x7c, 0x7d, 0x00, 0x7e};
49 const UShort ModeIndex_1152x768[] = {0x23, 0x24, 0x00, 0x25}; /* 300 series only */
50 const UShort ModeIndex_1152x864[] = {0x29, 0x2a, 0x00, 0x2b};
51 const UShort ModeIndex_300_1280x768[] = {0x55, 0x5a, 0x00, 0x5b};
52 const UShort ModeIndex_310_1280x768[] = {0x23, 0x24, 0x00, 0x25};
53 const UShort ModeIndex_1280x720[] = {0x79, 0x75, 0x00, 0x78};
54 const UShort ModeIndex_1360x768[] = {0x48, 0x4b, 0x00, 0x4e};
55 const UShort ModeIndex_300_1360x1024[]= {0x67, 0x6f, 0x00, 0x72}; /* 300 series, BARCO only */
56 const UShort ModeIndex_1400x1050[] = {0x26, 0x27, 0x00, 0x28}; /* 315 series only */
57 const UShort ModeIndex_1600x1200[] = {0x3c, 0x3d, 0x00, 0x66};
58 const UShort ModeIndex_1920x1440[] = {0x68, 0x69, 0x00, 0x6b};
59 const UShort ModeIndex_300_2048x1536[]= {0x6c, 0x6d, 0x00, 0x00};
60 const UShort ModeIndex_310_2048x1536[]= {0x6c, 0x6d, 0x00, 0x6e};
61
62 /* VESA */
63 /* The following is included because there are BIOSes out there that
64 * report incomplete mode lists. These are 630 BIOS versions <2.01.2x
65 *
66 * -) VBE 3.0 on SiS300 and 315 series do not support 24 fpp modes
67 * -) Only SiS315 series support 1920x1440x32
68 */
69 /* 8 16 (24) 32 */
70 static const UShort VESAModeIndex_320x200[] = {0x138, 0x10e, 0x000, 0x000};
71 static const UShort VESAModeIndex_320x240[] = {0x132, 0x135, 0x000, 0x000};
72 static const UShort VESAModeIndex_400x300[] = {0x133, 0x136, 0x000, 0x000};
73 static const UShort VESAModeIndex_512x384[] = {0x134, 0x137, 0x000, 0x000};
74 static const UShort VESAModeIndex_640x400[] = {0x100, 0x139, 0x000, 0x000};
75 static const UShort VESAModeIndex_640x480[] = {0x101, 0x111, 0x000, 0x13a};
76 static const UShort VESAModeIndex_800x600[] = {0x103, 0x114, 0x000, 0x13b};
77 static const UShort VESAModeIndex_1024x768[] = {0x105, 0x117, 0x000, 0x13c};
78 static const UShort VESAModeIndex_1280x1024[] = {0x107, 0x11a, 0x000, 0x13d};
79 static const UShort VESAModeIndex_1600x1200[] = {0x130, 0x131, 0x000, 0x13e};
80 static const UShort VESAModeIndex_1920x1440[] = {0x13f, 0x140, 0x000, 0x141};
81
82 /* For calculating refresh rate index (CR33) */
83 static const struct _sis_vrate {
84 CARD16 idx;
85 CARD16 xres;
86 CARD16 yres;
87 CARD16 refresh;
88 BOOLEAN SiS730valid32bpp;
89 } sisx_vrate[] = {
90 {1, 320, 200, 70, TRUE},
91 {1, 320, 240, 60, TRUE},
92 {1, 400, 300, 60, TRUE},
93 {1, 512, 384, 60, TRUE},
94 {1, 640, 400, 72, TRUE},
95 {1, 640, 480, 60, TRUE}, {2, 640, 480, 72, TRUE}, {3, 640, 480, 75, TRUE},
96 {4, 640, 480, 85, TRUE}, {5, 640, 480, 100, TRUE}, {6, 640, 480, 120, TRUE},
97 {7, 640, 480, 160, FALSE}, {8, 640, 480, 200, FALSE},
98 {1, 720, 480, 60, TRUE},
99 {1, 720, 576, 58, TRUE},
100 {1, 768, 576, 58, TRUE},
101 {1, 800, 480, 60, TRUE}, {2, 800, 480, 75, TRUE}, {3, 800, 480, 85, TRUE},
102 {1, 800, 600, 56, TRUE}, {2, 800, 600, 60, TRUE}, {3, 800, 600, 72, TRUE},
103 {4, 800, 600, 75, TRUE}, {5, 800, 600, 85, TRUE}, {6, 800, 600, 105, TRUE},
104 {7, 800, 600, 120, FALSE}, {8, 800, 600, 160, FALSE},
105 {1, 848, 480, 39, TRUE}, {2, 848, 480, 60, TRUE},
106 {1, 856, 480, 39, TRUE}, {2, 856, 480, 60, TRUE},
107 {1, 1024, 576, 60, TRUE}, {2, 1024, 576, 75, TRUE}, {3, 1024, 576, 85, TRUE},
108 {1, 1024, 600, 60, TRUE},
109 {1, 1024, 768, 43, TRUE}, {2, 1024, 768, 60, TRUE}, {3, 1024, 768, 70, FALSE},
110 {4, 1024, 768, 75, FALSE}, {5, 1024, 768, 85, TRUE}, {6, 1024, 768, 100, TRUE},
111 {7, 1024, 768, 120, TRUE},
112 {1, 1152, 768, 60, TRUE},
113 {1, 1152, 864, 75, TRUE}, {2, 1152, 864, 84, FALSE},
114 {1, 1280, 720, 60, TRUE}, {2, 1280, 720, 75, FALSE}, {3, 1280, 720, 85, TRUE},
115 {1, 1280, 768, 60, TRUE},
116 {1, 1280, 960, 60, TRUE}, {2, 1280, 960, 85, TRUE},
117 {1, 1280, 1024, 43, FALSE}, {2, 1280, 1024, 60, TRUE}, {3, 1280, 1024, 75, FALSE},
118 {4, 1280, 1024, 85, TRUE},
119 {1, 1360, 768, 60, TRUE},
120 {1, 1400, 1050, 60, TRUE}, {2, 1400, 1050, 75, TRUE},
121 {1, 1600, 1200, 60, TRUE}, {2, 1600, 1200, 65, TRUE}, {3, 1600, 1200, 70, TRUE},
122 {4, 1600, 1200, 75, TRUE}, {5, 1600, 1200, 85, TRUE}, {6, 1600, 1200, 100, TRUE},
123 {7, 1600, 1200, 120, TRUE},
124 {1, 1920, 1440, 60, TRUE}, {2, 1920, 1440, 65, TRUE}, {3, 1920, 1440, 70, TRUE},
125 {4, 1920, 1440, 75, TRUE}, {5, 1920, 1440, 85, TRUE}, {6, 1920, 1440, 100, TRUE},
126 {1, 2048, 1536, 60, TRUE}, {2, 2048, 1536, 65, TRUE}, {3, 2048, 1536, 70, TRUE},
127 {4, 2048, 1536, 75, TRUE}, {5, 2048, 1536, 85, TRUE},
128 {0, 0, 0, 0, FALSE}
129 };
130
131 /* Some 300-series laptops have a badly designed BIOS and make it
132 * impossible to detect the correct panel delay compensation. This
133 * table used to detect such machines by their PCI subsystem IDs;
134 * however, I don't know how reliable this method is. (With Asus
135 * machines, it is to general, ASUS uses the same ID for different
136 * boxes)
137 */
138 static const pdctable mypdctable[] = {
139 { 0x1071, 0x7522, 32, "Mitac", "7521T" },
140 { 0, 0, 0, "" , "" }
141 };
142
143 static const chswtable mychswtable[] = {
144 { 0x1631, 0x1002, "Mitachi", "0x1002" },
145 { 0x1071, 0x7521, "Mitac" , "7521P" },
146 { 0, 0, "" , "" }
147 };
148
149 const customttable mycustomttable[] = {
150 { SIS_630, "2.00.07", "09/27/2002-13:38:25",
151 0x3240A8,
152 { 0x220, 0x227, 0x228, 0x229, 0x0ee },
153 { 0x01, 0xe3, 0x9a, 0x6a, 0xef },
154 0x1039, 0x6300,
155 "Barco", "iQ R200L/300/400", CUT_BARCO1366, "BARCO1366"
156 },
157 { SIS_630, "2.00.07", "09/27/2002-13:38:25",
158 0x323FBD,
159 { 0x220, 0x227, 0x228, 0x229, 0x0ee },
160 { 0x00, 0x5a, 0x64, 0x41, 0xef },
161 0x1039, 0x6300,
162 "Barco", "iQ G200L/300/400/500", CUT_BARCO1024, "BARCO1024"
163 },
164 { SIS_650, "", "",
165 0,
166 { 0, 0, 0, 0, 0 },
167 { 0, 0, 0, 0, 0 },
168 0x0e11, 0x083c,
169 "Compaq (Inventec)", "Presario 3017cl/3045US", CUT_COMPAQ12802, "COMPAQ1280"
170 },
171 { SIS_650, "", "",
172 0,
173 { 0x00c, 0, 0, 0, 0 },
174 { 'e' , 0, 0, 0, 0 },
175 0x1558, 0x0287,
176 "Clevo", "L285/L287 (Version 1)", CUT_CLEVO1024, "CLEVO1024"
177 },
178 { SIS_650, "", "",
179 0,
180 { 0x00c, 0, 0, 0, 0 },
181 { 'y' , 0, 0, 0, 0 },
182 0x1558, 0x0287,
183 "Clevo", "L285/L287 (Version 2)", CUT_CLEVO10242, "CLEVO10242"
184 },
185 { SIS_650, "", "",
186 0,
187 { 0, 0, 0, 0, 0 },
188 { 0, 0, 0, 0, 0 },
189 0x1558, 0x0400, /* possibly 401 and 402 as well; not panelsize specific (?) */
190 "Clevo", "D400S/D410S/D400H/D410H", CUT_CLEVO1400, "CLEVO400"
191 },
192 { 4321, "", "", /* This is hopefully NEVER autodetected */
193 0,
194 { 0, 0, 0, 0, 0 },
195 { 0, 0, 0, 0, 0 },
196 0, 0,
197 "Generic", "LVDS/Parallel 848x480", CUT_PANEL848, "PANEL848x480"
198 },
199 { 0, "", "",
200 0,
201 { 0, 0, 0, 0 },
202 { 0, 0, 0, 0 },
203 0, 0,
204 "", "", CUT_NONE, ""
205 }
206 };
207
208 /* Our TV modes for the 6326. The data in these structures
209 * is mainly correct, but since we use our private CR and
210 * clock values anyway, small errors do no matter.
211 */
212 static DisplayModeRec SiS6326PAL800x600Mode = {
213 NULL, NULL, /* prev, next */
214 "PAL800x600", /* identifier of this mode */
215 MODE_OK, /* mode status */
216 M_T_BUILTIN, /* mode type */
217 36000, /* Clock frequency */
218 800, /* HDisplay */
219 848, /* HSyncStart */
220 912, /* HSyncEnd */
221 1008, /* HTotal */
222 0, /* HSkew */
223 600, /* VDisplay */
224 600, /* VSyncStart */
225 602, /* VSyncEnd */
226 625, /* VTotal */
227 0, /* VScan */
228 V_PHSYNC | V_PVSYNC, /* Flags */
229 -1, /* ClockIndex */
230 36000, /* SynthClock */
231 800, /* CRTC HDisplay */
232 808, /* CRTC HBlankStart */
233 848, /* CRTC HSyncStart */
234 912, /* CRTC HSyncEnd */
235 1008, /* CRTC HBlankEnd */
236 1008, /* CRTC HTotal */
237 0, /* CRTC HSkew */
238 600, /* CRTC VDisplay */
239 600, /* CRTC VBlankStart */
240 600, /* CRTC VSyncStart */
241 602, /* CRTC VSyncEnd */
242 625, /* CRTC VBlankEnd */
243 625, /* CRTC VTotal */
244 FALSE, /* CrtcHAdjusted */
245 FALSE, /* CrtcVAdjusted */
246 0, /* PrivSize */
247 NULL, /* Private */
248 0.0, /* HSync */
249 0.0 /* VRefresh */
250 };
251
252 /* Due to the scaling method this mode uses, the vertical data here
253 * does not match the CR data. But this does not matter, we use our
254 * private CR data anyway.
255 */
256 static DisplayModeRec SiS6326PAL800x600UMode = {
257 NULL, /* prev */
258 &SiS6326PAL800x600Mode, /* next */
259 "PAL800x600U", /* identifier of this mode */
260 MODE_OK, /* mode status */
261 M_T_BUILTIN, /* mode type */
262 37120, /* Clock frequency */
263 800, /* HDisplay */
264 872, /* HSyncStart */
265 984, /* HSyncEnd */
266 1088, /* HTotal */
267 0, /* HSkew */
268 600, /* VDisplay (548 due to scaling) */
269 600, /* VSyncStart (584) */
270 602, /* VSyncEnd (586) */
271 625, /* VTotal */
272 0, /* VScan */
273 V_PHSYNC | V_PVSYNC, /* Flags */
274 -1, /* ClockIndex */
275 37120, /* SynthClock */
276 800, /* CRTC HDisplay */
277 808, /* CRTC HBlankStart */
278 872, /* CRTC HSyncStart */
279 984, /* CRTC HSyncEnd */
280 1024, /* CRTC HBlankEnd */
281 1088, /* CRTC HTotal */
282 0, /* CRTC HSkew */
283 600, /* CRTC VDisplay (548 due to scaling) */
284 600, /* CRTC VBlankStart (600) */
285 600, /* CRTC VSyncStart (584) */
286 602, /* CRTC VSyncEnd (586) */
287 625, /* CRTC VBlankEnd */
288 625, /* CRTC VTotal */
289 FALSE, /* CrtcHAdjusted */
290 FALSE, /* CrtcVAdjusted */
291 0, /* PrivSize */
292 NULL, /* Private */
293 0.0, /* HSync */
294 0.0 /* VRefresh */
295 };
296
297 static DisplayModeRec SiS6326PAL720x540Mode = {
298 NULL, /* prev */
299 &SiS6326PAL800x600UMode, /* next */
300 "PAL720x540", /* identifier of this mode */
301 MODE_OK, /* mode status */
302 M_T_BUILTIN, /* mode type */
303 36000, /* Clock frequency */
304 720, /* HDisplay */
305 816, /* HSyncStart */
306 920, /* HSyncEnd */
307 1008, /* HTotal */
308 0, /* HSkew */
309 540, /* VDisplay */
310 578, /* VSyncStart */
311 580, /* VSyncEnd */
312 625, /* VTotal */
313 0, /* VScan */
314 V_PHSYNC | V_PVSYNC, /* Flags */
315 -1, /* ClockIndex */
316 36000, /* SynthClock */
317 720, /* CRTC HDisplay */
318 736, /* CRTC HBlankStart */
319 816, /* CRTC HSyncStart */
320 920, /* CRTC HSyncEnd */
321 1008, /* CRTC HBlankEnd */
322 1008, /* CRTC HTotal */
323 0, /* CRTC HSkew */
324 540, /* CRTC VDisplay */
325 577, /* CRTC VBlankStart */
326 578, /* CRTC VSyncStart */
327 580, /* CRTC VSyncEnd */
328 625, /* CRTC VBlankEnd */
329 625, /* CRTC VTotal */
330 FALSE, /* CrtcHAdjusted */
331 FALSE, /* CrtcVAdjusted */
332 0, /* PrivSize */
333 NULL, /* Private */
334 0.0, /* HSync */
335 0.0 /* VRefresh */
336 };
337
338 static DisplayModeRec SiS6326PAL640x480Mode = {
339 NULL, /* prev */
340 &SiS6326PAL720x540Mode, /* next */
341 "PAL640x480", /* identifier of this mode */
342 MODE_OK, /* mode status */
343 M_T_BUILTIN, /* mode type */
344 36000, /* Clock frequency */
345 640, /* HDisplay */
346 768, /* HSyncStart */
347 920, /* HSyncEnd */
348 1008, /* HTotal */
349 0, /* HSkew */
350 480, /* VDisplay */
351 532, /* VSyncStart */
352 534, /* VSyncEnd */
353 625, /* VTotal */
354 0, /* VScan */
355 V_NHSYNC | V_NVSYNC, /* Flags */
356 -1, /* ClockIndex */
357 36000, /* SynthClock */
358 640, /* CRTC HDisplay */
359 648, /* CRTC HBlankStart */
360 768, /* CRTC HSyncStart */
361 920, /* CRTC HSyncEnd */
362 944, /* CRTC HBlankEnd */
363 1008, /* CRTC HTotal */
364 0, /* CRTC HSkew */
365 480, /* CRTC VDisplay */
366 481, /* CRTC VBlankStart */
367 532, /* CRTC VSyncStart */
368 534, /* CRTC VSyncEnd */
369 561, /* CRTC VBlankEnd */
370 625, /* CRTC VTotal */
371 FALSE, /* CrtcHAdjusted */
372 FALSE, /* CrtcVAdjusted */
373 0, /* PrivSize */
374 NULL, /* Private */
375 0.0, /* HSync */
376 0.0 /* VRefresh */
377 };
378
379 static DisplayModeRec SiS6326NTSC640x480Mode = {
380 NULL, NULL, /* prev, next */
381 "NTSC640x480", /* identifier of this mode */
382 MODE_OK, /* mode status */
383 M_T_BUILTIN, /* mode type */
384 27000, /* Clock frequency */
385 640, /* HDisplay */
386 664, /* HSyncStart */
387 760, /* HSyncEnd */
388 800, /* HTotal */
389 0, /* HSkew */
390 480, /* VDisplay */
391 489, /* VSyncStart */
392 491, /* VSyncEnd */
393 525, /* VTotal */
394 0, /* VScan */
395 V_NHSYNC | V_NVSYNC, /* Flags */
396 -1, /* ClockIndex */
397 27000, /* SynthClock */
398 640, /* CRTC HDisplay */
399 648, /* CRTC HBlankStart */
400 664, /* CRTC HSyncStart */
401 760, /* CRTC HSyncEnd */
402 792, /* CRTC HBlankEnd */
403 800, /* CRTC HTotal */
404 0, /* CRTC HSkew */
405 480, /* CRTC VDisplay */
406 488, /* CRTC VBlankStart */
407 489, /* CRTC VSyncStart */
408 491, /* CRTC VSyncEnd */
409 517, /* CRTC VBlankEnd */
410 525, /* CRTC VTotal */
411 FALSE, /* CrtcHAdjusted */
412 FALSE, /* CrtcVAdjusted */
413 0, /* PrivSize */
414 NULL, /* Private */
415 0.0, /* HSync */
416 0.0 /* VRefresh */
417 };
418
419 /* Due to the scaling method this mode uses, the vertical data here
420 * does not match the CR data. But this does not matter, we use our
421 * private CR data anyway.
422 */
423 static DisplayModeRec SiS6326NTSC640x480UMode = {
424 NULL, /* prev */
425 &SiS6326NTSC640x480Mode, /* next */
426 "NTSC640x480U", /* identifier of this mode */
427 MODE_OK, /* mode status */
428 M_T_BUILTIN, /* mode type */
429 32215, /* Clock frequency */
430 640, /* HDisplay */
431 696, /* HSyncStart */
432 840, /* HSyncEnd */
433 856, /* HTotal */
434 0, /* HSkew */
435 480, /* VDisplay (439 due to scaling) */
436 489, /* VSyncStart (473) */
437 491, /* VSyncEnd (475) */
438 525, /* VTotal */
439 0, /* VScan */
440 V_NHSYNC | V_NVSYNC, /* Flags */
441 -1, /* ClockIndex */
442 32215, /* SynthClock */
443 640, /* CRTC HDisplay */
444 656, /* CRTC HBlankStart */
445 696, /* CRTC HSyncStart */
446 840, /* CRTC HSyncEnd */
447 856, /* CRTC HBlankEnd */
448 856, /* CRTC HTotal */
449 0, /* CRTC HSkew */
450 480, /* CRTC VDisplay */
451 488, /* CRTC VBlankStart */
452 489, /* CRTC VSyncStart */
453 491, /* CRTC VSyncEnd */
454 517, /* CRTC VBlankEnd */
455 525, /* CRTC VTotal */
456 FALSE, /* CrtcHAdjusted */
457 FALSE, /* CrtcVAdjusted */
458 0, /* PrivSize */
459 NULL, /* Private */
460 0.0, /* HSync */
461 0.0 /* VRefresh */
462 };
463
464
465 static DisplayModeRec SiS6326NTSC640x400Mode = {
466 NULL, /* prev */
467 &SiS6326NTSC640x480UMode, /* next */
468 "NTSC640x400", /* identifier of this mode */
469 MODE_OK, /* mode status */
470 M_T_BUILTIN, /* mode type */
471 27000, /* Clock frequency */
472 640, /* HDisplay */
473 664, /* HSyncStart */
474 760, /* HSyncEnd */
475 800, /* HTotal */
476 0, /* HSkew */
477 400, /* VDisplay */
478 459, /* VSyncStart */
479 461, /* VSyncEnd */
480 525, /* VTotal */
481 0, /* VScan */
482 V_NHSYNC | V_NVSYNC, /* Flags */
483 -1, /* ClockIndex */
484 27000, /* SynthClock */
485 640, /* CRTC HDisplay */
486 648, /* CRTC HBlankStart */
487 664, /* CRTC HSyncStart */
488 760, /* CRTC HSyncEnd */
489 792, /* CRTC HBlankEnd */
490 800, /* CRTC HTotal */
491 0, /* CRTC HSkew */
492 400, /* CRTC VDisplay */
493 407, /* CRTC VBlankStart */
494 459, /* CRTC VSyncStart */
495 461, /* CRTC VSyncEnd */
496 490, /* CRTC VBlankEnd */
497 525, /* CRTC VTotal */
498 FALSE, /* CrtcHAdjusted */
499 FALSE, /* CrtcVAdjusted */
500 0, /* PrivSize */
501 NULL, /* Private */
502 0.0, /* HSync */
503 0.0 /* VRefresh */
504 };
505
506 /* Built-in hi-res modes for the 6326.
507 * For some reason, our default mode lines and the
508 * clock calculation functions in sis_dac.c do no
509 * good job on higher clocks. It seems, the hardware
510 * needs some tricks so make mode with higher clock
511 * rates than ca. 120MHz work. I didn't bother trying
512 * to find out what exactly is going wrong, so I
513 * implemented two special modes instead for 1280x1024
514 * and 1600x1200. These two are automatically added
515 * to the list if they are supported with the current
516 * depth.
517 * The data in the strucures below is a proximation,
518 * in sis_vga.c the register contents are fetched from
519 * fixed tables anyway.
520 */
521 static DisplayModeRec SiS6326SIS1280x1024_75Mode = {
522 NULL, /* prev */
523 NULL, /* next */
524 "SIS1280x1024-75", /* identifier of this mode */
525 MODE_OK, /* mode status */
526 M_T_BUILTIN, /* mode type */
527 135000, /* Clock frequency */
528 1280, /* HDisplay */
529 1296, /* HSyncStart */
530 1440, /* HSyncEnd */
531 1688, /* HTotal */
532 0, /* HSkew */
533 1024, /* VDisplay */
534 1025, /* VSyncStart */
535 1028, /* VSyncEnd */
536 1066, /* VTotal */
537 0, /* VScan */
538 V_PHSYNC | V_PVSYNC, /* Flags */
539 -1, /* ClockIndex */
540 135000, /* SynthClock */
541 1280, /* CRTC HDisplay */
542 1280, /* CRTC HBlankStart */
543 1296, /* CRTC HSyncStart */
544 1440, /* CRTC HSyncEnd */
545 1680, /* CRTC HBlankEnd */
546 1688, /* CRTC HTotal */
547 0, /* CRTC HSkew */
548 1024, /* CRTC VDisplay */
549 1024, /* CRTC VBlankStart */
550 1025, /* CRTC VSyncStart */
551 1028, /* CRTC VSyncEnd */
552 1065, /* CRTC VBlankEnd */
553 1066, /* CRTC VTotal */
554 FALSE, /* CrtcHAdjusted */
555 FALSE, /* CrtcVAdjusted */
556 0, /* PrivSize */
557 NULL, /* Private */
558 0.0, /* HSync */
559 0.0 /* VRefresh */
560 };
561
562 static DisplayModeRec SiS6326SIS1600x1200_60Mode = {
563 NULL, /* prev */
564 NULL, /* next */
565 "SIS1600x1200-60", /* identifier of this mode */
566 MODE_OK, /* mode status */
567 M_T_BUILTIN, /* mode type */
568 162000, /* Clock frequency */
569 1600, /* HDisplay */
570 1664, /* HSyncStart */
571 1856, /* HSyncEnd */
572 2160, /* HTotal */
573 0, /* HSkew */
574 1200, /* VDisplay */
575 1201, /* VSyncStart */
576 1204, /* VSyncEnd */
577 1250, /* VTotal */
578 0, /* VScan */
579 V_PHSYNC | V_PVSYNC, /* Flags */
580 -1, /* ClockIndex */
581 162000, /* SynthClock */
582 1600, /* CRTC HDisplay */
583 1600, /* CRTC HBlankStart */
584 1664, /* CRTC HSyncStart */
585 1856, /* CRTC HSyncEnd */
586 2152, /* CRTC HBlankEnd */
587 2160, /* CRTC HTotal */
588 0, /* CRTC HSkew */
589 1200, /* CRTC VDisplay */
590 1200, /* CRTC VBlankStart */
591 1201, /* CRTC VSyncStart */
592 1204, /* CRTC VSyncEnd */
593 1249, /* CRTC VBlankEnd */
594 1250, /* CRTC VTotal */
595 FALSE, /* CrtcHAdjusted */
596 FALSE, /* CrtcVAdjusted */
597 0, /* PrivSize */
598 NULL, /* Private */
599 0.0, /* HSync */
600 0.0 /* VRefresh */
601 };
602
603 static const struct _SiSTVFilter301 {
604 unsigned char filter[7][4];
605 } SiSTVFilter301[] = {
606 {{ {0x00,0xE0,0x10,0x60}, /* NTSCFilter - 320 */
607 {0x00,0xEE,0x10,0x44},
608 {0x00,0xF4,0x10,0x38},
609 {0xF8,0xF4,0x18,0x38},
610 {0xFC,0xFB,0x14,0x2A},
611 {0x00,0x00,0x10,0x20},
612 {0x00,0x04,0x10,0x18} }},
613 {{ {0xF5,0xEE,0x1B,0x44}, /* NTSCFilter - 640 */
614 {0xF8,0xF4,0x18,0x38},
615 {0xEB,0x04,0x25,0x18},
616 {0xF1,0x05,0x1F,0x16},
617 {0xF6,0x06,0x1A,0x14},
618 {0xFA,0x06,0x16,0x14},
619 {0x00,0x04,0x10,0x18} }},
620 {{ {0xEB,0x04,0x25,0x18}, /* NTSCFilter - 720 */
621 {0xE7,0x0E,0x29,0x04},
622 {0xEE,0x0C,0x22,0x08},
623 {0xF6,0x0B,0x1A,0x0A},
624 {0xF9,0x0A,0x17,0x0C},
625 {0xFC,0x0A,0x14,0x0C},
626 {0x00,0x08,0x10,0x10} }},
627 {{ {0xEC,0x02,0x24,0x1C}, /* NTSCFilter - 800/400 */
628 {0xF2,0x04,0x1E,0x18},
629 {0xEB,0x15,0x25,0xF6},
630 {0xF4,0x10,0x1C,0x00},
631 {0xF8,0x0F,0x18,0x02},
632 {0x00,0x04,0x10,0x18},
633 {0x01,0x06,0x0F,0x14} }},
634 {{ {0x00,0xE0,0x10,0x60}, /* PALFilter - 320 */
635 {0x00,0xEE,0x10,0x44},
636 {0x00,0xF4,0x10,0x38},
637 {0xF8,0xF4,0x18,0x38},
638 {0xFC,0xFB,0x14,0x2A},
639 {0x00,0x00,0x10,0x20},
640 {0x00,0x04,0x10,0x18} }},
641 {{ {0xF5,0xEE,0x1B,0x44}, /* PALFilter - 640 */
642 {0xF8,0xF4,0x18,0x38},
643 {0xF1,0xF7,0x1F,0x32},
644 {0xF5,0xFB,0x1B,0x2A},
645 {0xF9,0xFF,0x17,0x22},
646 {0xFB,0x01,0x15,0x1E},
647 {0x00,0x04,0x10,0x18} }},
648 {{ {0xF5,0xEE,0x1B,0x2A}, /* PALFilter - 720 */
649 {0xEE,0xFE,0x22,0x24},
650 {0xF3,0x00,0x1D,0x20},
651 {0xF9,0x03,0x17,0x1A},
652 {0xFB,0x02,0x14,0x1E},
653 {0xFB,0x04,0x15,0x18},
654 {0x00,0x06,0x10,0x14} }},
655 {{ {0xF5,0xEE,0x1B,0x44}, /* PALFilter - 800/400 */
656 {0xF8,0xF4,0x18,0x38},
657 {0xFC,0xFB,0x14,0x2A},
658 {0xEB,0x05,0x25,0x16},
659 {0xF1,0x05,0x1F,0x16},
660 {0xFA,0x07,0x16,0x12},
661 {0x00,0x07,0x10,0x12} }}
662 };
663
664 static const struct _SiSTVFilter301B {
665 unsigned char filter[7][7];
666 } SiSTVFilter301B[] = {
667 {{ {0x01,0x02,0xfb,0xf8,0x06,0x27,0x3a}, /* NTSC - 640 */
668 {0x01,0x02,0xfe,0xf7,0x03,0x27,0x3c},
669 {0x01,0x01,0x00,0xf6,0x00,0x28,0x40},
670 {0xff,0x03,0x02,0xf6,0xfc,0x27,0x46},
671 {0xff,0x01,0x04,0xf8,0xfa,0x27,0x46},
672 {0xff,0x01,0x05,0xf9,0xf7,0x26,0x4a},
673 {0xff,0xff,0x05,0xfc,0xf4,0x24,0x52} }},
674 {{ {0x01,0x00,0xfb,0xfb,0x0b,0x25,0x32}, /* NTSC - 720 (?) */
675 {0x01,0x01,0xfb,0xf9,0x09,0x26,0x36},
676 {0x01,0x02,0xfc,0xf8,0x06,0x27,0x38},
677 {0x01,0x02,0xfe,0xf7,0x03,0x27,0x3c},
678 {0x01,0x03,0xff,0xf6,0x00,0x27,0x40},
679 {0xff,0x03,0x02,0xf6,0xfe,0x27,0x42},
680 {0xff,0x02,0x03,0xf7,0xfb,0x27,0x46} }},
681 {{ {0x01,0xfe,0xfb,0xfe,0x0e,0x23,0x2e}, /* NTSC - 800 */
682 {0x01,0xff,0xfb,0xfc,0x0c,0x25,0x30},
683 {0x01,0x00,0xfb,0xfa,0x0a,0x26,0x34},
684 {0x01,0x01,0xfc,0xf8,0x08,0x26,0x38},
685 {0x01,0x02,0xfd,0xf7,0x06,0x27,0x38},
686 {0x01,0x02,0xfe,0xf7,0x03,0x27,0x3c},
687 {0xff,0x03,0x00,0xf6,0x00,0x27,0x42} }},
688 {{ {0xff,0xfd,0xfe,0x05,0x11,0x1e,0x24}, /* NTSC - 1024 */
689 {0xff,0xfd,0xfd,0x04,0x11,0x1f,0x26},
690 {0xff,0xfd,0xfc,0x02,0x10,0x22,0x28},
691 {0xff,0xff,0xfc,0x00,0x0f,0x22,0x28},
692 {0x01,0xfe,0xfb,0xff,0x0e,0x23,0x2c},
693 {0x01,0xff,0xfb,0xfd,0x0d,0x24,0x2e},
694 {0x01,0xff,0xfb,0xfb,0x0c,0x25,0x32} }},
695 {{ {0x01,0x02,0xfb,0xf8,0x06,0x27,0x3a}, /* PAL - 640 */
696 {0x01,0x02,0xfe,0xf7,0x03,0x27,0x3c},
697 {0x01,0x01,0x00,0xf6,0x00,0x28,0x40},
698 {0xff,0x03,0x02,0xf6,0xfc,0x27,0x46},
699 {0xff,0x01,0x04,0xf8,0xfa,0x27,0x46},
700 {0xff,0x01,0x05,0xf9,0xf7,0x26,0x4a},
701 {0xff,0xff,0x05,0xfc,0xf4,0x24,0x52} }},
702 {{ {0x01,0x00,0xfb,0xfb,0x0b,0x25,0x32}, /* PAL - 720/768 */
703 {0x01,0x01,0xfb,0xf9,0x09,0x26,0x36},
704 {0x01,0x02,0xfc,0xf8,0x06,0x27,0x38},
705 {0x01,0x02,0xfe,0xf7,0x03,0x27,0x3c},
706 {0x01,0x03,0xff,0xf6,0x00,0x27,0x40},
707 {0xff,0x03,0x02,0xf6,0xfe,0x27,0x42},
708 {0xff,0x02,0x03,0xf7,0xfb,0x27,0x46} }},
709 {{ {0x01,0xfe,0xfb,0xfe,0x0e,0x23,0x2e}, /* PAL - 800 */
710 {0x01,0xff,0xfb,0xfc,0x0c,0x25,0x30},
711 {0x01,0x00,0xfb,0xfa,0x0a,0x26,0x34},
712 {0x01,0x01,0xfc,0xf8,0x08,0x26,0x38},
713 {0x01,0x02,0xfd,0xf7,0x06,0x27,0x38},
714 {0x01,0x02,0xfe,0xf7,0x03,0x27,0x3c},
715 {0xff,0x03,0x00,0xf6,0x00,0x27,0x42} }},
716 {{ {0xff,0xfd,0xfe,0x05,0x11,0x1e,0x24}, /* PAL - 1024 */
717 {0xff,0xfd,0xfd,0x04,0x11,0x1f,0x26},
718 {0xff,0xfd,0xfc,0x02,0x10,0x22,0x28},
719 {0xff,0xff,0xfc,0x00,0x0f,0x22,0x28},
720 {0x01,0xfe,0xfb,0xff,0x0e,0x23,0x2c},
721 {0x01,0xff,0xfb,0xfd,0x0d,0x24,0x2e},
722 {0x01,0xff,0xfb,0xfb,0x0c,0x25,0x32} }}
723 };
724
725 typedef struct _SiSTVVScale {
726 unsigned short ScaleVDE;
727 int sindex;
728 unsigned short RealVDE;
729 #if 0
730 unsigned short HT, HRS, HRE, VT, VRS, VRE;
731 unsigned short NFF, HCFACT, HCMAX, VBHT, VBVT, VBHRS;
732 unsigned short HT300, HRS300, HRE300, VT300, VRS300, VRE300;
733 unsigned short NFF300, HCFACT300, HCMAX300, VBHT300, VBVT300, VBHRS300;
734 #endif
735 unsigned short reg[24];
736 } MySiSTVVScale, *MySiSTVVScalePtr;
737
738 static const MySiSTVVScale SiSTVVScale[] = {
739 { 0x01D6, 3, 480, /* NTSC 640 */
740 { 0x037C, 0x02B0, 0x00EF, 0x01FA, 0x01E7, 0x01E9,
741 0x0000, 0x004C, 0x008F, 0x037C, 0x01FB, 0x00D4,
742 0x037C, 0x02CB, 0x0049, 0x01FB, 0x01EE, 0x01F0,
743 0x0000, 0x004C, 0x008F, 0x037C, 0x01FB, 0x00E0 }
744 },
745 { 0x01CC, 2, 480,
746 { 0x0369, 0x02AD, 0x00E7, 0x01FF, 0x01E8, 0x01EB,
747 0x0000, 0x004C, 0x008F, 0x0369, 0x0200, 0x00D4,
748 0x0369, 0x02C6, 0x003A, 0x0200, 0x01F0, 0x01F3,
749 0x0000, 0x004C, 0x008F, 0x0369, 0x0200, 0x00E0 }
750 },
751 { 0x01C2, 1, 480,
752 { 0x0356, 0x02AB, 0x00E0, 0x0204, 0x01E9, 0x01EC,
753 0x0000, 0x004C, 0x008F, 0x0356, 0x0205, 0x00D4,
754 0x0356, 0x02C1, 0x002B, 0x0205, 0x01F3, 0x01F6,
755 0x0000, 0x004C, 0x008F, 0x0356, 0x0205, 0x00E0 }
756 },
757 { 0x01B8, 0, 480, /* default */
758 { 0x0343, 0x02A9, 0x00DA, 0x0209, 0x01EA, 0x01ED,
759 0x0000, 0x004C, 0x008F, 0x0343, 0x020A, 0x00D4,
760 0x0343, 0x02BD, 0x001F, 0x020A, 0x01F5, 0x01F8,
761 0x0000, 0x004C, 0x008F, 0x0343, 0x020A, 0x00E0 }
762 },
763 { 0x01AE, -1, 480,
764 { 0x035B, 0x02AC, 0x00E3, 0x020E, 0x01EC, 0x01F0,
765 0x0000, 0x0050, 0x008F, 0x035B, 0x020F, 0x0152,
766 0x035B, 0x02C3, 0x0031, 0x020F, 0x01F8, 0x01FC,
767 0x0000, 0x0050, 0x008F, 0x035B, 0x020F, 0x015E }
768 },
769 { 0x01A4, -2, 480,
770 { 0x0347, 0x02A9, 0x00DB, 0x0213, 0x01ED, 0x01F1,
771 0x0000, 0x0050, 0x008F, 0x0347, 0x0214, 0x0102,
772 0x0347, 0x02BE, 0x0022, 0x0214, 0x01FA, 0x01FE,
773 0x0000, 0x0050, 0x008F, 0x0347, 0x0214, 0x010E }
774 },
775 { 0x019A, -3, 480,
776 { 0x0333, 0x02A7, 0x00D4, 0x0218, 0x01EE, 0x01F2,
777 0x0000, 0x0050, 0x008F, 0x0333, 0x0219, 0x016A,
778 0x0333, 0x02B9, 0x0013, 0x0219, 0x01FD, 0x0201,
779 0x0000, 0x0050, 0x008F, 0x0333, 0x0219, 0x016A }
780 },
781 { 0x01D6, 3, 480, /* NTSC 720 */
782 { 0x037C, 0x0307, 0x005D, 0x01FB, 0x01EE, 0x01F0,
783 0x0000, 0x004C, 0x008F, 0x037C, 0x01FB, 0x0090 }
784 },
785 { 0x01CC, 2, 480,
786 { 0x0369, 0x0302, 0x004E, 0x0200, 0x01F0, 0x01F3,
787 0x0000, 0x004C, 0x008F, 0x0369, 0x0200, 0x0090 }
788 },
789 { 0x01C2, 1, 480,
790 { 0x0356, 0x02FD, 0x003F, 0x0205, 0x01F3, 0x01F6,
791 0x0000, 0x004C, 0x008F, 0x0356, 0x0205, 0x0090 }
792 },
793 { 0x01B8, 0, 480, /* default */
794 { 0x0343, 0x02F9, 0x0033, 0x020A, 0x01F5, 0x01F8,
795 0x0000, 0x004C, 0x008F, 0x0343, 0x020A, 0x0090 }
796 },
797 { 0x01AE, -1, 480,
798 { 0x035B, 0x02FF, 0x0045, 0x020F, 0x01F8, 0x01FC,
799 0x0000, 0x0050, 0x008F, 0x035B, 0x020F, 0x010E }
800 },
801 { 0x01A4, -2, 480,
802 { 0x0347, 0x02FA, 0x0036, 0x0214, 0x01FA, 0x01FE,
803 0x0000, 0x0050, 0x008F, 0x0347, 0x0214, 0x00BE }
804 },
805 { 0x019A, -3, 480,
806 { 0x0333, 0x02F5, 0x0027, 0x0219, 0x01FD, 0x0201,
807 0x0000, 0x0050, 0x008F, 0x0333, 0x0219, 0x0136 }
808 },
809 { 0x01D6, 3, 600, /* NTSC 800 */
810 { 0x0438, 0x0353, 0x0099, 0x0272, 0x025F, 0x0261,
811 0x0000, 0x0073, 0x008F, 0x0438, 0x0273, 0x020A,
812 0x0438, 0x0372, 0x00FE, 0x0273, 0x0266, 0x0268,
813 0x0000, 0x0073, 0x008F, 0x0438, 0x0273, 0x020A }
814 },
815 { 0x01CC, 2, 600,
816 { 0x0421, 0x0350, 0x0090, 0x0277, 0x0260, 0x0263,
817 0x0000, 0x0073, 0x008F, 0x0421, 0x0278, 0x020A,
818 0x0421, 0x036C, 0x00EC, 0x0278, 0x0268, 0x026B,
819 0x0000, 0x0073, 0x008F, 0x0421, 0x0278, 0x020A }
820 },
821 { 0x01C2, 1, 600,
822 { 0x0413, 0x034F, 0x008C, 0x027C, 0x0261, 0x0264,
823 0x0000, 0x0074, 0x008F, 0x0413, 0x027D, 0x01FE,
824 0x0413, 0x0369, 0x00E3, 0x027D, 0x026B, 0x026E,
825 0x0000, 0x0074, 0x008F, 0x0413, 0x027D, 0x020C }
826 },
827 { 0x01B8, 0, 600, /* default */
828 { 0x041F, 0x0350, 0x0090, 0x0281, 0x0262, 0x0265,
829 0x0000, 0x0078, 0x008F, 0x041F, 0x0282, 0x0220,
830 0x041F, 0x036C, 0x00EC, 0x0282, 0x026D, 0x0270,
831 0x0001, 0x0078, 0x008F, 0x041F, 0x0282, 0x0220 }
832 },
833 { 0x01AE, -1, 600,
834 { 0x0407, 0x034D, 0x0087, 0x0286, 0x0264, 0x0268,
835 0x0000, 0x0078, 0x008F, 0x0407, 0x0287, 0x0220,
836 0x0407, 0x0366, 0x00DA, 0x0287, 0x0270, 0x0274,
837 0x0001, 0x0078, 0x008F, 0x0407, 0x0287, 0x0220 }
838 },
839 { 0x01A4, -2, 600,
840 { 0x03EF, 0x034A, 0x007E, 0x028B, 0x0265, 0x0269,
841 0x0000, 0x0078, 0x008F, 0x03EF, 0x028C, 0x0220,
842 0x03EF, 0x0360, 0x00C8, 0x028C, 0x0272, 0x0276,
843 0x0001, 0x0078, 0x008F, 0x03EF, 0x028C, 0x0220 }
844 },
845 { 0x019A, -3, 600,
846 { 0x0429, 0x0351, 0x0093, 0x0290, 0x0266, 0x026A,
847 0x0000, 0x0082, 0x008F, 0x0429, 0x0291, 0x024E,
848 0x0429, 0x036E, 0x00F2, 0x0291, 0x0275, 0x0279,
849 0x0001, 0x0082, 0x008F, 0x0429, 0x0291, 0x024E }
850 },
851 #if 0
852 { 0x01B8, 0, 768, /* NTSC 1024 - v-scaling not supported */
853 { 0x044B, 0x041A, 0x002D, 0x0329, 0x030A, 0x030D,
854 0x0000, 0x0001, 0x0001, 0x044B, 0x032A, 0x02D2 }
855 },
856 #endif
857
858 { 0x0230, 3, 480, /* PAL 640 */
859 { 0x0371, 0x02AE, 0x00EA, 0x01FF, 0x01E8, 0x01EB,
860 0x0000, 0x0007, 0x0010, 0x0371, 0x0200, 0x0032,
861 0x0371, 0x02C8, 0x0040, 0x0200, 0x01F0, 0x01F3,
862 0x0000, 0x000E, 0x0020, 0x0371, 0x0200, 0x0032 }
863 },
864 { 0x0226, 2, 480,
865 { 0x0383, 0x02B1, 0x00F2, 0x0204, 0x01E9, 0x01EC,
866 0x0000, 0x0005, 0x000B, 0x0383, 0x0205, 0x0032,
867 0x0383, 0x02CD, 0x004F, 0x0205, 0x01F3, 0x01F6,
868 0x0000, 0x0005, 0x000B, 0x0383, 0x0205, 0x0032 }
869 },
870 { 0x021C, 1, 480,
871 { 0x035F, 0x02AC, 0x00E4, 0x0209, 0x01EA, 0x01ED,
872 0x0000, 0x0004, 0x0009, 0x035F, 0x020A, 0x0032,
873 0x035F, 0x02C4, 0x0034, 0x020A, 0x01F5, 0x01F8,
874 0x0000, 0x0004, 0x0009, 0x035F, 0x020A, 0x0032 }
875 },
876 { 0x0212, 0, 480, /* default */
877 { 0x034F, 0x02AA, 0x00DE, 0x020E, 0x01EC, 0x01F0,
878 0x0000, 0x0004, 0x0009, 0x034F, 0x020F, 0x0032,
879 0x034F, 0x02C0, 0x0028, 0x020F, 0x01F8, 0x01FC,
880 0x0000, 0x0004, 0x0009, 0x034F, 0x020F, 0x0032 }
881 },
882 { 0x0208, -1, 480,
883 { 0x033F, 0x02A8, 0x00D8, 0x0213, 0x01ED, 0x01F1,
884 0x0000, 0x0004, 0x0009, 0x033F, 0x0214, 0x0032,
885 0x033F, 0x02BC, 0x001C, 0x0214, 0x01FA, 0x01FE,
886 0x0000, 0x0004, 0x0009, 0x033F, 0x0214, 0x0032 }
887 },
888 { 0x01FE, -2, 480,
889 { 0x0395, 0x02B3, 0x00F8, 0x0218, 0x01EE, 0x01F2,
890 0x0000, 0x0001, 0x0002, 0x0395, 0x0219, 0x0032,
891 0x0395, 0x02D1, 0x005B, 0x0219, 0x01FD, 0x0201,
892 0x0000, 0x0001, 0x0002, 0x0395, 0x0219, 0x0032 }
893 },
894 { 0x01F4, -3, 480,
895 { 0x0383, 0x02B1, 0x00F2, 0x021D, 0x01EF, 0x01F3,
896 0x0000, 0x0001, 0x0002, 0x0383, 0x021E, 0x0032,
897 0x0383, 0x02CD, 0x004F, 0x021E, 0x01FF, 0x0203,
898 0x0000, 0x0001, 0x0002, 0x0383, 0x021E, 0x0032 }
899 },
900 { 0x0230, 2, 576, /* PAL 720 */
901 { 0x03BF, 0x0318, 0x0090, 0x0260, 0x0250, 0x0253,
902 0x0000, 0x0004, 0x0007, 0x03BF, 0x0260, 0x00E0,
903 0x6954, 0x6C6C, 0x5320, 0x666F, 0x6169, 0x4220,
904 0x7265, 0x746E, 0x7373, 0x6E6F, 0x0260, 0x00E0 }
905 },
906 { 0x0226, 1, 576,
907 { 0x03DD, 0x031F, 0x00A5, 0x0265, 0x0253, 0x0256,
908 0x0000, 0x0003, 0x0005, 0x03DD, 0x0265, 0x013B,
909 0x7242, 0x756F, 0x6867, 0x2074, 0x6F74, 0x7920,
910 0x756F, 0x6220, 0x2079, 0x6F6E, 0x2074, 0x2061 }
911 },
912 { 0x021C, 0, 576, /* default */
913 { 0x0437, 0x0336, 0x00EA, 0x026A, 0x0255, 0x0258,
914 0x0000, 0x0002, 0x0003, 0x0437, 0x026A, 0x0180,
915 0x656D, 0x6572, 0x5720, 0x7A69, 0x7261, 0x2064,
916 0x7562, 0x2074, 0x6874, 0x2065, 0x0274, 0x01CE }
917 },
918 { 0x0212, -1, 576,
919 { 0x0423, 0x0331, 0x00DB, 0x026F, 0x0258, 0x025C,
920 0x0001, 0x0002, 0x0003, 0x0423, 0x026F, 0x01CA,
921 0x6957, 0x617A, 0x6472, 0x4520, 0x7478, 0x6172,
922 0x726F, 0x6964, 0x616E, 0x7269, 0x3A65, 0x01CE }
923 },
924 { 0x0208, -2, 576,
925 { 0x040F, 0x032C, 0x00CC, 0x0274, 0x025A, 0x025E,
926 0x0000, 0x0002, 0x0003, 0x040F, 0x0274, 0x01CA,
927 0x6854, 0x6D6F, 0x7361, 0x5720, 0x6E69, 0x7369,
928 0x6863, 0x6F68, 0x6566, 0x2172, 0x027E, 0x01CA }
929 },
930 { 0x01FE, -3, 576,
931 { 0x03FB, 0x0327, 0x00BD, 0x0279, 0x025D, 0x0261,
932 0x0000, 0x0002, 0x0003, 0x03FB, 0x0279, 0x01CA,
933 }
934 },
935 { 0x01F4, -4, 576,
936 { 0x03E7, 0x0322, 0x00AE, 0x027E, 0x025F, 0x0263,
937 0x0000, 0x0002, 0x0003, 0x03E7, 0x027E, 0x01CA,
938 0x6854, 0x7369, 0x7320, 0x6170, 0x6563, 0x6620,
939 0x726F, 0x7320, 0x6C61, 0x0365, 0x027F, 0x01FE }
940 },
941 { 0x0230, 3, 600, /* PAL 800 */
942 { 0x047F, 0x035C, 0x00B4, 0x0277, 0x0260, 0x0263,
943 0x0000, 0x0005, 0x0007, 0x047F, 0x0278, 0x0170,
944 0x047F, 0x0384, 0x0034, 0x0278, 0x0268, 0x026B,
945 0x0000, 0x0005, 0x0007, 0x047F, 0x0278, 0x017E }
946 },
947 { 0x0226, 2, 600,
948 { 0x044B, 0x0356, 0x00A1, 0x027C, 0x0261, 0x0264,
949 0x0000, 0x0019, 0x0024, 0x044B, 0x027D, 0x0150,
950 0x044B, 0x0377, 0x000D, 0x027D, 0x026B, 0x026E,
951 0x0000, 0x0019, 0x0024, 0x044B, 0x027D, 0x015E }
952 },
953 { 0x021C, 1, 600,
954 { 0x0437, 0x0353, 0x0099, 0x0281, 0x0262, 0x0265,
955 0x0000, 0x0019, 0x0024, 0x0437, 0x0282, 0x0150,
956 0x0437, 0x0372, 0x00FE, 0x0282, 0x026D, 0x0270,
957 0x0000, 0x0019, 0x0024, 0x0437, 0x0282, 0x015E }
958 },
959 { 0x0212, 0, 600, /* default */
960 { 0x0423, 0x0351, 0x0092, 0x0286, 0x0264, 0x0268,
961 0x0000, 0x0019, 0x0024, 0x0423, 0x0287, 0x01C8,
962 0x0423, 0x036D, 0x00EF, 0x0287, 0x0270, 0x0274,
963 0x0000, 0x0019, 0x0024, 0x0423, 0x0287, 0x01D6 }
964 },
965 { 0x0208, -1, 600,
966 { 0x040F, 0x034E, 0x008A, 0x028B, 0x0265, 0x0269,
967 0x0000, 0x0019, 0x0024, 0x040F, 0x028C, 0x01A0,
968 0x040F, 0x0368, 0x00E0, 0x028C, 0x0272, 0x0276,
969 0x0000, 0x0019, 0x0024, 0x040F, 0x028C, 0x01AE }
970 },
971 { 0x01FE, -2, 600,
972 { 0x03FB, 0x034C, 0x0083, 0x0290, 0x0266, 0x026A,
973 0x0000, 0x0019, 0x0024, 0x03FB, 0x0291, 0x01C8,
974 0x03FB, 0x0363, 0x00D1, 0x0291, 0x0275, 0x0279,
975 0x0000, 0x0019, 0x0024, 0x03FB, 0x0291, 0x01D6 }
976 },
977 { 0x01F4, -3, 600,
978 { 0x0437, 0x0353, 0x0099, 0x0295, 0x0267, 0x026B,
979 0x0000, 0x0003, 0x0004, 0x0437, 0x0296, 0x01BF,
980 0x0437, 0x0372, 0x00FE, 0x0296, 0x0277, 0x027B,
981 0x0000, 0x0003, 0x0004, 0x0437, 0x0296, 0x01BA }
982 },
983 #if 0
984 { 0x0208, 0, 768, /* PAL 1024 - v-scaling not supported */
985 { 0x0491, 0x0422, 0x0046, 0x0333, 0x030D, 0x0311,
986 0x0000, 0x0001, 0x0001, 0x0491, 0x0334, 0x02AE }
987 }
988 #endif
989 };
990
991 unsigned const char SiSScalingP1Regs[] = {
992 0x08,0x09,0x0b,0x0c,0x0d,0x0e,0x10,0x11,0x12
993 };
994 unsigned const char SiSScalingP4Regs[] = {
995 0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b
996 };
997
998
999 USHORT SiS_CalcModeIndex(ScrnInfoPtr pScrn, DisplayModePtr mode, BOOLEAN hcm);
1000 USHORT SiS_CheckCalcModeIndex(ScrnInfoPtr pScrn, DisplayModePtr mode, unsigned long VBFlags, BOOLEAN hcm);
1001 unsigned char SiS_GetSetBIOSScratch(ScrnInfoPtr pScrn, USHORT offset, unsigned char value);
1002
1003 void SISMergePointerMoved(int scrnIndex, int x, int y);
1004
1005