?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Add Russian translation provided by Валерий Крувялис <valkru@mail.ru>
[xiph-mirror.git] / theora-fpga / doc / leon3_integration / leon3mp.vhd
blobceeff49ac786116ead8db86a2aa13ae40e543585
1 ------------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18
19
20 library ieee;
21 use ieee.std_logic_1164.all;
22 library grlib;
23 use grlib.amba.all;
24 use grlib.stdlib.all;
25 library techmap;
26 use techmap.gencomp.all;
27 library gaisler;
28 use gaisler.memctrl.all;
29 use gaisler.leon3.all;
30 use gaisler.uart.all;
31 use gaisler.misc.all;
32 use gaisler.net.all;
33 use gaisler.ata.all;
34 use gaisler.jtag.all;
35 library esa;
36 use esa.memoryctrl.all;
37 use work.config.all;
38 library contrib;
39 use contrib.theora_hardware.all;
40 --LIBRARY altera_mf;
41 --USE altera_mf.all;
42 LIBRARY work;
43 USE work.plldotheora;
44 entity leon3mp is
45 generic (
46 fabtech : integer := CFG_FABTECH;
47 memtech : integer := CFG_MEMTECH;
48 padtech : integer := CFG_PADTECH;
49 clktech : integer := CFG_CLKTECH;
50 ncpu : integer := CFG_NCPU;
51 disas : integer := CFG_DISAS; -- Enable disassembly to console
52 dbguart : integer := CFG_DUART; -- Print UART on console
53 pclow : integer := CFG_PCLOW;
54 freq : integer := 50000 -- frequency of main clock (used for PLLs)
55 );
56 port (
57
58 resetn : in std_ulogic;
59 clk : in std_ulogic;
60 errorn : out std_ulogic;
61
62 -- Shared bus
63 address : out std_logic_vector(23 downto 0);
64 data : inout std_logic_vector(31 downto 0);
65
66 -- SRAM
67 ramsn : out std_ulogic;
68 ramoen : out std_ulogic;
69 rwen : out std_ulogic;
70 mben : out std_logic_vector(3 downto 0);
71 -- pragma translate_off
72 iosn : out std_ulogic;
73 -- pragma translate_on
74
75 -- FLASH
76 romsn : out std_ulogic;
77 oen : out std_ulogic;
78 writen : out std_ulogic;
79 byten : out std_ulogic;
80 wpn : out std_ulogic;
81
82 sa : out std_logic_vector(11 downto 0);
83 sd : inout std_logic_vector(31 downto 0);
84 sdclk : out std_ulogic;
85 sdcke : out std_logic; -- sdram clock enable
86 sdcsn : out std_logic; -- sdram chip select
87 sdwen : out std_ulogic; -- sdram write enable
88 sdrasn : out std_ulogic; -- sdram ras
89 sdcasn : out std_ulogic; -- sdram cas
90 sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
91 sdba : out std_logic_vector(1 downto 0); -- sdram bank address
92
93 -- debug support unit
94 dsutx : out std_ulogic; -- DSU tx data
95 dsurx : in std_ulogic; -- DSU rx data
96 dsubren : in std_ulogic;
97 dsuact : out std_ulogic;
98
99 -- console UART
100 rxd1 : in std_ulogic;
101 txd1 : out std_ulogic;
102
103 -- ATA signals
104 -- pragma translate_off
105 ata_rst : out std_logic;
106 -- pragma translate_on
107 ata_data : inout std_logic_vector(15 downto 0);
108 ata_da : out std_logic_vector(2 downto 0);
109 ata_cs0 : out std_logic;
110 ata_cs1 : out std_logic;
111 ata_dior : out std_logic;
112 ata_diow : out std_logic;
113 ata_iordy : in std_logic;
114 ata_intrq : in std_logic;
115 ata_dmack : out std_logic;
116
117 -- Signals nedded to use CompactFlash with ATA controller
118 cf_power : out std_logic; -- To turn on power to the CompactFlash
119 cf_gnd_da : out std_logic_vector(10 downto 3); -- grounded address lines
120 cf_atasel : out std_logic; -- grounded to select true IDE mode
121 cf_we : out std_logic; -- should be connected to VCC in true IDE mode
122 cf_csel : out std_logic;
123
124 -- for smsc lan chip
125 eth_aen : out std_logic;
126 eth_readn : out std_logic;
127 eth_writen: out std_logic;
128 eth_nbe : out std_logic_vector(3 downto 0);
129
130 eth_lclk : out std_ulogic;
131 eth_nads : out std_logic;
132 eth_ncycle : out std_logic;
133 eth_wnr : out std_logic;
134 eth_nvlbus : out std_logic;
135 eth_nrdyrtn : out std_logic;
136 eth_ndatacs : out std_logic;
137
138 gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
139
140 red : out std_logic_vector(7 downto 0); -- red component
141 green : out std_logic_vector(7 downto 0); -- green component
142 blue : out std_logic_vector(7 downto 0); -- blue component
143 -- line_pixel : out std_logic_vector(9 downto 0); -- compute line
144 -- column_pixel : out std_logic_vector(9 downto 0); -- compute column
145 m1, m2 : out std_logic; -- select dac mode
146 blank_n : out std_logic; -- dac command
147 sync_n : out std_logic; -- dac command
148 sync_t : out std_logic; -- dac command
149 video_clk : out std_logic; -- dac command
150 vga_vs : out std_logic; -- vertical sync
151 vga_hs : out std_logic -- horizontal sync
152
153 );
154 end;
155
156 architecture rtl of leon3mp is
157
158 constant blength : integer := 12;
159 constant fifodepth : integer := 8;
160
161 constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG;
162
163 signal vcc, gnd : std_logic_vector(7 downto 0);
164 signal memi : memory_in_type;
165 signal memo : memory_out_type;
166 signal wpo : wprot_out_type;
167 signal sdi : sdctrl_in_type;
168 signal sdo : sdram_out_type;
169 signal sdo2, sdo3 : sdctrl_out_type;
170
171 --for smc lan chip
172 signal s_eth_aen : std_logic;
173 signal s_eth_readn : std_logic;
174 signal s_eth_writen: std_logic;
175 signal s_eth_nbe : std_logic_vector(3 downto 0);
176
177 signal apbi : apb_slv_in_type;
178 signal apbo : apb_slv_out_vector := (others => apb_none);
179 signal ahbsi : ahb_slv_in_type;
180 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
181 signal ahbmi : ahb_mst_in_type;
182 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
183
184 signal clkm, rstn, sdclkl : std_ulogic;
185 signal cgi : clkgen_in_type;
186 signal cgo : clkgen_out_type;
187 signal u1i, dui : uart_in_type;
188 signal u1o, duo : uart_out_type;
189
190 signal irqi : irq_in_vector(0 to NCPU-1);
191 signal irqo : irq_out_vector(0 to NCPU-1);
192
193 signal dbgi : l3_debug_in_vector(0 to NCPU-1);
194 signal dbgo : l3_debug_out_vector(0 to NCPU-1);
195
196 signal dsui : dsu_in_type;
197 signal dsuo : dsu_out_type;
198
199 signal ata : ata_type;
200 signal cf : cf_out_type;
201
202 signal gpti : gptimer_in_type;
203 signal gpioi : gpio_in_type;
204 signal gpioo : gpio_out_type;
205
206 constant IOAEN : integer := 1;
207 constant CFG_SDEN : integer := CFG_MCTRL_SDEN ;
208 constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
209
210 signal lclk, lclkout : std_ulogic;
211
212 signal dsubre : std_ulogic;
213 signal clk_25Mhz: std_logic;
214
215 component smc_mctrl
216 generic (
217 hindex : integer := 0;
218 pindex : integer := 0;
219 romaddr : integer := 16#000#;
220 rommask : integer := 16#E00#;
221 ioaddr : integer := 16#200#;
222 iomask : integer := 16#E00#;
223 ramaddr : integer := 16#400#;
224 rammask : integer := 16#C00#;
225 paddr : integer := 0;
226 pmask : integer := 16#fff#;
227 wprot : integer := 0;
228 invclk : integer := 0;
229 fast : integer := 0;
230 romasel : integer := 28;
231 sdrasel : integer := 29;
232 srbanks : integer := 4;
233 ram8 : integer := 0;
234 ram16 : integer := 0;
235 sden : integer := 0;
236 sepbus : integer := 0;
237 sdbits : integer := 32;
238 sdlsb : integer := 2;
239 oepol : integer := 0;
240 syncrst : integer := 0
241 );
242 port (
243 rst : in std_ulogic;
244 clk : in std_ulogic;
245 memi : in memory_in_type;
246 memo : out memory_out_type;
247 ahbsi : in ahb_slv_in_type;
248 ahbso : out ahb_slv_out_type;
249 apbi : in apb_slv_in_type;
250 apbo : out apb_slv_out_type;
251 wpo : in wprot_out_type;
252 sdo : out sdram_out_type;
253 eth_aen : out std_ulogic; -- for smsc lan chip
254 eth_readn : out std_ulogic; -- for smsc lan chip
255 eth_writen: out std_ulogic; -- for smsc lan chip
256 eth_nbe : out std_logic_vector(3 downto 0) -- for smsc lan chip
257 );
258 end component;
259
260 begin
261
262 ----------------------------------------------------------------------
263 --- Reset and Clock generation -------------------------------------
264 ----------------------------------------------------------------------
265
266 vcc <= (others => '1'); gnd <= (others => '0');
267 cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= clk;
268
269 clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
270
271 clkgen0 : clkgen -- clock generator using toplevel generic 'freq'
272 generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL,
273 clk_div => CFG_CLKDIV, sdramen => CFG_MCTRL_SDEN,
274 noclkfb => CFG_CLK_NOFB, freq => freq, clk2xen => 1)
275 port map (clkin => lclk, pciclkin => gnd(0), clk => clkm, clkn => open,
276 clk2x => clk_25Mhz, sdclk => sdclkl, pciclk => open, -- clk2x => open
277 cgi => cgi, cgo => cgo);
278
279 sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24) port map (sdclk, sdclkl);
280
281 rst0 : rstgen -- reset generator
282 port map (resetn, clkm, cgo.clklock, rstn);
283
284 ----------------------------------------------------------------------
285 --- AHB CONTROLLER --------------------------------------------------
286 ----------------------------------------------------------------------
287
288 ahb0 : ahbctrl -- AHB arbiter/multiplexer
289 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
290 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
291 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
292 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
293
294 ----------------------------------------------------------------------
295 --- LEON3 processor and DSU -----------------------------------------
296 ----------------------------------------------------------------------
297
298 l3 : if CFG_LEON3 = 1 generate
299 cpu : for i in 0 to NCPU-1 generate
300 u0 : leon3s -- LEON3 processor
301 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
302 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
303 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
304 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
305 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
306 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
307 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
308 irqi(i), irqo(i), dbgi(i), dbgo(i));
309 end generate;
310 errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
311
312 dsugen : if CFG_DSU = 1 generate
313 dsu0 : dsu3 -- LEON3 Debug Support Unit
314 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
315 ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
316 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
317
318 dsui.enable <= '1';
319
320 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
321 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
322 end generate;
323 end generate;
324 nodcom : if CFG_DSU = 0 generate ahbso(2) <= ahbs_none; end generate;
325
326 dcomgen : if CFG_AHB_UART = 1 generate
327 dcom0 : ahbuart -- Debug UART
328 generic map (hindex => NCPU, pindex => 4, paddr => 7)
329 port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
330 dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
331 dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
332 end generate;
333 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
334
335 ahbjtaggen0 : if CFG_AHB_JTAG = 1 generate
336 ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
337 port map(rstn, clkm, gnd(0), gnd(0), gnd(0), open, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
338 open, open, open, open, open, open, open, gnd(0));
339 end generate;
340
341
342 ----------------------------------------------------------------------
343 --- Memory controllers ----------------------------------------------
344 ----------------------------------------------------------------------
345
346 src : if CFG_SRCTRL = 1 generate -- 32-bit PROM/SRAM controller
347 sr0 : srctrl generic map (hindex => 0, ramws => CFG_SRCTRL_RAMWS,
348 romws => CFG_SRCTRL_PROMWS, ramaddr => 16#400#,
349 prom8en => CFG_SRCTRL_8BIT, rmw => CFG_SRCTRL_RMW)
350 port map (rstn, clkm, ahbsi, ahbso(0), memi, memo, sdo3);
351 apbo(0) <= apb_none;
352 end generate;
353
354 mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
355 sr1 : smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
356 srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
357 ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK,
358 sepbus => CFG_MCTRL_SEPBUS, sdbits => 32 + 32*CFG_MCTRL_SD64)
359 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo,
360 s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe);
361 sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
362 sd2 : if CFG_MCTRL_SEPBUS = 1 generate
363 sa_pad : outpadv generic map (width => 12) port map (sa, memo.sa(11 downto 0));
364 sdba_pad : outpadv generic map (width => 2) port map (sdba, memo.sa(14 downto 13));
365 bdr : for i in 0 to 3 generate
366 sd_pad : iopadv generic map (tech => padtech, width => 8)
367 port map (sd(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
368 memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
369 sd2 : if CFG_MCTRL_SD64 = 1 generate
370 sd_pad2 : iopadv generic map (tech => padtech, width => 8)
371 port map (sd(31-i*8+32 downto 24-i*8+32), memo.data(31-i*8 downto 24-i*8),
372 memo.bdrive(i), memi.sd(31-i*8+32 downto 24-i*8+32));
373 end generate;
374 end generate;
375 end generate;
376 sdwen_pad : outpad generic map (tech => padtech)
377 port map (sdwen, sdo.sdwen);
378 sdras_pad : outpad generic map (tech => padtech)
379 port map (sdrasn, sdo.rasn);
380 sdcas_pad : outpad generic map (tech => padtech)
381 port map (sdcasn, sdo.casn);
382 sddqm_pad : outpadv generic map (width =>4, tech => padtech)
383 port map (sddqm, sdo.dqm(3 downto 0));
384 end generate;
385 sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo.sdcke(0));
386 sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo.sdcsn(0));
387 end generate;
388
389 wpn <= '1'; byten <= '0';
390
391 nosd0 : if (CFG_MCTRL_LEON2 = 0) generate -- no SDRAM controller
392 sdcke_pad : outpad generic map (tech => padtech) port map (sdcke, sdo3.sdcke(0));
393 sdcsn_pad : outpad generic map (tech => padtech) port map (sdcsn, sdo3.sdcsn(0));
394 end generate;
395
396 memi.brdyn <= '1'; memi.bexcn <= '1';
397 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
398
399 mg0 : if not ((CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1)) generate -- no prom/sram pads
400 apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
401 rams_pad : outpad generic map (tech => padtech)
402 port map (ramsn, vcc(0));
403 roms_pad : outpad generic map (tech => padtech)
404 port map (romsn, vcc(0));
405 end generate;
406
407 mgpads : if (CFG_SRCTRL = 1) or (CFG_MCTRL_LEON2 = 1) generate -- prom/sram pads
408 addr_pad : outpadv generic map (width => 24, tech => padtech)
409 port map (address, memo.address(23 downto 0));
410 memb_pad : outpadv generic map (width => 4, tech => padtech)
411 port map (mben, memo.mben);
412 rams_pad : outpad generic map (tech => padtech)
413 port map (ramsn, memo.ramsn(0));
414 roms_pad : outpad generic map (tech => padtech)
415 port map (romsn, memo.romsn(0));
416 oen_pad : outpad generic map (tech => padtech)
417 port map (oen, memo.oen);
418 rwen_pad : outpad generic map (tech => padtech)
419 port map (rwen, memo.wrn(0));
420 roen_pad : outpad generic map (tech => padtech)
421 port map (ramoen, memo.ramoen(0));
422 wri_pad : outpad generic map (tech => padtech)
423 port map (writen, memo.writen);
424 -- pragma translate_off
425 iosn_pad : outpad generic map (tech => padtech)
426 port map (iosn, memo.iosn);
427 -- pragma translate_on
428
429 -- for smc lan chip
430 eth_aen_pad : outpad generic map (tech => padtech)
431 port map (eth_aen, s_eth_aen);
432 eth_readn_pad : outpad generic map (tech => padtech)
433 port map (eth_readn, s_eth_readn);
434 eth_writen_pad : outpad generic map (tech => padtech)
435 port map (eth_writen, s_eth_writen);
436 eth_nbe_pad : outpadv generic map (width => 4, tech => padtech)
437 port map (eth_nbe, s_eth_nbe);
438
439 bdr : for i in 0 to 3 generate
440 data_pad : iopadv generic map (tech => padtech, width => 8)
441 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
442 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
443 end generate;
444 end generate;
445
446 ----------------------------------------------------------------------
447 --- APB Bridge and various periherals -------------------------------
448 ----------------------------------------------------------------------
449
450 apb0 : apbctrl -- AHB/APB bridge
451 generic map (hindex => 1, haddr => CFG_APBADDR)
452 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
453
454 ua1 : if CFG_UART1_ENABLE /= 0 generate
455 uart1 : apbuart -- UART 1
456 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
457 fifosize => CFG_UART1_FIFO)
458 port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
459 u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
460 end generate;
461 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
462
463 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
464 irqctrl0 : irqmp -- interrupt controller
465 generic map (pindex => 2, paddr => 2, ncpu => NCPU)
466 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
467 end generate;
468 irq3 : if CFG_IRQ3_ENABLE = 0 generate
469 x : for i in 0 to NCPU-1 generate
470 irqi(i).irl <= "0000";
471 end generate;
472 apbo(2) <= apb_none;
473 end generate;
474
475 gpt : if CFG_GPT_ENABLE /= 0 generate
476 timer0 : gptimer -- timer unit
477 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
478 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
479 nbits => CFG_GPT_TW)
480 port map (rstn, clkm, apbi, apbo(3), gpti, open);
481 gpti.dhalt <= dsuo.active; gpti.extclk <= '0';
482 end generate;
483 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
484
485 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
486 grgpio0: grgpio
487 generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
488 port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
489 gpioi => gpioi, gpioo => gpioo);
490 pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
491 pio_pad : iopad generic map (tech => padtech)
492 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
493 end generate;
494 end generate;
495
496
497 -- plldotheora1: plldotheora
498 -- port map (
499 -- inclk0 => clk,
500 -- c0 => clk_25Mhz
501 -- );
502
503 theora_hardware1 : theora_amba_interface -- casca_amba
504 generic map (pindex => 8, paddr => 8, pmask => 16#FFF#) --
505 port map (rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
506 clk_25Mhz => clk_25Mhz,--clkm
507 red => red,
508 green => green,
509 blue => blue,
510 -- line_pixel => line_pixel,
511 -- column_pixel => column_pixel,
512 m1 => m1,
513 m2 => m2,
514 blank_n => blank_n,
515 sync_n => sync_n,
516 sync_t => sync_t,
517 video_clk => video_clk,
518 vga_vs => vga_vs,
519 vga_hs => vga_hs
520 );
521
522 -----------------------------------------------------------------------
523 --- ATA Controller ---------------------------------------------------
524 -----------------------------------------------------------------------
525 atac : if CFG_ATA = 1 generate
526 atac0 : atactrl
527 generic map(
528 hindex => 5,
529 haddr => CFG_ATAIO,
530 hmask => 16#fff#,
531 pirq => CFG_ATAIRQ,
532
533 TWIDTH => 8, -- counter width
534
535 -- PIO mode 0 settings (@100MHz clock)
536 PIO_mode0_T1 => 6, -- 70ns
537 PIO_mode0_T2 => 28, -- 290ns
538 PIO_mode0_T4 => 2, -- 30ns
539 PIO_mode0_Teoc => 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
540 )
541 port map(
542 rst => rstn,
543 arst => '1',
544 clk => clkm,
545 ahbsi => ahbsi,
546 ahbso => ahbso(5),
547 cfo => cf,
548
549 -- ATA signals
550 ata_resetn => ata.rst,
551 ddin => ata.ddi,
552 ddout => ata.ddo,
553 ddoe => ata.oen,
554 da => ata.da,
555 cs0n => ata.cs0,
556 cs1n => ata.cs1,
557 diorn => ata.dior,
558 diown => ata.diow,
559 iordy => ata.iordy,
560 intrq => ata.intrq,
561 dmack => ata.dmack
562 );
563
564 -- pragma translate_off
565 ata_rst_pad : outpad generic map (tech => padtech)
566 port map (ata_rst, ata.rst);
567 -- pragma translate_on
568 ata_data_pad : iopadv generic map (tech => padtech, width => 16, oepol => 1)
569 port map (ata_data, ata.ddo, ata.oen, ata.ddi);
570 ata_da_pad : outpadv generic map (tech => padtech, width => 3)
571 port map (ata_da, ata.da);
572 ata_cs0_pad : outpad generic map (tech => padtech)
573 port map (ata_cs0, ata.cs0);
574 ata_cs1_pad : outpad generic map (tech => padtech)
575 port map (ata_cs1, ata.cs1);
576 ata_dior_pad : outpad generic map (tech => padtech)
577 port map (ata_dior, ata.dior);
578 ata_diow_pad : outpad generic map (tech => padtech)
579 port map (ata_diow, ata.diow);
580 iordy_pad : inpad generic map (tech => padtech)
581 port map (ata_iordy, ata.iordy);
582 intrq_pad : inpad generic map (tech => padtech)
583 port map (ata_intrq, ata.intrq);
584 dmack_pad : outpad generic map (tech => padtech)
585 port map (ata_dmack, ata.dmack);
586
587 -- for CompactFlach mode selection
588 cf_gnd_da_pad : outpadv generic map (tech => padtech, width => 8)
589 port map (cf_gnd_da, cf.da);
590 cf_atasel_pad : outpad generic map (tech => padtech)
591 port map (cf_atasel, cf.atasel);
592 cf_we_pad : outpad generic map (tech => padtech)
593 port map (cf_we, cf.we);
594 cf_power_pad : outpad generic map (tech => padtech)
595 port map (cf_power, cf.power);
596 cf_csel_pad : outpad generic map (tech => padtech)
597 port map (cf_csel, cf.csel);
598
599 end generate;
600
601 -----------------------------------------------------------------------
602 --- AHB ROM ----------------------------------------------------------
603 -----------------------------------------------------------------------
604
605 bpromgen : if CFG_AHBROMEN /= 0 generate
606 brom : entity work.ahbrom
607 generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
608 port map ( rstn, clkm, ahbsi, ahbso(6));
609 end generate;
610 nobpromgen : if CFG_AHBROMEN = 0 generate
611 ahbso(6) <= ahbs_none;
612 end generate;
613
614 -----------------------------------------------------------------------
615 --- AHB RAM ----------------------------------------------------------
616 -----------------------------------------------------------------------
617
618 ahbramgen : if CFG_AHBRAMEN = 1 generate
619 ahbram0 : ahbram generic map (hindex => 3, haddr => CFG_AHBRADDR,
620 tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
621 port map (rstn, clkm, ahbsi, ahbso(3));
622 end generate;
623 nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
624
625 -----------------------------------------------------------------------
626 --- Drive unused bus elements ---------------------------------------
627 -----------------------------------------------------------------------
628
629 nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
630 ahbmo(i) <= ahbm_none;
631 end generate;
632 nap0 : for i in 9 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
633 apbo(6) <= apb_none;
634 nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
635
636 -- invert signal for input via a key
637 dsubre <= not dsubren;
638
639 -- for smc lan chip
640 eth_lclk <= vcc(0);
641 eth_nads <= gnd(0);
642 eth_ncycle <= vcc(0);
643 eth_wnr <= vcc(0);
644 eth_nvlbus <= vcc(0);
645 eth_nrdyrtn <= vcc(0);
646 eth_ndatacs <= vcc(0);
647
648 -----------------------------------------------------------------------
649 --- Boot message ----------------------------------------------------
650 -----------------------------------------------------------------------
651
652 -- pragma translate_off
653 x : report_version
654 generic map (
655 msg1 => "LEON3 Altera EP2C60 SDR Demonstration design",
656 msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
657 & "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
658 msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
659 mdel => 1
660 );
661 -- pragma translate_on
662
663 end;
Automatic mirror of xiph.org svn repository