theora-fpga/testbenchs/expandblock/dual_syncram.vhd

   1 library IEEE;
   2 use IEEE.std_logic_1164.all;
   3 use IEEE.numeric_std.all;
   4
   5
   6 -- This entity will infferr two identical block rams
   7 -- to permit two reads in the same clock cicle.
   8
   9 entity dual_syncram is
  10   generic (
  11     DEPTH : positive := 64;             -- How many slots
  12     DATA_WIDTH : positive := 16;        -- How many bits per slot
  13     ADDR_WIDTH : positive := 6          -- = ceil(log2(DEPTH))
  14     );
  15   port (
  16     clk : in std_logic;
  17     wr_e  : in std_logic;
  18     wr_addr : in unsigned(ADDR_WIDTH-1 downto 0);
  19     wr_data : in signed(DATA_WIDTH-1 downto 0);
  20     rd1_addr : in unsigned(ADDR_WIDTH-1 downto 0);
  21     rd1_data : out signed(DATA_WIDTH-1 downto 0);
  22     rd2_addr : in unsigned(ADDR_WIDTH-1 downto 0);
  23     rd2_data : out signed(DATA_WIDTH-1 downto 0)
  24     );
  25 end entity dual_syncram;
  26
  27 architecture rtl of dual_syncram is
  28
  29   type MEM_TYPE is array(0 to DEPTH-1) of
  30     signed(DATA_WIDTH-1 downto 0);
  31   signal memory : MEM_TYPE;
  32 begin
  33
  34   process( clk )
  35   begin
  36     if ( rising_edge(clk) ) then
  37       if ( wr_e = '1' ) then
  38         memory( to_integer(wr_addr) ) <= wr_data;
  39       end if;
  40       rd1_data <= memory( to_integer(rd1_addr) );
  41       rd2_data <= memory( to_integer(rd2_addr) );
  42     end if;
  43   end process;
  44
  45 end rtl;