theora-fpga/theora_hardware/databuffer.vhd

   1 -------------------------------------------------------------------------------
   2 --  Description: This file implements a big buffer to keep
   3 --               the roconstructed frames (This, Golden and Last)
   4 -------------------------------------------------------------------------------
   5
   6 library std;
   7 library ieee;
   8 library work;
   9
  10 use ieee.std_logic_1164.all;
  11 use ieee.numeric_std.all;
  12 use work.all;
  13
  14 entity DataBuffer is
  15
  16   port (Clk,
  17         Reset_n       :       in std_logic;
  18
  19         in_request    :       out std_logic;
  20         in_valid      :       in std_logic;
  21         in_addr       :       in unsigned(19 downto 0);
  22         in_data       :       in signed(31 downto 0);
  23
  24
  25         out_requested :       in std_logic;
  26         out_valid     :       out std_logic;
  27         out_addr      :       in unsigned(19 downto 0);
  28         out_data      :       out signed(31 downto 0)
  29         );
  30 end DataBuffer;
  31
  32
  33 architecture a_DataBuffer of DataBuffer is
  34   component tsyncram
  35     generic (
  36       DEPTH : positive := 64;             -- How many slots
  37       DATA_WIDTH : positive := 16;        -- How many bits per slot
  38       ADDR_WIDTH : positive := 6          -- = ceil(log2(DEPTH))
  39       );
  40     port (
  41       clk : in std_logic;
  42       wr_e  : in std_logic;
  43       wr_addr : in unsigned(ADDR_WIDTH-1 downto 0);
  44       wr_data : in signed(DATA_WIDTH-1 downto 0);
  45       rd_addr : in unsigned(ADDR_WIDTH-1 downto 0);
  46       rd_data : out signed(DATA_WIDTH-1 downto 0)
  47       );
  48   end component;
  49
  50
  51   signal count : integer;
  52 -- Handshake
  53   signal s_in_request : std_logic;
  54   signal s_out_valid : std_logic;
  55
  56   constant MEM_DEPTH : natural := 16384;
  57   constant MEM_DATA_WIDTH : natural := 32;
  58   constant MEM_ADDR_WIDTH : natural := 20;
  59
  60   signal mem_wr_e     : std_logic;
  61   signal mem_wr_addr  : unsigned(MEM_ADDR_WIDTH-1 downto 0);
  62   signal mem_wr_data  : signed(MEM_DATA_WIDTH-1 downto 0);
  63   signal mem_rd_addr  : unsigned(MEM_ADDR_WIDTH-1 downto 0);
  64   signal mem_rd_data  : signed(MEM_DATA_WIDTH-1 downto 0);
  65
  66 begin  -- a_DataBuffer
  67   in_request <= s_in_request;
  68   out_valid <= s_out_valid;
  69
  70   mem_int32: tsyncram
  71     generic map (MEM_DEPTH, MEM_DATA_WIDTH, MEM_ADDR_WIDTH)
  72     port map (clk, mem_wr_e, mem_wr_addr, mem_wr_data,
  73               mem_rd_addr, mem_rd_data);
  74
  75   process (clk)
  76
  77   begin  -- process
  78
  79     if (clk'event and clk = '1') then
  80       if (Reset_n = '0') then
  81         s_in_request <= '0';
  82         s_out_valid <= '0';
  83
  84         count <= 0;
  85 --memory's signals
  86         mem_wr_e <= '0';
  87         mem_wr_addr <= x"00000";
  88         mem_wr_data <= x"00000000";
  89         mem_rd_addr <= x"00000";
  90       else
  91
  92         s_out_valid <= '0';
  93         s_in_request <= '1';
  94         mem_wr_e <= '0';
  95         if (s_in_request = '1' and in_valid = '1') then
  96           mem_wr_e <= '1';
  97           mem_wr_data <= in_data;
  98           mem_wr_addr <= in_addr;
  99         end if;
 100         count <= 0;
 101         if (out_requested = '1' and s_out_valid = '0') then
 102           if (count = 0) then
 103             mem_rd_addr <= out_addr;
 104             count <= count + 1;
 105           elsif (count = 1) then
 106             count <= count + 1;
 107           else
 108             out_data <= mem_rd_data;
 109             s_out_valid <= '1';
 110             count <= 0;
 111           end if;
 112         end if;
 113       end if;
 114     end if;
 115   end process;
 116
 117 end a_DataBuffer;