include/powerpc.h

   1 /*      $Id: powerpc.h,v 1.1.1.1 2006/09/14 01:59:06 root Exp $ */
   2
   3 /*
   4  * Copyright (c) 2001 ipUnplugged AB (www.ipunplugged.com)
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed for Patrik Lindergren, by
  17  *      ipUnplugged AB, Sweden.
  18  * 4. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
  22  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  */
  34
  35
  36 /*
  37  * PowerPC Special Registers
  38  */
  39 #define CTR     9
  40 #define SPRG0   272
  41 #define SPRG1   273
  42 #define SPRG2   274
  43 #define SPRG3   275
  44 #define PVR     287
  45 #define HID0    1008
  46 #define HID1    1009
  47 #define L2CR    1017
  48
  49
  50 /*
  51  * Hardware Implementation-Dependent Register 0 (HID0)
  52  */
  53 #define HID0_NMCP       0x80000000      /* Enable MCP */
  54 #define HID0_EBA        0x20000000      /* Enable/Disable system bus address parity check */
  55 #define HID0_EBD        0x10000000      /* Enable/Disable system bus data parity check */
  56 #define HID0_BCLK       0x08000000      /* CLK_OUT output enable aned clock selection */
  57 #define HID0_ECLK       0x02000000      /* CLK_OUT output enable aned clock selection */
  58 #define HID0_PAR        0x01000000      /* Disable precharge of ARTRY* amd SHD[0] or SHD[1] */
  59 #define HID0_DOZE       0x00800000      /* Doze Mode Enable */
  60 #define HID0_NAP        0x00400000      /* NAP Mode enable */
  61 #define HID0_SLEEP      0x00200000      /* Sleep Mode Enable */
  62 #define HID0_DPM        0x00100000      /* Dynamic Power Management enable */
  63 #define HID0_EIEC       0x00040000      /* Enable internal error checking */
  64 #define HID0_NHR        0x00010000      /* Not hard reset */
  65 #define HID0_ICE        0x00008000      /* Instruction Cache Enable */
  66 #define HID0_DCE        0x00004000      /* Data Cache enable */
  67 #define HID0_ILOCK      0x00002000      /* Instruction cache Lock */
  68 #define HID0_DLOCK      0x00001000      /* Data cache Lock*/
  69 #define HID0_ICFI       0x00000800      /* Instruction cache invalidate */
  70 #define HID0_DCFI       0x00000400      /* Data cache flash invalidate */
  71 #define HID0_SPD        0x00000200      /* Speculative data and instruction cache */
  72 #define HID0_IFTT       0x00000100      /* I-Fetch TTx encoding differentiation */
  73 #define HID0_SGE        0x00000080      /* Store gathering enable */
  74 #define HID0_DCFA       0x00000040      /* Data Cache Flush assist */
  75 #define HID0_BTIC       0x00000020      /* Branch Target Instruction Cache enable */
  76 #define HID0_BHTE       0x00000004      /* Branch History Table enable */
  77 #define HID0_NOPDST     0x00000002      /* No-Op dst, dstt, dstst and dststt instructions */
  78 #define HID0_NOPTI      0x00000001      /* No-Op the data cache touch instructions */
  79
  80 /* Defines for MPC740/750/7400 L2-Cache register L2CR */
  81
  82 #define L2CR_L2E           (0x80000000)  /* Enable cache    */
  83 #define L2CR_L2PE          (0x40000000)  /* Parity enable   */
  84 #define L2CR_L2SIZ_256     (0x10000000)  /* Cache of 256KB  */
  85 #define L2CR_L2SIZ_512     (0x20000000)  /* Cache of 512KB */
  86 #define L2CR_L2SIZ_1024    (0x30000000)  /* Cache of 1024KB */
  87 #define L2CR_L2SIZ_2048    (0x00000000)  /* Cache of 2048KB */
  88 #define L2CR_L2CLK_DIS     (0x00000000)  /* Disable DLL+CLK */
  89 #define L2CR_L2CLK_1       (0x02000000)  /* Div by 1   */
  90 #define L2CR_L2CLK_15      (0x04000000)  /* Div by 1.5 */
  91 #define L2CR_L2CLK_35      (0x06000000)  /* Div by 3.5 */
  92 #define L2CR_L2CLK_2       (0x08000000)  /* Div by 2   */
  93 #define L2CR_L2CLK_25      (0x0A000000)  /* Div by 2.5 */
  94 #define L2CR_L2CLK_3       (0x0C000000)  /* Div by 3   */
  95 #define L2CR_L2CLK_4       (0x0E000000)  /* Div by 4   */
  96 #define L2CR_L2CLK_SPEED_MSK (0x10)      /* Cache speed mask */
  97 #define L2CR_L2RAM_FLOW    (0x00000000)  /* flow sync burst RAM*/
  98 #define L2CR_L2RAM_RES     (0x00800000)  /* reserved   */
  99 #define L2CR_L2RAM_PIPE    (0x01000000)  /* pipl sync burst RAM*/
 100 #define L2CR_L2RAM_LATEW   (0x01800000)  /* late write sync RAM*/
 101 #define L2CR_L2DO          (0x00400000)  /* Enable Data only caching*/
 102 #define L2CR_L2I           (0x00200000)  /* Enable Cache Invalidation*/
 103 #define L2CR_L2CTL         (0x00100000)  /* Enable low power mode ZZ */
 104 #define L2CR_L2WT          (0x00080000)  /* Enable write-thru mode */
 105 #define L2CR_L2TS          (0x00040000)  /* Enable test mode */
 106 #define L2CR_L2OH_05       (0x00000000)  /* Output hold of 0.5ns */
 107 #define L2CR_L2OH_10       (0x00010000)  /* Output hold of 1.0ns */
 108 #define L2CR_L2OH_MOUT     (0x00020000)  /* more output hold */
 109 #define L2CR_L2OH_EMOUT    (0x00030000)  /* even more output hold */
 110 #define L2CR_L2SL          (0x00008000)  /* Enable DLL slow for L2-clock < 100MHz*/
 111 #define L2CR_L2DF          (0x00004000)  /* Enable differential clock pins */
 112 #define L2CR_L2BYP         (0x00002000)  /* Enable DLL bypass */
 113 #define L2CR_L2FA          (0x00001000)  /* Flush Assist bit */
 114 #define L2CR_L2HWF         (0x00000800)  /* Start HW flusg operation of L2 Cache */
 115 #define L2CR_L2IO          (0x00000400)  /* L2 Instruction cache only enable */
 116 #define L2CR_L2CLKSTP      (0x00000200)  /* Enable clock stop to L2 cache rams */
 117 #define L2CR_L2DRO         (0x00000100)  /* Roll-over enable for DLL */
 118 #define L2CR_L2CTR         (0x000000FE)  /* Mask for L2CR_L2CTR DLL 127..0 counter */
 119 #define L2CR_L2IP          (0x00000001)  /* RO, Indicate invalidate in progress */
 120
 121 /*
 122  * Machine State Register (MSR)
 123  */
 124 #define PPC_MSR_FP      0x00002000
 125
 126 #define GETHID1(x) \
 127          __asm __volatile("mfspr %0, 1009" : "=r"(x));
 128
 129 #ifdef __ASSEMBLER__
 130 #define HIADJ(x)        (x)@ha
 131 #define HI(x)           (x)@h
 132 #define LO(x)           (x)@l
 133
 134 /*
 135  *  Use this macro to prevent reordering by as/ld and processor
 136  */
 137 #define IORDER          eieio; sync
 138
 139 /*
 140  *  Macros used to setup BAT regs.
 141  */
 142 #define IBAT_SETUP(batno, batuval, batlval)     \
 143         lis 3, HIADJ(batuval); addi 3, 3, LO(batuval);  \
 144         lis 4, HIADJ(batlval); addi 4, 4, LO(batlval);  \
 145         mtibatu batno, 3; mtibatl batno, 4
 146
 147 #define DBAT_SETUP(batno, batuval, batlval)     \
 148         lis 3, HIADJ(batuval); addi 3, 3, LO(batuval);  \
 149         lis 4, HIADJ(batlval); addi 4, 4, LO(batlval);  \
 150         mtdbatu batno, 3; mtdbatl batno, 4
 151
 152 #endif /* __ASSEMBLER__ */
 153