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[xorg_rtime.git] / xorg-server-1.4 / hw / xfree86 / os-support / bus / xf86Pci.h
blobc444a0cd1265e93436e7b02cc9a60725ad4b3ae6
1 /*
2 * Copyright 1998 by Concurrent Computer Corporation
3 *
4 * Permission to use, copy, modify, distribute, and sell this software
5 * and its documentation for any purpose is hereby granted without fee,
6 * provided that the above copyright notice appear in all copies and that
7 * both that copyright notice and this permission notice appear in
8 * supporting documentation, and that the name of Concurrent Computer
9 * Corporation not be used in advertising or publicity pertaining to
10 * distribution of the software without specific, written prior
11 * permission. Concurrent Computer Corporation makes no representations
12 * about the suitability of this software for any purpose. It is
13 * provided "as is" without express or implied warranty.
14 *
15 * CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD
16 * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
17 * AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE
18 * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
19 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
20 * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
21 * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
22 * SOFTWARE.
23 *
24 * Copyright 1998 by Metro Link Incorporated
25 *
26 * Permission to use, copy, modify, distribute, and sell this software
27 * and its documentation for any purpose is hereby granted without fee,
28 * provided that the above copyright notice appear in all copies and that
29 * both that copyright notice and this permission notice appear in
30 * supporting documentation, and that the name of Metro Link
31 * Incorporated not be used in advertising or publicity pertaining to
32 * distribution of the software without specific, written prior
33 * permission. Metro Link Incorporated makes no representations
34 * about the suitability of this software for any purpose. It is
35 * provided "as is" without express or implied warranty.
36 *
37 * METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD
38 * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
39 * AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE
40 * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
41 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
42 * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
43 * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
44 * SOFTWARE.
45 *
46 * This file is derived in part from the original xf86_PCI.h that included
47 * following copyright message:
48 *
49 * Copyright 1995 by Robin Cutshaw <robin@XFree86.Org>
50 *
51 * Permission to use, copy, modify, distribute, and sell this software and its
52 * documentation for any purpose is hereby granted without fee, provided that
53 * the above copyright notice appear in all copies and that both that
54 * copyright notice and this permission notice appear in supporting
55 * documentation, and that the names of the above listed copyright holder(s)
56 * not be used in advertising or publicity pertaining to distribution of
57 * the software without specific, written prior permission. The above listed
58 * copyright holder(s) make(s) no representations about the suitability of this
59 * software for any purpose. It is provided "as is" without express or
60 * implied warranty.
61 *
62 * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD
63 * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
64 * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE
65 * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
66 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
67 * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
68 * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
69 *
70 */
71 /*
72 * Copyright (c) 1999-2003 by The XFree86 Project, Inc.
73 *
74 * Permission is hereby granted, free of charge, to any person obtaining a
75 * copy of this software and associated documentation files (the "Software"),
76 * to deal in the Software without restriction, including without limitation
77 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
78 * and/or sell copies of the Software, and to permit persons to whom the
79 * Software is furnished to do so, subject to the following conditions:
80 *
81 * The above copyright notice and this permission notice shall be included in
82 * all copies or substantial portions of the Software.
83 *
84 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
85 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
86 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
87 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
88 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
89 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
90 * OTHER DEALINGS IN THE SOFTWARE.
91 *
92 * Except as contained in this notice, the name of the copyright holder(s)
93 * and author(s) shall not be used in advertising or otherwise to promote
94 * the sale, use or other dealings in this Software without prior written
95 * authorization from the copyright holder(s) and author(s).
96 */
97
98
99 /*
100 * This file contains just the public interface to the PCI code.
101 * Drivers should use this file rather than Pci.h.
102 */
103
104 #ifndef _XF86PCI_H
105 #define _XF86PCI_H 1
106 #include <X11/Xarch.h>
107 #include <X11/Xfuncproto.h>
108 #include "misc.h"
109
110 #define PCI_NOT_FOUND 0xFFFFFFFFU
111
112 /*
113 * PCI cfg space definitions (e.g. stuff right out of the PCI spec)
114 */
115
116 /* Device identification register */
117 #define PCI_ID_REG 0x00
118
119 /* Command and status register */
120 #define PCI_CMD_STAT_REG 0x04
121 #define PCI_CMD_BASE_REG 0x10
122 #define PCI_CMD_BIOS_REG 0x30
123 #define PCI_CMD_MASK 0xffff
124 #define PCI_CMD_IO_ENABLE 0x01
125 #define PCI_CMD_MEM_ENABLE 0x02
126 #define PCI_CMD_MASTER_ENABLE 0x04
127 #define PCI_CMD_SPECIAL_ENABLE 0x08
128 #define PCI_CMD_INVALIDATE_ENABLE 0x10
129 #define PCI_CMD_PALETTE_ENABLE 0x20
130 #define PCI_CMD_PARITY_ENABLE 0x40
131 #define PCI_CMD_STEPPING_ENABLE 0x80
132 #define PCI_CMD_SERR_ENABLE 0x100
133 #define PCI_CMD_BACKTOBACK_ENABLE 0x200
134 #define PCI_CMD_BIOS_ENABLE 0x01
135
136 /* base class */
137 #define PCI_CLASS_REG 0x08
138 #define PCI_CLASS_MASK 0xff000000
139 #define PCI_CLASS_SHIFT 24
140 #define PCI_CLASS_EXTRACT(x) \
141 (((x) & PCI_CLASS_MASK) >> PCI_CLASS_SHIFT)
142
143 /* base class values */
144 #define PCI_CLASS_PREHISTORIC 0x00
145 #define PCI_CLASS_MASS_STORAGE 0x01
146 #define PCI_CLASS_NETWORK 0x02
147 #define PCI_CLASS_DISPLAY 0x03
148 #define PCI_CLASS_MULTIMEDIA 0x04
149 #define PCI_CLASS_MEMORY 0x05
150 #define PCI_CLASS_BRIDGE 0x06
151 #define PCI_CLASS_COMMUNICATIONS 0x07
152 #define PCI_CLASS_SYSPERIPH 0x08
153 #define PCI_CLASS_INPUT 0x09
154 #define PCI_CLASS_DOCKING 0x0a
155 #define PCI_CLASS_PROCESSOR 0x0b
156 #define PCI_CLASS_SERIALBUS 0x0c
157 #define PCI_CLASS_WIRELESS 0x0d
158 #define PCI_CLASS_I2O 0x0e
159 #define PCI_CLASS_SATELLITE 0x0f
160 #define PCI_CLASS_CRYPT 0x10
161 #define PCI_CLASS_DATA_ACQUISTION 0x11
162 #define PCI_CLASS_UNDEFINED 0xff
163
164 /* sub class */
165 #define PCI_SUBCLASS_MASK 0x00ff0000
166 #define PCI_SUBCLASS_SHIFT 16
167 #define PCI_SUBCLASS_EXTRACT(x) \
168 (((x) & PCI_SUBCLASS_MASK) >> PCI_SUBCLASS_SHIFT)
169
170 /* Sub class values */
171 /* 0x00 prehistoric subclasses */
172 #define PCI_SUBCLASS_PREHISTORIC_MISC 0x00
173 #define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
174
175 /* 0x01 mass storage subclasses */
176 #define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00
177 #define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01
178 #define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
179 #define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
180 #define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
181
182 /* 0x02 network subclasses */
183 #define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
184 #define PCI_SUBCLASS_NETWORK_TOKENRING 0x01
185 #define PCI_SUBCLASS_NETWORK_FDDI 0x02
186 #define PCI_SUBCLASS_NETWORK_MISC 0x80
187
188 /* 0x03 display subclasses */
189 #define PCI_SUBCLASS_DISPLAY_VGA 0x00
190 #define PCI_SUBCLASS_DISPLAY_XGA 0x01
191 #define PCI_SUBCLASS_DISPLAY_MISC 0x80
192
193 /* 0x04 multimedia subclasses */
194 #define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00
195 #define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
196 #define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80
197
198 /* 0x05 memory subclasses */
199 #define PCI_SUBCLASS_MEMORY_RAM 0x00
200 #define PCI_SUBCLASS_MEMORY_FLASH 0x01
201 #define PCI_SUBCLASS_MEMORY_MISC 0x80
202
203 /* 0x06 bridge subclasses */
204 #define PCI_SUBCLASS_BRIDGE_HOST 0x00
205 #define PCI_SUBCLASS_BRIDGE_ISA 0x01
206 #define PCI_SUBCLASS_BRIDGE_EISA 0x02
207 #define PCI_SUBCLASS_BRIDGE_MC 0x03
208 #define PCI_SUBCLASS_BRIDGE_PCI 0x04
209 #define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05
210 #define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
211 #define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
212 #define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08
213 #define PCI_SUBCLASS_BRIDGE_MISC 0x80
214 #define PCI_IF_BRIDGE_PCI_SUBTRACTIVE 0x01
215
216 /* 0x07 communications controller subclasses */
217 #define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
218 #define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01
219 #define PCI_SUBCLASS_COMMUNICATIONS_MULTISERIAL 0x02
220 #define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03
221 #define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80
222
223 /* 0x08 generic system peripherals subclasses */
224 #define PCI_SUBCLASS_SYSPERIPH_PIC 0x00
225 #define PCI_SUBCLASS_SYSPERIPH_DMA 0x01
226 #define PCI_SUBCLASS_SYSPERIPH_TIMER 0x02
227 #define PCI_SUBCLASS_SYSPERIPH_RTC 0x03
228 #define PCI_SUBCLASS_SYSPERIPH_HOTPCI 0x04
229 #define PCI_SUBCLASS_SYSPERIPH_MISC 0x80
230
231 /* 0x09 input device subclasses */
232 #define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
233 #define PCI_SUBCLASS_INPUT_DIGITIZER 0x01
234 #define PCI_SUBCLASS_INPUT_MOUSE 0x02
235 #define PCI_SUBCLASS_INPUT_SCANNER 0x03
236 #define PCI_SUBCLASS_INPUT_GAMEPORT 0x04
237 #define PCI_SUBCLASS_INPUT_MISC 0x80
238
239 /* 0x0a docking station subclasses */
240 #define PCI_SUBCLASS_DOCKING_GENERIC 0x00
241 #define PCI_SUBCLASS_DOCKING_MISC 0x80
242
243 /* 0x0b processor subclasses */
244 #define PCI_SUBCLASS_PROCESSOR_386 0x00
245 #define PCI_SUBCLASS_PROCESSOR_486 0x01
246 #define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02
247 #define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10
248 #define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
249 #define PCI_SUBCLASS_PROCESSOR_MIPS 0x30
250 #define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
251
252 /* 0x0c serial bus controller subclasses */
253 #define PCI_SUBCLASS_SERIAL_FIREWIRE 0x00
254 #define PCI_SUBCLASS_SERIAL_ACCESS 0x01
255 #define PCI_SUBCLASS_SERIAL_SSA 0x02
256 #define PCI_SUBCLASS_SERIAL_USB 0x03
257 #define PCI_SUBCLASS_SERIAL_FIBRECHANNEL 0x04
258 #define PCI_SUBCLASS_SERIAL_SMBUS 0x05
259
260 /* 0x0d wireless controller subclasses */
261 #define PCI_SUBCLASS_WIRELESS_IRDA 0x00
262 #define PCI_SUBCLASS_WIRELESS_CONSUMER_IR 0x01
263 #define PCI_SUBCLASS_WIRELESS_RF 0x02
264 #define PCI_SUBCLASS_WIRELESS_MISC 0x80
265
266 /* 0x0e intelligent I/O controller subclasses */
267 #define PCI_SUBCLASS_I2O_I2O 0x00
268
269 /* 0x0f satellite communications controller subclasses */
270 #define PCI_SUBCLASS_SATELLITE_TV 0x01
271 #define PCI_SUBCLASS_SATELLITE_AUDIO 0x02
272 #define PCI_SUBCLASS_SATELLITE_VOICE 0x03
273 #define PCI_SUBCLASS_SATELLITE_DATA 0x04
274
275 /* 0x10 encryption/decryption controller subclasses */
276 #define PCI_SUBCLASS_CRYPT_NET_COMPUTING 0x00
277 #define PCI_SUBCLASS_CRYPT_ENTERTAINMENT 0x10
278 #define PCI_SUBCLASS_CRYPT_MISC 0x80
279
280 /* 0x11 data acquisition and signal processing controller subclasses */
281 #define PCI_SUBCLASS_DATAACQ_DPIO 0x00
282 #define PCI_SUBCLASS_DATAACQ_MISC 0x80
283
284
285 /* Header */
286 #define PCI_HEADER_MISC 0x0c
287 #define PCI_HEADER_MULTIFUNCTION 0x00800000
288
289 /* Interrupt configration register */
290 #define PCI_INTERRUPT_REG 0x3c
291 #define PCI_INTERRUPT_PIN_MASK 0x0000ff00
292 #define PCI_INTERRUPT_PIN_EXTRACT(x) \
293 ((((x) & PCI_INTERRUPT_PIN_MASK) >> 8) & 0xff)
294 #define PCI_INTERRUPT_PIN_NONE 0x00
295 #define PCI_INTERRUPT_PIN_A 0x01
296 #define PCI_INTERRUPT_PIN_B 0x02
297 #define PCI_INTERRUPT_PIN_C 0x03
298 #define PCI_INTERRUPT_PIN_D 0x04
299
300 #define PCI_INTERRUPT_LINE_MASK 0x000000ff
301 #define PCI_INTERRUPT_LINE_EXTRACT(x) \
302 ((((x) & PCI_INTERRUPT_LINE_MASK) >> 0) & 0xff)
303 #define PCI_INTERRUPT_LINE_INSERT(x,v) \
304 (((x) & ~PCI_INTERRUPT_LINE_MASK) | ((v) << 0))
305
306 /* Base registers */
307 #define PCI_MAP_REG_START 0x10
308 #define PCI_MAP_REG_END 0x28
309 #define PCI_MAP_ROM_REG 0x30
310
311 #define PCI_MAP_MEMORY 0x00000000
312 #define PCI_MAP_IO 0x00000001
313
314 #define PCI_MAP_MEMORY_TYPE 0x00000007
315 #define PCI_MAP_IO_TYPE 0x00000003
316
317 #define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000
318 #define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002
319 #define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004
320 #define PCI_MAP_MEMORY_TYPE_MASK 0x00000006
321 #define PCI_MAP_MEMORY_CACHABLE 0x00000008
322 #define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e
323 #define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0
324
325 #define PCI_MAP_IO_ATTR_MASK 0x00000003
326
327 #define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO)
328 #define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b))
329
330 #define PCI_MAP_IS64BITMEM(b) \
331 (((b) & PCI_MAP_MEMORY_TYPE) == PCI_MAP_MEMORY_TYPE_64BIT)
332
333 #define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
334 #define PCIGETMEMORY64HIGH(b) (*((CARD32*)&(b) + 1))
335 #define PCIGETMEMORY64(b) \
336 (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
337
338 #define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc
339
340 #define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK)
341
342 #define PCI_MAP_ROM_DECODE_ENABLE 0x00000001
343 #define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800
344
345 #define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK)
346
347 /* PCI-PCI bridge mapping registers */
348 #define PCI_PCI_BRIDGE_BUS_REG 0x18
349 #define PCI_SUBORDINATE_BUS_MASK 0x00ff0000
350 #define PCI_SECONDARY_BUS_MASK 0x0000ff00
351 #define PCI_PRIMARY_BUS_MASK 0x000000ff
352
353 #define PCI_PCI_BRIDGE_IO_REG 0x1c
354 #define PCI_PCI_BRIDGE_MEM_REG 0x20
355 #define PCI_PCI_BRIDGE_PMEM_REG 0x24
356
357 #define PCI_PPB_IOBASE_EXTRACT(x) (((x) << 8) & 0xFF00)
358 #define PCI_PPB_IOLIMIT_EXTRACT(x) (((x) << 0) & 0xFF00)
359
360 #define PCI_PPB_MEMBASE_EXTRACT(x) (((x) << 16) & 0xFFFF0000)
361 #define PCI_PPB_MEMLIMIT_EXTRACT(x) (((x) << 0) & 0xFFFF0000)
362
363 #define PCI_PCI_BRIDGE_CONTROL_REG 0x3E
364 #define PCI_PCI_BRIDGE_PARITY_EN 0x01
365 #define PCI_PCI_BRIDGE_SERR_EN 0x02
366 #define PCI_PCI_BRIDGE_ISA_EN 0x04
367 #define PCI_PCI_BRIDGE_VGA_EN 0x08
368 #define PCI_PCI_BRIDGE_MASTER_ABORT_EN 0x20
369 #define PCI_PCI_BRIDGE_SECONDARY_RESET 0x40
370 #define PCI_PCI_BRIDGE_FAST_B2B_EN 0x80
371 /* header type 2 extensions */
372 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
373 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
374 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
375 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
376 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
377
378 #define PCI_CB_SEC_STATUS_REG 0x16 /* Secondary status */
379 #define PCI_CB_PRIMARY_BUS_REG 0x18 /* PCI bus number */
380 #define PCI_CB_CARD_BUS_REG 0x19 /* CardBus bus number */
381 #define PCI_CB_SUBORDINATE_BUS_REG 0x1a /* Subordinate bus number */
382 #define PCI_CB_LATENCY_TIMER_REG 0x1b /* CardBus latency timer */
383 #define PCI_CB_MEM_BASE_0_REG 0x1c
384 #define PCI_CB_MEM_LIMIT_0_REG 0x20
385 #define PCI_CB_MEM_BASE_1_REG 0x24
386 #define PCI_CB_MEM_LIMIT_1_REG 0x28
387 #define PCI_CB_IO_BASE_0_REG 0x2c
388 #define PCI_CB_IO_LIMIT_0_REG 0x30
389 #define PCI_CB_IO_BASE_1_REG 0x34
390 #define PCI_CB_IO_LIMIT_1_REG 0x38
391 #define PCI_CB_BRIDGE_CONTROL_REG 0x3E
392
393 #define PCI_CB_IO_RANGE_MASK ~0x03
394 #define PCI_CB_IOBASE(x) (x & PCI_CB_IO_RANGE_MASK)
395 #define PCI_CB_IOLIMIT(x) ((x & PCI_CB_IO_RANGE_MASK) + 3)
396
397 /* Subsystem identification register */
398 #define PCI_SUBSYSTEM_ID_REG 0x2c
399
400 /* User defined cfg space regs */
401 #define PCI_REG_USERCONFIG 0x40
402 #define PCI_OPTION_REG 0x40
403
404 /*
405 * Typedefs, etc...
406 */
407
408 /* Primitive Types */
409 typedef unsigned long ADDRESS; /* Memory/PCI address */
410 typedef unsigned long IOADDRESS; /* Must be large enough for a pointer */
411 typedef unsigned long PCITAG;
412
413 /*
414 * PCI configuration space
415 */
416 typedef struct pci_cfg_regs {
417 /* start of official PCI config space header */
418 union { /* Offset 0x0 - 0x3 */
419 CARD32 device_vendor;
420 struct {
421 #if X_BYTE_ORDER == X_BIG_ENDIAN
422 CARD16 device;
423 CARD16 vendor;
424 #else
425 CARD16 vendor;
426 CARD16 device;
427 #endif
428 } dv;
429 } dv_id;
430
431 union { /* Offset 0x4 - 0x8 */
432 CARD32 status_command;
433 struct {
434 #if X_BYTE_ORDER == X_BIG_ENDIAN
435 CARD16 status;
436 CARD16 command;
437 #else
438 CARD16 command;
439 CARD16 status;
440 #endif
441 } sc;
442 } stat_cmd;
443
444 union { /* Offset 0x8 - 0xb */
445 CARD32 class_revision;
446 struct {
447 #if X_BYTE_ORDER == X_BIG_ENDIAN
448 CARD8 base_class;
449 CARD8 sub_class;
450 CARD8 prog_if;
451 CARD8 rev_id;
452 #else
453 CARD8 rev_id;
454 CARD8 prog_if;
455 CARD8 sub_class;
456 CARD8 base_class;
457 #endif
458 } cr;
459 } class_rev;
460
461 union { /* Offset 0xc - 0xf */
462 CARD32 bist_header_latency_cache;
463 struct {
464 #if X_BYTE_ORDER == X_BIG_ENDIAN
465 CARD8 bist;
466 CARD8 header_type;
467 CARD8 latency_timer;
468 CARD8 cache_line_size;
469 #else
470 CARD8 cache_line_size;
471 CARD8 latency_timer;
472 CARD8 header_type;
473 CARD8 bist;
474 #endif
475 } bhlc;
476 } bhlc;
477 union { /* Offset 0x10 - 0x3b */
478 struct { /* header type 2 */
479 CARD32 cg_rsrvd1; /* 0x10 */
480 #if X_BYTE_ORDER == X_BIG_ENDIAN
481 CARD16 secondary_status; /* 0x16 */
482 CARD16 cg_rsrvd2; /* 0x14 */
483
484 union {
485 CARD32 cg_bus_reg;
486 struct {
487 CARD8 latency_timer; /* 0x1b */
488 CARD8 subordinate_bus_number; /* 0x1a */
489 CARD8 cardbus_bus_number; /* 0x19 */
490 CARD8 primary_bus_number; /* 0x18 */
491 } cgbr;
492 } cgbr;
493 #else
494 CARD16 cg_rsrvd2; /* 0x14 */
495 CARD16 secondary_status; /* 0x16 */
496
497 union {
498 CARD32 cg_bus_reg;
499 struct {
500 CARD8 primary_bus_number; /* 0x18 */
501 CARD8 cardbus_bus_number; /* 0x19 */
502 CARD8 subordinate_bus_number; /* 0x1a */
503 CARD8 latency_timer; /* 0x1b */
504 } cgbr;
505 } cgbr;
506 #endif
507 CARD32 mem_base0; /* 0x1c */
508 CARD32 mem_limit0; /* 0x20 */
509 CARD32 mem_base1; /* 0x24 */
510 CARD32 mem_limit1; /* 0x28 */
511 CARD32 io_base0; /* 0x2c */
512 CARD32 io_limit0; /* 0x30 */
513 CARD32 io_base1; /* 0x34 */
514 CARD32 io_limit1; /* 0x38 */
515 } cg;
516 struct {
517 union { /* Offset 0x10 - 0x27 */
518 struct { /* header type 0 */
519 CARD32 dv_base0;
520 CARD32 dv_base1;
521 CARD32 dv_base2;
522 CARD32 dv_base3;
523 CARD32 dv_base4;
524 CARD32 dv_base5;
525 } dv;
526 struct { /* header type 1 */
527 CARD32 bg_rsrvd[2];
528 #if X_BYTE_ORDER == X_BIG_ENDIAN
529 union {
530 CARD32 pp_bus_reg;
531 struct {
532 CARD8 secondary_latency_timer;
533 CARD8 subordinate_bus_number;
534 CARD8 secondary_bus_number;
535 CARD8 primary_bus_number;
536 } ppbr;
537 } ppbr;
538
539 CARD16 secondary_status;
540 CARD8 io_limit;
541 CARD8 io_base;
542
543 CARD16 mem_limit;
544 CARD16 mem_base;
545
546 CARD16 prefetch_mem_limit;
547 CARD16 prefetch_mem_base;
548 #else
549 union {
550 CARD32 pp_bus_reg;
551 struct {
552 CARD8 primary_bus_number;
553 CARD8 secondary_bus_number;
554 CARD8 subordinate_bus_number;
555 CARD8 secondary_latency_timer;
556 } ppbr;
557 } ppbr;
558
559 CARD8 io_base;
560 CARD8 io_limit;
561 CARD16 secondary_status;
562
563 CARD16 mem_base;
564 CARD16 mem_limit;
565
566 CARD16 prefetch_mem_base;
567 CARD16 prefetch_mem_limit;
568 #endif
569 } bg;
570 } bc;
571 union { /* Offset 0x28 - 0x2b */
572 CARD32 rsvd1;
573 CARD32 pftch_umem_base;
574 CARD32 cardbus_cis_ptr;
575 } um_c_cis;
576 union { /* Offset 0x2c - 0x2f */
577 CARD32 subsys_card_vendor;
578 CARD32 pftch_umem_limit;
579 CARD32 rsvd2;
580 struct {
581 #if X_BYTE_ORDER == X_BIG_ENDIAN
582 CARD16 subsys_card;
583 CARD16 subsys_vendor;
584 #else
585 CARD16 subsys_vendor;
586 CARD16 subsys_card;
587 #endif
588 } ssys;
589 } um_ssys_id;
590 union { /* Offset 0x30 - 0x33 */
591 CARD32 baserom;
592 struct {
593 #if X_BYTE_ORDER == X_BIG_ENDIAN
594 CARD16 io_ulimit;
595 CARD16 io_ubase;
596 #else
597 CARD16 io_ubase;
598 CARD16 io_ulimit;
599 #endif
600 } b_u_io;
601 } uio_rom;
602 struct {
603 CARD32 rsvd3; /* Offset 0x34 - 0x37 */
604 CARD32 rsvd4; /* Offset 0x38 - 0x3b */
605 } rsvd;
606 } cd;
607 } cx;
608 union { /* Offset 0x3c - 0x3f */
609 union { /* header type 0 */
610 CARD32 max_min_ipin_iline;
611 struct {
612 #if X_BYTE_ORDER == X_BIG_ENDIAN
613 CARD8 max_lat;
614 CARD8 min_gnt;
615 CARD8 int_pin;
616 CARD8 int_line;
617 #else
618 CARD8 int_line;
619 CARD8 int_pin;
620 CARD8 min_gnt;
621 CARD8 max_lat;
622 #endif
623 } mmii;
624 } mmii;
625 struct { /* header type 1 */
626 #if X_BYTE_ORDER == X_BIG_ENDIAN
627 CARD16 bridge_control; /* upper 8 bits reserved */
628 CARD8 rsvd2;
629 CARD8 rsvd1;
630 #else
631 CARD8 rsvd1;
632 CARD8 rsvd2;
633 CARD16 bridge_control; /* upper 8 bits reserved */
634 #endif
635 } bctrl;
636 } bm;
637 union { /* Offset 0x40 - 0xff */
638 CARD32 dwords[48];
639 CARD8 bytes[192];
640 } devspf;
641 } pciCfgRegs;
642
643 typedef union pci_cfg_spc {
644 pciCfgRegs regs;
645 CARD32 dwords[256/sizeof(CARD32)];
646 CARD8 bytes[256/sizeof(CARD8)];
647 } pciCfgSpc;
648
649 /*
650 * Data structure returned by xf86scanpci including contents of
651 * PCI config space header
652 */
653 typedef struct pci_device {
654 PCITAG tag;
655 int busnum;
656 int devnum;
657 int funcnum;
658 pciCfgSpc cfgspc;
659 int basesize[7]; /* number of bits in base addr allocations */
660 Bool minBasesize;
661 pointer businfo; /* pointer to secondary's bus info structure */
662 Bool fakeDevice; /* Device added by system chipset support */
663 } pciDevice, *pciConfigPtr;
664
665 typedef enum {
666 PCI_MEM,
667 PCI_MEM_SIZE,
668 PCI_MEM_SPARSE_BASE,
669 PCI_MEM_SPARSE_MASK,
670 PCI_IO,
671 PCI_IO_SIZE,
672 PCI_IO_SPARSE_BASE,
673 PCI_IO_SPARSE_MASK
674 } PciAddrType;
675
676 #define pci_device_vendor cfgspc.regs.dv_id.device_vendor
677 #define pci_vendor cfgspc.regs.dv_id.dv.vendor
678 #define pci_device cfgspc.regs.dv_id.dv.device
679 #define pci_status_command cfgspc.regs.stat_cmd.status_command
680 #define pci_command cfgspc.regs.stat_cmd.sc.command
681 #define pci_status cfgspc.regs.stat_cmd.sc.status
682 #define pci_class_revision cfgspc.regs.class_rev.class_revision
683 #define pci_rev_id cfgspc.regs.class_rev.cr.rev_id
684 #define pci_prog_if cfgspc.regs.class_rev.cr.prog_if
685 #define pci_sub_class cfgspc.regs.class_rev.cr.sub_class
686 #define pci_base_class cfgspc.regs.class_rev.cr.base_class
687 #define pci_bist_header_latency_cache cfgspc.regs.bhlc.bist_header_latency_cache
688 #define pci_cache_line_size cfgspc.regs.bhlc.bhlc.cache_line_size
689 #define pci_latency_timer cfgspc.regs.bhlc.bhlc.latency_timer
690 #define pci_header_type cfgspc.regs.bhlc.bhlc.header_type
691 #define pci_bist cfgspc.regs.bhlc.bhlc.bist
692 #define pci_cb_secondary_status cfgspc.regs.cx.cg.secondary_status
693 #define pci_cb_bus_register cfgspc.regs.cx.cg.cgbr.cg_bus_reg
694 #define pci_cb_primary_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.primary_bus_number
695 #define pci_cb_cardbus_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.cardbus_bus_number
696 #define pci_cb_subordinate_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.subordinate_bus_number
697 #define pci_cb_latency_timer cfgspc.regs.cx.cg.cgbr.cgbr.latency_timer
698 #define pci_cb_membase0 cfgspc.regs.cx.cg.mem_base0
699 #define pci_cb_memlimit0 cfgspc.regs.cx.cg.mem_limit0
700 #define pci_cb_membase1 cfgspc.regs.cx.cg.mem_base1
701 #define pci_cb_memlimit1 cfgspc.regs.cx.cg.mem_limit1
702 #define pci_cb_iobase0 cfgspc.regs.cx.cg.io_base0
703 #define pci_cb_iolimit0 cfgspc.regs.cx.cg.io_limit0
704 #define pci_cb_iobase1 cfgspc.regs.cx.cg.io_base1
705 #define pci_cb_iolimit1 cfgspc.regs.cx.cg.io_limit1
706 #define pci_base0 cfgspc.regs.cx.cd.bc.dv.dv_base0
707 #define pci_base1 cfgspc.regs.cx.cd.bc.dv.dv_base1
708 #define pci_base2 cfgspc.regs.cx.cd.bc.dv.dv_base2
709 #define pci_base3 cfgspc.regs.cx.cd.bc.dv.dv_base3
710 #define pci_base4 cfgspc.regs.cx.cd.bc.dv.dv_base4
711 #define pci_base5 cfgspc.regs.cx.cd.bc.dv.dv_base5
712 #define pci_cardbus_cis_ptr cfgspc.regs.cx.cd.umem_c_cis.cardbus_cis_ptr
713 #define pci_subsys_card_vendor cfgspc.regs.cx.cd.um_ssys_id.subsys_card_vendor
714 #define pci_subsys_vendor cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_vendor
715 #define pci_subsys_card cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_card
716 #define pci_baserom cfgspc.regs.cx.cd.uio_rom.baserom
717 #define pci_pp_bus_register cfgspc.regs.cx.cd.bc.bg.ppbr.pp_bus_reg
718 #define pci_primary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.primary_bus_number
719 #define pci_secondary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_bus_number
720 #define pci_subordinate_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.subordinate_bus_number
721 #define pci_secondary_latency_timer cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_latency_timer
722 #define pci_io_base cfgspc.regs.cx.cd.bc.bg.io_base
723 #define pci_io_limit cfgspc.regs.cx.cd.bc.bg.io_limit
724 #define pci_secondary_status cfgspc.regs.cx.cd.bc.bg.secondary_status
725 #define pci_mem_base cfgspc.regs.cx.cd.bc.bg.mem_base
726 #define pci_mem_limit cfgspc.regs.cx.cd.bc.bg.mem_limit
727 #define pci_prefetch_mem_base cfgspc.regs.cx.cd.bc.bg.prefetch_mem_base
728 #define pci_prefetch_mem_limit cfgspc.regs.cx.cd.bc.bg.prefetch_mem_limit
729 #define pci_rsvd1 cfgspc.regs.cx.cd.um_c_cis.rsvd1
730 #define pci_rsvd2 cfgspc.regs.cx.cd.um_ssys_id.rsvd2
731 #define pci_prefetch_upper_mem_base cfgspc.regs.cx.cd.um_c_cis.pftch_umem_base
732 #define pci_prefetch_upper_mem_limit cfgspc.regs.cx.cd.um_ssys_id.pftch_umem_limit
733 #define pci_upper_io_base cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ubase
734 #define pci_upper_io_limit cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ulimit
735 #define pci_int_line cfgspc.regs.bm.mmii.mmii.int_line
736 #define pci_int_pin cfgspc.regs.bm.mmii.mmii.int_pin
737 #define pci_min_gnt cfgspc.regs.bm.mmii.mmii.min_gnt
738 #define pci_max_lat cfgspc.regs.bm.mmii.mmii.max_lat
739 #define pci_max_min_ipin_iline cfgspc.regs.bm.mmii.max_min_ipin_iline
740 #define pci_bridge_control cfgspc.regs.bm.bctrl.bridge_control
741 #define pci_user_config cfgspc.regs.devspf.dwords[0]
742 #define pci_user_config_0 cfgspc.regs.devspf.bytes[0]
743 #define pci_user_config_1 cfgspc.regs.devspf.bytes[1]
744 #define pci_user_config_2 cfgspc.regs.devspf.bytes[2]
745 #define pci_user_config_3 cfgspc.regs.devspf.bytes[3]
746
747 typedef enum {
748 PCI_BIOS_PC = 0,
749 PCI_BIOS_OPEN_FIRMWARE,
750 PCI_BIOS_HP_PA_RISC,
751 PCI_BIOS_OTHER
752 } PciBiosType;
753
754 /* Public PCI access functions */
755 void pciInit(void);
756 PCITAG pciFindFirst(CARD32 id, CARD32 mask);
757 PCITAG pciFindNext(void);
758 CARD32 pciReadLong(PCITAG tag, int offset);
759 CARD16 pciReadWord(PCITAG tag, int offset);
760 CARD8 pciReadByte(PCITAG tag, int offset);
761 void pciWriteLong(PCITAG tag, int offset, CARD32 val);
762 void pciWriteWord(PCITAG tag, int offset, CARD16 val);
763 void pciWriteByte(PCITAG tag, int offset, CARD8 val);
764 void pciSetBitsLong(PCITAG tag, int offset, CARD32 mask, CARD32 val);
765 void pciSetBitsByte(PCITAG tag, int offset, CARD8 mask, CARD8 val);
766 ADDRESS pciBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr);
767 ADDRESS pciHostAddrToBusAddr(PCITAG tag, PciAddrType type, ADDRESS addr);
768 PCITAG pciTag(int busnum, int devnum, int funcnum);
769 PCITAG pciDomTag(int domnum, int busnum, int devnum, int funcnum);
770 int pciGetBaseSize(PCITAG tag, int indx, Bool destructive, Bool *min);
771 CARD32 pciCheckForBrokenBase(PCITAG tag,int basereg);
772 pointer xf86MapPciMem(int ScreenNum, int Flags, PCITAG Tag,
773 ADDRESS Base, unsigned long Size);
774 int xf86ReadPciBIOS(unsigned long Offset, PCITAG Tag, int basereg,
775 unsigned char *Buf, int Len);
776 pciConfigPtr *xf86scanpci(int flags);
777 pciConfigPtr xf86GetPciConfigFromTag(PCITAG Tag);
778
779 extern int pciNumBuses;
780
781 /* Domain access functions. Some of these probably shouldn't be public */
782 int xf86GetPciDomain(PCITAG tag);
783 pointer xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag,
784 ADDRESS Base, unsigned long Size);
785 IOADDRESS xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag,
786 IOADDRESS Base, unsigned long Size);
787 int xf86ReadDomainMemory(PCITAG Tag, ADDRESS Base, int Len,
788 unsigned char *Buf);
789
790 typedef enum {
791 ROM_BASE_PRESET = -2,
792 ROM_BASE_BIOS,
793 ROM_BASE_MEM0 = 0,
794 ROM_BASE_MEM1,
795 ROM_BASE_MEM2,
796 ROM_BASE_MEM3,
797 ROM_BASE_MEM4,
798 ROM_BASE_MEM5,
799 ROM_BASE_FIND
800 } romBaseSource;
801
802 #endif /* _XF86PCI_H */
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