xorg-server-1.4/hw/xfree86/os-support/misc/BUSmemcpy.c

   1
   2 /****************************************************************************
   3
   4  For Alpha Linux, BusToMem() and MemToBus() can be simply memcpy(), BUT:
   5   we need to prevent unaligned operations when accessing DENSE space on the BUS,
   6   as the video memory is mmap'd that way. The below code does this.
   7
   8 NOTE: we could simply use the "memcpy()" from LIBC here, but that, currently, is
   9       not as fast.
  10
  11 Thanks to Linus Torvalds for contributing this code.
  12
  13 ****************************************************************************/
  14
  15
  16 #ifdef HAVE_XORG_CONFIG_H
  17 #include <xorg-config.h>
  18 #endif
  19
  20 #include <X11/X.h>
  21 #include "xf86.h"
  22 #include "xf86Priv.h"
  23 #include "xf86_OSlib.h"
  24
  25 #ifdef __alpha__
  26
  27 #include "compiler.h"
  28
  29 /*
  30  * The Jensen lacks dense memory, thus we have to address the bus via
  31  * the sparse addressing scheme. These routines are only used in s3im.c
  32  * Non time critical code uses SlowBCopy_{from/to} bus.
  33  *
  34  * Martin Ostermann (ost@comnets.rwth-aachen.de) - Apr.-Sep. 1996
  35  */
  36
  37 #ifdef TEST_JENSEN_CODE /* define to test the Sparse addressing on a non-Jensen */
  38 #define LWORD_CODING (0x18)
  39 #define SPARSE (5)
  40 #else
  41 #define LWORD_CODING (0x60)
  42 #define SPARSE (7)
  43 #endif
  44
  45 void
  46 xf86JensenMemToBus(char *Base, long dst, long src, int count)
  47 {
  48     if( ((long)src^((long)dst)) & 3) {
  49                                /* src & dst are NOT aligned to each other */
  50         unsigned long addr;
  51         unsigned long low_word, high_word,last_read;
  52         long  rm,loop;
  53         unsigned long tmp,org,org2,mask,src_org,count_org;
  54
  55         src_org=src;
  56         count_org=count;
  57
  58         /* add EISA longword coding and round off*/
  59         addr = (long)(Base+(dst<<SPARSE) + LWORD_CODING) & ~(3<<SPARSE);
  60         rm = (long)dst & 3;
  61         count += rm;
  62
  63         count = count_org + rm;
  64         org = *(volatile unsigned int *)addr;
  65         __asm__("ldq_u %0,%1"
  66                 :"=r" (low_word):"m" (*(unsigned long *)(src_org)));
  67         src = src_org - rm;
  68         if( count > 4  ) {
  69             last_read = src_org+count_org - 1;
  70             __asm__("ldq_u %0,%1"
  71                     :"=r" (high_word):"m" (*(unsigned long *)(src+4)));
  72             __asm__("extll %1,%2,%0"
  73                     :"=r" (low_word)
  74                     :"r" (low_word), "r" ((unsigned long)(src)));
  75             __asm__("extlh %1,%2,%0"
  76                     :"=r" (tmp)
  77                     :"r" (high_word), "r" ((unsigned long)(src)));
  78             tmp |= low_word;
  79             src += 4;
  80             __asm__("mskqh %1,%2,%0"
  81                     :"=r" (tmp)
  82                     :"r" (tmp), "r" (rm));
  83             __asm__("mskql %1,%2,%0"
  84                     :"=r" (org2)
  85                     :"r" (org), "r" (rm));
  86             tmp |= org2;
  87
  88             loop = (count-4) >> 2; /* loop eqv. count>=4 ; count -= 4 */
  89             while (loop) {
  90                      /* tmp to be stored completly -- need to read next word*/
  91                 low_word = high_word;
  92                 *(volatile unsigned int *) (addr) = tmp;
  93                 __asm__("ldq_u %0,%1"
  94                         :"=r" (high_word):"m" (*(unsigned long*)(src+4)));
  95                 loop --;
  96                 __asm__("extll %1,%2,%0"
  97                         :"=r" (low_word)
  98                         :"r" (low_word), "r" ((unsigned long)src));
  99                 __asm__("extlh %1,%2,%0"
 100                         :"=r" (tmp)
 101                         :"r" (high_word), "r" ((unsigned long)src));
 102                 src += 4;
 103                 tmp |= low_word;
 104                 addr += 4<<SPARSE;
 105             }
 106             if ( count & 3 ) {
 107                      /* Store tmp completly, and possibly read one more word.*/
 108                 *(volatile unsigned int *) (addr) = tmp;
 109                 __asm__("ldq_u %0,%1"
 110                         :"=r" (tmp):"m" (*((unsigned long *)(last_read)) ));
 111                 addr += 4<<SPARSE;
 112                 __asm__("extll %1,%2,%0"
 113                         :"=r" (low_word)
 114                         :"r" (high_word), "r" ((unsigned long)src));
 115                 __asm__("extlh %1,%2,%0"
 116                         :"=r" (tmp)
 117                         :"r" (tmp), "r" ((unsigned long)src));
 118                 tmp |= low_word;
 119                 org = *(volatile unsigned int *)addr;
 120
 121                 __asm__("mskql %1,%2,%0"
 122                         :"=r" (tmp)
 123                         :"r" (tmp), "r" (count&3));
 124                 __asm__("mskqh %1,%2,%0"
 125                         :"=r" (org)
 126                         :"r" (org), "r" (count&3));
 127
 128                 tmp |= org;
 129             }
 130             *(volatile unsigned int *) (addr) = tmp;
 131             return;
 132         } else {         /* count > 4  */
 133             __asm__("ldq_u %0,%1"
 134                     :"=r" (high_word):"m" (*(unsigned long *)(src+4)));
 135             __asm__("extll %1,%2,%0"
 136                     :"=r" (low_word)
 137                     :"r" (low_word), "r" ((unsigned long)(src)));
 138             __asm__("extlh %1,%2,%0"
 139                     :"=r" (tmp)
 140                     :"r" (high_word), "r" ((unsigned long)(src)));
 141             tmp |= low_word;
 142             if( count < 4 ) {
 143
 144                 mask = -1;
 145                 __asm__("mskqh %1,%2,%0"
 146                         :"=r" (mask)
 147                         :"r" (mask), "r" (rm));
 148                 __asm__("mskql %1,%2,%0"
 149                         :"=r" (mask)
 150                         :"r" (mask), "r" (count));
 151                 tmp = (tmp & mask) | (org & ~mask);
 152                 *(volatile unsigned int *) (addr) = tmp;
 153                 return;
 154             }  else {
 155                 __asm__("mskqh %1,%2,%0"
 156                         :"=r" (tmp)
 157                         :"r" (tmp), "r" (rm));
 158                 __asm__("mskql %1,%2,%0"
 159                         :"=r" (org2)
 160                         :"r" (org), "r" (rm));
 161
 162                 tmp |= org2;
 163                 *(volatile unsigned int *) (addr) = tmp;
 164                 return;
 165             }
 166         }
 167     } else {          /* src & dst are aligned to each other */
 168         unsigned long addr;
 169         unsigned int tmp,org,rm;
 170         unsigned int *src_r;
 171
 172         /* add EISA longword coding and round off*/
 173         addr = (long)(Base+(dst<<SPARSE) + LWORD_CODING) & ~(3<<SPARSE);
 174
 175         src_r = (unsigned int*)((long)src & ~3L);
 176         rm=(long)src & 3;
 177         count += rm;
 178
 179         tmp = *src_r;
 180         org = *(volatile unsigned int *)addr;
 181
 182         __asm__("mskqh %1,%2,%0"
 183                 :"=r" (tmp)
 184                 :"r" (tmp), "r" (rm));
 185         __asm__("mskql %1,%2,%0"
 186                 :"=r" (org)
 187                 :"r" (org), "r" (rm));
 188
 189         tmp |= org;
 190
 191         while (count > 4) {
 192             *(volatile unsigned int *) addr = tmp;
 193             addr += 4<<SPARSE;
 194             src_r += 1;
 195             tmp = *src_r;
 196             count -= 4;
 197         }
 198
 199         org = *(volatile unsigned int *)addr;
 200         __asm__("mskql %1,%2,%0"
 201                 :"=r" (tmp)
 202                 :"r" (tmp), "r" (count));
 203         __asm__("mskqh %1,%2,%0"
 204                 :"=r" (org)
 205                 :"r" (org), "r" (count));
 206         tmp |= org;
 207         *(volatile unsigned int *) (addr) = tmp;
 208     }
 209 }
 210
 211 void
 212 xf86JensenBusToMem(char *Base, char *dst, unsigned long src, int count)
 213 {
 214 #if 0
 215   /* Optimization of BusToMem() is left as an exercise to the reader ;-)
 216    * Consider that ldq_u/extlh/extll won't work because of the bus being
 217    * only 4 bytes wide!
 218    */
 219 #else
 220   unsigned long addr;
 221   long result;
 222
 223   addr = (unsigned long)(Base+(src<<SPARSE)) ;
 224   while( addr & (3<<SPARSE) ){
 225     if(count <= 0) return;
 226     result = *(volatile int *) addr;
 227     result >>= ((addr>>SPARSE) & 3) * 8;
 228     *dst++ = (char) result;
 229     addr += 1<<SPARSE;
 230     count--;
 231   }
 232   count -=4;
 233   while(count >= 0){
 234     int i;
 235
 236     result = *(volatile int *) (addr+LWORD_CODING);
 237     for(i=4;i--;) {
 238       *dst++ = (char) result;
 239       result >>= 8;
 240     }
 241     addr += 4<<SPARSE;
 242     count -= 4;
 243   }
 244   count +=4;
 245
 246   while( count ){
 247     result = *(volatile int *) addr;
 248     result >>= ((addr>>SPARSE) & 3) * 8;
 249     *dst++ = (char) result;
 250     addr += 1<<SPARSE;
 251     count--;
 252   }
 253 #endif
 254 }
 255
 256
 257 static unsigned long __memcpy(unsigned long dest, unsigned long src, int n);
 258
 259 _X_EXPORT void
 260 xf86BusToMem(unsigned char *dst, unsigned char *src, int len)
 261 {
 262         __memcpy((unsigned long)dst, (unsigned long)src, len);
 263 }
 264 _X_EXPORT void
 265 xf86MemToBus(unsigned char *dst, unsigned char *src, int len)
 266 {
 267   if (len == sizeof(int))
 268     if (!(((long)src | (long)dst) & 3))
 269       *((unsigned int*)dst) = *((unsigned int*)(src));
 270     else {
 271       int i;
 272       if (((long)src) & 3)
 273         i = ldl_u((unsigned int*)src);
 274       else
 275         i = *(unsigned int*)src;
 276       if (((long)dst) & 3)
 277         stl_u(i,(unsigned int*)dst);
 278       else
 279         *(unsigned int*)dst = i;
 280     }
 281   else
 282     __memcpy((unsigned long)dst, (unsigned long)src, len);
 283 }
 284
 285 /*
 286  *  linux/arch/alpha/lib/memcpy.c
 287  *
 288  *  Copyright (C) 1995  Linus Torvalds, used with his permission.
 289  */
 290
 291 /*
 292  * This is a reasonably optimized memcpy() routine.
 293  */
 294
 295 /*
 296  * Note that the C code is written to be optimized into good assembly. However,
 297  * at this point gcc is unable to sanely compile "if (n >= 0)", resulting in a
 298  * explicit compare against 0 (instead of just using the proper "blt reg, xx" or
 299  * "bge reg, xx"). I hope alpha-gcc will be fixed to notice this eventually..
 300  */
 301
 302 /*
 303  * This should be done in one go with ldq_u*2/mask/stq_u. Do it
 304  * with a macro so that we can fix it up later..
 305  */
 306 #define ALIGN_DEST_TO8(d,s,n) \
 307         while (d & 7) { \
 308                 if (n <= 0) return; \
 309                 n--; \
 310                 *(char *) d = *(char *) s; \
 311                 d++; s++; \
 312         }
 313
 314 /*
 315  * This should similarly be done with ldq_u*2/mask/stq. The destination
 316  * is aligned, but we don't fill in a full quad-word
 317  */
 318 #define DO_REST(d,s,n) \
 319         while (n > 0) { \
 320                 n--; \
 321                 *(char *) d = *(char *) s; \
 322                 d++; s++; \
 323         }
 324
 325 /*
 326  * This should be done with ldq/mask/stq. The source and destination are
 327  * aligned, but we don't fill in a full quad-word
 328  */
 329 #define DO_REST_ALIGNED(d,s,n) DO_REST(d,s,n)
 330
 331 /*
 332  * This does unaligned memory copies. We want to avoid storing to
 333  * an unaligned address, as that would do a read-modify-write cycle.
 334  * We also want to avoid double-reading the unaligned reads.
 335  *
 336  * Note the ordering to try to avoid load (and address generation) latencies.
 337  */
 338 static __inline__ void __memcpy_unaligned(unsigned long d, unsigned long s, long n)
 339 {
 340         ALIGN_DEST_TO8(d,s,n);
 341         n -= 8;                 /* to avoid compare against 8 in the loop */
 342         if (n >= 0) {
 343                 unsigned long low_word, high_word;
 344                 __asm__("ldq_u %0,%1":"=r" (low_word):"m" (*(unsigned long *) s));
 345                 do {
 346                         unsigned long tmp;
 347                         __asm__("ldq_u %0,%1":"=r" (high_word):"m" (*(unsigned long *)(s+8)));
 348                         n -= 8;
 349                         __asm__("extql %1,%2,%0"
 350                                 :"=r" (low_word)
 351                                 :"r" (low_word), "r" (s));
 352                         __asm__("extqh %1,%2,%0"
 353                                 :"=r" (tmp)
 354                                 :"r" (high_word), "r" (s));
 355                         s += 8;
 356                         *(unsigned long *) d = low_word | tmp;
 357                         d += 8;
 358                         low_word = high_word;
 359                 } while (n >= 0);
 360         }
 361         n += 8;
 362         DO_REST(d,s,n);
 363 }
 364
 365 /*
 366  * Hmm.. Strange. The __asm__ here is there to make gcc use a integer register
 367  * for the load-store. I don't know why, but it would seem that using a floating
 368  * point register for the move seems to slow things down (very small difference,
 369  * though).
 370  *
 371  * Note the ordering to try to avoid load (and address generation) latencies.
 372  */
 373 static __inline__ void __memcpy_aligned(unsigned long d, unsigned long s, long n)
 374 {
 375         ALIGN_DEST_TO8(d,s,n);
 376         n -= 8;
 377         while (n >= 0) {
 378                 unsigned long tmp;
 379                 __asm__("ldq %0,%1":"=r" (tmp):"m" (*(unsigned long *) s));
 380                 n -= 8;
 381                 s += 8;
 382                 *(unsigned long *) d = tmp;
 383                 d += 8;
 384         }
 385         n += 8;
 386         DO_REST_ALIGNED(d,s,n);
 387 }
 388
 389 static unsigned long __memcpy(unsigned long dest, unsigned long src, int n)
 390 {
 391         if (!((dest ^ src) & 7)) {
 392                 __memcpy_aligned(dest, src, n);
 393                 return dest;
 394         }
 395         __memcpy_unaligned(dest, src, n);
 396         return dest;
 397 }
 398
 399 #else /* __alpha__ */
 400
 401 void
 402 xf86BusToMem(unsigned char *dst, unsigned char *src, int len)
 403 {
 404         memcpy(dst, src, len);
 405 }
 406 void
 407 xf86MemToBus(unsigned char *dst, unsigned char *src, int len)
 408 {
 409         memcpy(dst, src, len);
 410 }
 411
 412 #endif /* __alpha__ */