mmu.h

   1 // This file contains definitions for the
   2 // x86 memory management unit (MMU).
   3
   4 // Eflags register
   5 #define FL_CF           0x00000001      // Carry Flag
   6 #define FL_PF           0x00000004      // Parity Flag
   7 #define FL_AF           0x00000010      // Auxiliary carry Flag
   8 #define FL_ZF           0x00000040      // Zero Flag
   9 #define FL_SF           0x00000080      // Sign Flag
  10 #define FL_TF           0x00000100      // Trap Flag
  11 #define FL_IF           0x00000200      // Interrupt Enable
  12 #define FL_DF           0x00000400      // Direction Flag
  13 #define FL_OF           0x00000800      // Overflow Flag
  14 #define FL_IOPL_MASK    0x00003000      // I/O Privilege Level bitmask
  15 #define FL_IOPL_0       0x00000000      //   IOPL == 0
  16 #define FL_IOPL_1       0x00001000      //   IOPL == 1
  17 #define FL_IOPL_2       0x00002000      //   IOPL == 2
  18 #define FL_IOPL_3       0x00003000      //   IOPL == 3
  19 #define FL_NT           0x00004000      // Nested Task
  20 #define FL_RF           0x00010000      // Resume Flag
  21 #define FL_VM           0x00020000      // Virtual 8086 mode
  22 #define FL_AC           0x00040000      // Alignment Check
  23 #define FL_VIF          0x00080000      // Virtual Interrupt Flag
  24 #define FL_VIP          0x00100000      // Virtual Interrupt Pending
  25 #define FL_ID           0x00200000      // ID flag
  26
  27 // Control Register flags
  28 #define CR0_PE          0x00000001      // Protection Enable
  29 #define CR0_MP          0x00000002      // Monitor coProcessor
  30 #define CR0_EM          0x00000004      // Emulation
  31 #define CR0_TS          0x00000008      // Task Switched
  32 #define CR0_ET          0x00000010      // Extension Type
  33 #define CR0_NE          0x00000020      // Numeric Errror
  34 #define CR0_WP          0x00010000      // Write Protect
  35 #define CR0_AM          0x00040000      // Alignment Mask
  36 #define CR0_NW          0x20000000      // Not Writethrough
  37 #define CR0_CD          0x40000000      // Cache Disable
  38 #define CR0_PG          0x80000000      // Paging
  39
  40 // Segment Descriptor
  41 struct segdesc {
  42   uint lim_15_0 : 16;  // Low bits of segment limit
  43   uint base_15_0 : 16; // Low bits of segment base address
  44   uint base_23_16 : 8; // Middle bits of segment base address
  45   uint type : 4;       // Segment type (see STS_ constants)
  46   uint s : 1;          // 0 = system, 1 = application
  47   uint dpl : 2;        // Descriptor Privilege Level
  48   uint p : 1;          // Present
  49   uint lim_19_16 : 4;  // High bits of segment limit
  50   uint avl : 1;        // Unused (available for software use)
  51   uint rsv1 : 1;       // Reserved
  52   uint db : 1;         // 0 = 16-bit segment, 1 = 32-bit segment
  53   uint g : 1;          // Granularity: limit scaled by 4K when set
  54   uint base_31_24 : 8; // High bits of segment base address
  55 };
  56
  57 // Normal segment
  58 #define SEG(type, base, lim, dpl) (struct segdesc)    \
  59 { ((lim) >> 12) & 0xffff, (uint)(base) & 0xffff,      \
  60   ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1,       \
  61   (uint)(lim) >> 28, 0, 0, 1, 1, (uint)(base) >> 24 }
  62 #define SEG16(type, base, lim, dpl) (struct segdesc)  \
  63 { (lim) & 0xffff, (uint)(base) & 0xffff,              \
  64   ((uint)(base) >> 16) & 0xff, type, 1, dpl, 1,       \
  65   (uint)(lim) >> 16, 0, 0, 1, 0, (uint)(base) >> 24 }
  66
  67 #define DPL_USER    0x3     // User DPL
  68
  69 // Application segment type bits
  70 #define STA_X       0x8     // Executable segment
  71 #define STA_E       0x4     // Expand down (non-executable segments)
  72 #define STA_C       0x4     // Conforming code segment (executable only)
  73 #define STA_W       0x2     // Writeable (non-executable segments)
  74 #define STA_R       0x2     // Readable (executable segments)
  75 #define STA_A       0x1     // Accessed
  76
  77 // System segment type bits
  78 #define STS_T16A    0x1     // Available 16-bit TSS
  79 #define STS_LDT     0x2     // Local Descriptor Table
  80 #define STS_T16B    0x3     // Busy 16-bit TSS
  81 #define STS_CG16    0x4     // 16-bit Call Gate
  82 #define STS_TG      0x5     // Task Gate / Coum Transmitions
  83 #define STS_IG16    0x6     // 16-bit Interrupt Gate
  84 #define STS_TG16    0x7     // 16-bit Trap Gate
  85 #define STS_T32A    0x9     // Available 32-bit TSS
  86 #define STS_T32B    0xB     // Busy 32-bit TSS
  87 #define STS_CG32    0xC     // 32-bit Call Gate
  88 #define STS_IG32    0xE     // 32-bit Interrupt Gate
  89 #define STS_TG32    0xF     // 32-bit Trap Gate
  90
  91 // A linear address 'la' has a three-part structure as follows:
  92 //
  93 // +--------10------+-------10-------+---------12----------+
  94 // | Page Directory |   Page Table   | Offset within Page  |
  95 // |      Index     |      Index     |                     |
  96 // +----------------+----------------+---------------------+
  97 //  \--- PDX(la) --/ \--- PTX(la) --/
  98
  99 // page directory index
 100 #define PDX(la)         (((uint)(la) >> PDXSHIFT) & 0x3FF)
 101
 102 // page table index
 103 #define PTX(la)         (((uint)(la) >> PTXSHIFT) & 0x3FF)
 104
 105 // construct linear address from indexes and offset
 106 #define PGADDR(d, t, o) ((uint)((d) << PDXSHIFT | (t) << PTXSHIFT | (o)))
 107
 108 // turn a kernel linear address into a physical address.
 109 // all of the kernel data structures have linear and
 110 // physical addresses that are equal.
 111 #define PADDR(a)       ((uint)(a))
 112
 113 // Page directory and page table constants.
 114 #define NPDENTRIES      1024            // page directory entries per page directory
 115 #define NPTENTRIES      1024            // page table entries per page table
 116
 117 #define PGSIZE          4096            // bytes mapped by a page
 118 #define PGSHIFT         12              // log2(PGSIZE)
 119
 120 #define PTXSHIFT        12              // offset of PTX in a linear address
 121 #define PDXSHIFT        22              // offset of PDX in a linear address
 122
 123 #define PGROUNDUP(sz)  (((sz)+PGSIZE-1) & ~(PGSIZE-1))
 124 #define PGROUNDDOWN(a) ((char*)((((unsigned int)(a)) & ~(PGSIZE-1))))
 125
 126 // Page table/directory entry flags.
 127 #define PTE_P           0x001   // Present
 128 #define PTE_W           0x002   // Writeable
 129 #define PTE_U           0x004   // User
 130 #define PTE_PWT         0x008   // Write-Through
 131 #define PTE_PCD         0x010   // Cache-Disable
 132 #define PTE_A           0x020   // Accessed
 133 #define PTE_D           0x040   // Dirty
 134 #define PTE_PS          0x080   // Page Size
 135 #define PTE_MBZ         0x180   // Bits must be zero
 136
 137 // Address in page table or page directory entry
 138 #define PTE_ADDR(pte)   ((uint)(pte) & ~0xFFF)
 139
 140 typedef uint pte_t;
 141
 142 // Task state segment format
 143 struct taskstate {
 144   uint link;         // Old ts selector
 145   uint esp0;         // Stack pointers and segment selectors
 146   ushort ss0;        //   after an increase in privilege level
 147   ushort padding1;
 148   uint *esp1;
 149   ushort ss1;
 150   ushort padding2;
 151   uint *esp2;
 152   ushort ss2;
 153   ushort padding3;
 154   void *cr3;         // Page directory base
 155   uint *eip;         // Saved state from last task switch
 156   uint eflags;
 157   uint eax;          // More saved state (registers)
 158   uint ecx;
 159   uint edx;
 160   uint ebx;
 161   uint *esp;
 162   uint *ebp;
 163   uint esi;
 164   uint edi;
 165   ushort es;         // Even more saved state (segment selectors)
 166   ushort padding4;
 167   ushort cs;
 168   ushort padding5;
 169   ushort ss;
 170   ushort padding6;
 171   ushort ds;
 172   ushort padding7;
 173   ushort fs;
 174   ushort padding8;
 175   ushort gs;
 176   ushort padding9;
 177   ushort ldt;
 178   ushort padding10;
 179   ushort t;          // Trap on task switch
 180   ushort iomb;       // I/O map base address
 181 };
 182
 183 // Gate descriptors for interrupts and traps
 184 struct gatedesc {
 185   uint off_15_0 : 16;   // low 16 bits of offset in segment
 186   uint cs : 16;         // code segment selector
 187   uint args : 5;        // # args, 0 for interrupt/trap gates
 188   uint rsv1 : 3;        // reserved(should be zero I guess)
 189   uint type : 4;        // type(STS_{TG,IG32,TG32})
 190   uint s : 1;           // must be 0 (system)
 191   uint dpl : 2;         // descriptor(meaning new) privilege level
 192   uint p : 1;           // Present
 193   uint off_31_16 : 16;  // high bits of offset in segment
 194 };
 195
 196 // Set up a normal interrupt/trap gate descriptor.
 197 // - istrap: 1 for a trap (= exception) gate, 0 for an interrupt gate.
 198 //   interrupt gate clears FL_IF, trap gate leaves FL_IF alone
 199 // - sel: Code segment selector for interrupt/trap handler
 200 // - off: Offset in code segment for interrupt/trap handler
 201 // - dpl: Descriptor Privilege Level -
 202 //        the privilege level required for software to invoke
 203 //        this interrupt/trap gate explicitly using an int instruction.
 204 #define SETGATE(gate, istrap, sel, off, d)                \
 205 {                                                         \
 206   (gate).off_15_0 = (uint)(off) & 0xffff;                \
 207   (gate).cs = (sel);                                      \
 208   (gate).args = 0;                                        \
 209   (gate).rsv1 = 0;                                        \
 210   (gate).type = (istrap) ? STS_TG32 : STS_IG32;           \
 211   (gate).s = 0;                                           \
 212   (gate).dpl = (d);                                       \
 213   (gate).p = 1;                                           \
 214   (gate).off_31_16 = (uint)(off) >> 16;                  \
 215 }
 216