Icarus/Makefile

   1 # -----------------------------------------------------------------------
   2 #
   3 #   Copyright 2004,2007,2010 Tommy Thorn - All Rights Reserved
   4 #
   5 #   This program is free software; you can redistribute it and/or modify
   6 #   it under the terms of the GNU General Public License as published by
   7 #   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
   8 #   Bostom MA 02111-1307, USA; either version 2 of the License, or
   9 #   (at your option) any later version; incorporated herein by reference.
  10 #
  11 # -----------------------------------------------------------------------
  12
  13 TOPDIR=..
  14 include default.conf
  15 include ../shared/shared.mk
  16
  17 YARISRC:=yari.v stage_I.v stage_D.v stage_X.v stage_M.v
  18
  19 SYSTEMSRC:=pipeconnect.v  \
  20     bus_ctrl.v sram_ctrl.v \
  21     hexled.v \
  22     vga.v blockram.v \
  23     peri_ctrl.v rs232.v rs232out.v rs232in.v
  24
  25 PRIMSRC:=simpledpram.v dpram.v
  26
  27 # Target logic that we model
  28 TARGETSRC:=\
  29     toplevel.v \
  30     pll.v altsyncram.v \
  31     arithshiftbidir.v logshiftright.v
  32
  33 # Change IDT_SRAM_MODEL to point to the IDT SRAM model if one is available
  34 IDT_SRAM_MODEL=
  35
  36 SRC:=$(patsubst %,../../shared/rtl/yari-core/%,$(YARISRC)) \
  37      $(patsubst %,../../shared/rtl/soclib/%,$(SYSTEMSRC)) \
  38      $(PRIMSRC) \
  39      $(TARGETSRC) \
  40      $(IDT_SRAM_MODEL)
  41
  42 IVERILOGOPTS=-Wall -g2005 -I../../shared/rtl/soclib -I../../shared/rtl/yari-core
  43
  44 all: simulate
  45
  46 simulate: $(patsubst %,rtl/%,$(SRC)) rtl/config.h Makefile rtl/icache_ram0.data
  47         cd rtl; iverilog -o main.test \
  48                 $(IVERILOGOPTS) \
  49                 -DSIMULATE_MAIN -DTRACE_SERIAL -DSRAM_INIT=$(SRAM_INIT) $(SRC)
  50         cd rtl; ./main.test
  51
  52 rtl/icache_ram0.data: tinymon.mips $(YARISIM)
  53         cd rtl; ../$(YARISIM)                         \
  54                 --data                                \
  55                 --icache-way=$(IC_LINE_INDEX_BITS)    \
  56                 --icache-words=$(IC_WORD_INDEX_BITS)  \
  57                 --dcache-way=$(DC_LINE_INDEX_BITS)    \
  58                 --dcache-words=$(DC_WORD_INDEX_BITS)  \
  59                 ../tinymon.mips
  60
  61 mult:
  62         iverilog mult.v -o mult.test
  63         ./mult.test
  64
  65 testpipe: ../shared/rtl/soclib/pipeconnect.v
  66         iverilog -I .. ../shared/rtl/soclib/pipeconnect.v testpipe.v -o testpipe.test
  67         ./testpipe.test
  68
  69 testpipe2: ../shared/rtl/soclib/pipeconnect.v
  70         iverilog -I .. ../shared/rtl/soclib/pipeconnect.v testpipe2.v -o testpipe2.test
  71         ./testpipe2.test
  72
  73 testpipe3: ../shared/rtl/soclib/pipeconnect.v
  74         iverilog -I .. ../shared/rtl/soclib/pipeconnect.v testpipe3.v -o testpipe3.test
  75         ./testpipe3.test
  76
  77
  78 stage_I.test: ../shared/rtl/yari-core/stage_I.v coderom.v
  79         iverilog -DSIMULATE ../shared/rtl/yari-core/stage_I.v coderom.v -o stage_I.test
  80         ./stage_I.test
  81
  82 stage_D.test: stage_D.v coderom.v
  83         iverilog -DSIMULATE stage_D.v coderom.v -o stage_D.test
  84         ./stage_D.test
  85
  86 test1: pipeline1
  87         cp ../shared/rtl/../testcases/tests.data initmem.data
  88         ./pipeline1
  89
  90 rs232out: rs232out.v
  91         iverilog -DSIMULATE rs232out.v -o rs232out
  92         ./rs232out
  93
  94 pipeline1: pipeline1.v
  95         iverilog pipeline1.v -o pipeline1
  96
  97 clean:
  98         -rm main.test
  99
 100 realclean: clean
 101         -rm *~ *.data *.txt a.out
 102
 103 tinymon.mips-o: tinymon.c
 104         mips-elf-gcc -D_mips_ -msoft-float -c -Os $< -o $@
 105
 106 tinymon.mips: tinymon.mips-o
 107         mips-elf-ld -Tprom.ld $< -o $@