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spi-topcliff-pch: Fix issue for transmitting over 4KByte
[zen-stable.git] / arch / alpha / include / asm / core_mcpcia.h
blob9f67a056b46181e36753575698ea40d6944e6fd2
1 #ifndef __ALPHA_MCPCIA__H__
2 #define __ALPHA_MCPCIA__H__
3
4 /* Define to experiment with fitting everything into one 128MB HAE window.
5 One window per bus, that is. */
6 #define MCPCIA_ONE_HAE_WINDOW 1
7
8 #include <linux/types.h>
9 #include <asm/compiler.h>
10
11 /*
12 * MCPCIA is the internal name for a core logic chipset which provides
13 * PCI access for the RAWHIDE family of systems.
14 *
15 * This file is based on:
16 *
17 * RAWHIDE System Programmer's Manual
18 * 16-May-96
19 * Rev. 1.4
20 *
21 */
22
23 /*------------------------------------------------------------------------**
24 ** **
25 ** I/O procedures **
26 ** **
27 ** inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers **
28 ** inportbxt: 8 bits only **
29 ** inport: alias of inportw **
30 ** outport: alias of outportw **
31 ** **
32 ** inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers **
33 ** inmembxt: 8 bits only **
34 ** inmem: alias of inmemw **
35 ** outmem: alias of outmemw **
36 ** **
37 **------------------------------------------------------------------------*/
38
39
40 /* MCPCIA ADDRESS BIT DEFINITIONS
41 *
42 * 3333 3333 3322 2222 2222 1111 1111 11
43 * 9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
44 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
45 * 1 000
46 * ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
47 * | |\|
48 * | Byte Enable --+ |
49 * | Transfer Length --+
50 * +-- IO space, not cached
51 *
52 * Byte Transfer
53 * Enable Length Transfer Byte Address
54 * adr<6:5> adr<4:3> Length Enable Adder
55 * ---------------------------------------------
56 * 00 00 Byte 1110 0x000
57 * 01 00 Byte 1101 0x020
58 * 10 00 Byte 1011 0x040
59 * 11 00 Byte 0111 0x060
60 *
61 * 00 01 Word 1100 0x008
62 * 01 01 Word 1001 0x028 <= Not supported in this code.
63 * 10 01 Word 0011 0x048
64 *
65 * 00 10 Tribyte 1000 0x010
66 * 01 10 Tribyte 0001 0x030
67 *
68 * 10 11 Longword 0000 0x058
69 *
70 * Note that byte enables are asserted low.
71 *
72 */
73
74 #define MCPCIA_MAX_HOSES 4
75
76 #define MCPCIA_MID(m) ((unsigned long)(m) << 33)
77
78 /* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively.
79 Durango adds PCI2 and PCI3 at MID 6 and 7 respectively. */
80 #define MCPCIA_HOSE2MID(h) ((h) + 4)
81
82 #define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */
83
84 /*
85 * Memory spaces:
86 */
87 #define MCPCIA_SPARSE(m) (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
88 #define MCPCIA_DENSE(m) (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
89 #define MCPCIA_IO(m) (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
90 #define MCPCIA_CONF(m) (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
91 #define MCPCIA_CSR(m) (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
92 #define MCPCIA_IO_IACK(m) (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
93 #define MCPCIA_DENSE_IO(m) (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
94 #define MCPCIA_DENSE_CONF(m) (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
95
96 /*
97 * General Registers
98 */
99 #define MCPCIA_REV(m) (MCPCIA_CSR(m) + 0x000)
100 #define MCPCIA_WHOAMI(m) (MCPCIA_CSR(m) + 0x040)
101 #define MCPCIA_PCI_LAT(m) (MCPCIA_CSR(m) + 0x080)
102 #define MCPCIA_CAP_CTRL(m) (MCPCIA_CSR(m) + 0x100)
103 #define MCPCIA_HAE_MEM(m) (MCPCIA_CSR(m) + 0x400)
104 #define MCPCIA_HAE_IO(m) (MCPCIA_CSR(m) + 0x440)
105 #define _MCPCIA_IACK_SC(m) (MCPCIA_CSR(m) + 0x480)
106 #define MCPCIA_HAE_DENSE(m) (MCPCIA_CSR(m) + 0x4C0)
107
108 /*
109 * Interrupt Control registers
110 */
111 #define MCPCIA_INT_CTL(m) (MCPCIA_CSR(m) + 0x500)
112 #define MCPCIA_INT_REQ(m) (MCPCIA_CSR(m) + 0x540)
113 #define MCPCIA_INT_TARG(m) (MCPCIA_CSR(m) + 0x580)
114 #define MCPCIA_INT_ADR(m) (MCPCIA_CSR(m) + 0x5C0)
115 #define MCPCIA_INT_ADR_EXT(m) (MCPCIA_CSR(m) + 0x600)
116 #define MCPCIA_INT_MASK0(m) (MCPCIA_CSR(m) + 0x640)
117 #define MCPCIA_INT_MASK1(m) (MCPCIA_CSR(m) + 0x680)
118 #define MCPCIA_INT_ACK0(m) (MCPCIA_CSR(m) + 0x10003f00)
119 #define MCPCIA_INT_ACK1(m) (MCPCIA_CSR(m) + 0x10003f40)
120
121 /*
122 * Performance Monitor registers
123 */
124 #define MCPCIA_PERF_MON(m) (MCPCIA_CSR(m) + 0x300)
125 #define MCPCIA_PERF_CONT(m) (MCPCIA_CSR(m) + 0x340)
126
127 /*
128 * Diagnostic Registers
129 */
130 #define MCPCIA_CAP_DIAG(m) (MCPCIA_CSR(m) + 0x700)
131 #define MCPCIA_TOP_OF_MEM(m) (MCPCIA_CSR(m) + 0x7C0)
132
133 /*
134 * Error registers
135 */
136 #define MCPCIA_MC_ERR0(m) (MCPCIA_CSR(m) + 0x800)
137 #define MCPCIA_MC_ERR1(m) (MCPCIA_CSR(m) + 0x840)
138 #define MCPCIA_CAP_ERR(m) (MCPCIA_CSR(m) + 0x880)
139 #define MCPCIA_PCI_ERR1(m) (MCPCIA_CSR(m) + 0x1040)
140 #define MCPCIA_MDPA_STAT(m) (MCPCIA_CSR(m) + 0x4000)
141 #define MCPCIA_MDPA_SYN(m) (MCPCIA_CSR(m) + 0x4040)
142 #define MCPCIA_MDPA_DIAG(m) (MCPCIA_CSR(m) + 0x4080)
143 #define MCPCIA_MDPB_STAT(m) (MCPCIA_CSR(m) + 0x8000)
144 #define MCPCIA_MDPB_SYN(m) (MCPCIA_CSR(m) + 0x8040)
145 #define MCPCIA_MDPB_DIAG(m) (MCPCIA_CSR(m) + 0x8080)
146
147 /*
148 * PCI Address Translation Registers.
149 */
150 #define MCPCIA_SG_TBIA(m) (MCPCIA_CSR(m) + 0x1300)
151 #define MCPCIA_HBASE(m) (MCPCIA_CSR(m) + 0x1340)
152
153 #define MCPCIA_W0_BASE(m) (MCPCIA_CSR(m) + 0x1400)
154 #define MCPCIA_W0_MASK(m) (MCPCIA_CSR(m) + 0x1440)
155 #define MCPCIA_T0_BASE(m) (MCPCIA_CSR(m) + 0x1480)
156
157 #define MCPCIA_W1_BASE(m) (MCPCIA_CSR(m) + 0x1500)
158 #define MCPCIA_W1_MASK(m) (MCPCIA_CSR(m) + 0x1540)
159 #define MCPCIA_T1_BASE(m) (MCPCIA_CSR(m) + 0x1580)
160
161 #define MCPCIA_W2_BASE(m) (MCPCIA_CSR(m) + 0x1600)
162 #define MCPCIA_W2_MASK(m) (MCPCIA_CSR(m) + 0x1640)
163 #define MCPCIA_T2_BASE(m) (MCPCIA_CSR(m) + 0x1680)
164
165 #define MCPCIA_W3_BASE(m) (MCPCIA_CSR(m) + 0x1700)
166 #define MCPCIA_W3_MASK(m) (MCPCIA_CSR(m) + 0x1740)
167 #define MCPCIA_T3_BASE(m) (MCPCIA_CSR(m) + 0x1780)
168
169 /* Hack! Only words for bus 0. */
170
171 #ifndef MCPCIA_ONE_HAE_WINDOW
172 #define MCPCIA_HAE_ADDRESS MCPCIA_HAE_MEM(4)
173 #endif
174 #define MCPCIA_IACK_SC _MCPCIA_IACK_SC(4)
175
176 /*
177 * The canonical non-remaped I/O and MEM addresses have these values
178 * subtracted out. This is arranged so that folks manipulating ISA
179 * devices can use their familiar numbers and have them map to bus 0.
180 */
181
182 #define MCPCIA_IO_BIAS MCPCIA_IO(4)
183 #define MCPCIA_MEM_BIAS MCPCIA_DENSE(4)
184
185 /* Offset between ram physical addresses and pci64 DAC bus addresses. */
186 #define MCPCIA_DAC_OFFSET (1UL << 40)
187
188 /*
189 * Data structure for handling MCPCIA machine checks:
190 */
191 struct el_MCPCIA_uncorrected_frame_mcheck {
192 struct el_common header;
193 struct el_common_EV5_uncorrectable_mcheck procdata;
194 };
195
196
197 #ifdef __KERNEL__
198
199 #ifndef __EXTERN_INLINE
200 #define __EXTERN_INLINE extern inline
201 #define __IO_EXTERN_INLINE
202 #endif
203
204 /*
205 * I/O functions:
206 *
207 * MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164)
208 * and EV56 (21164a) processors, can use either a sparse address mapping
209 * scheme, or the so-called byte-word PCI address space, to get at PCI memory
210 * and I/O.
211 *
212 * Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE.
213 */
214
215 /*
216 * Memory functions. 64-bit and 32-bit accesses are done through
217 * dense memory space, everything else through sparse space.
218 *
219 * For reading and writing 8 and 16 bit quantities we need to
220 * go through one of the three sparse address mapping regions
221 * and use the HAE_MEM CSR to provide some bits of the address.
222 * The following few routines use only sparse address region 1
223 * which gives 1Gbyte of accessible space which relates exactly
224 * to the amount of PCI memory mapping *into* system address space.
225 * See p 6-17 of the specification but it looks something like this:
226 *
227 * 21164 Address:
228 *
229 * 3 2 1
230 * 9876543210987654321098765432109876543210
231 * 1ZZZZ0.PCI.QW.Address............BBLL
232 *
233 * ZZ = SBZ
234 * BB = Byte offset
235 * LL = Transfer length
236 *
237 * PCI Address:
238 *
239 * 3 2 1
240 * 10987654321098765432109876543210
241 * HHH....PCI.QW.Address........ 00
242 *
243 * HHH = 31:29 HAE_MEM CSR
244 *
245 */
246
247 #define vip volatile int __force *
248 #define vuip volatile unsigned int __force *
249
250 #ifndef MCPCIA_ONE_HAE_WINDOW
251 #define MCPCIA_FROB_MMIO \
252 if (__mcpcia_is_mmio(hose)) { \
253 set_hae(hose & 0xffffffff); \
254 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \
255 }
256 #else
257 #define MCPCIA_FROB_MMIO \
258 if (__mcpcia_is_mmio(hose)) { \
259 hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4); \
260 }
261 #endif
262
263 extern inline int __mcpcia_is_mmio(unsigned long addr)
264 {
265 return (addr & 0x80000000UL) == 0;
266 }
267
268 __EXTERN_INLINE unsigned int mcpcia_ioread8(void __iomem *xaddr)
269 {
270 unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
271 unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
272 unsigned long result;
273
274 MCPCIA_FROB_MMIO;
275
276 result = *(vip) ((addr << 5) + hose + 0x00);
277 return __kernel_extbl(result, addr & 3);
278 }
279
280 __EXTERN_INLINE void mcpcia_iowrite8(u8 b, void __iomem *xaddr)
281 {
282 unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
283 unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
284 unsigned long w;
285
286 MCPCIA_FROB_MMIO;
287
288 w = __kernel_insbl(b, addr & 3);
289 *(vuip) ((addr << 5) + hose + 0x00) = w;
290 }
291
292 __EXTERN_INLINE unsigned int mcpcia_ioread16(void __iomem *xaddr)
293 {
294 unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
295 unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
296 unsigned long result;
297
298 MCPCIA_FROB_MMIO;
299
300 result = *(vip) ((addr << 5) + hose + 0x08);
301 return __kernel_extwl(result, addr & 3);
302 }
303
304 __EXTERN_INLINE void mcpcia_iowrite16(u16 b, void __iomem *xaddr)
305 {
306 unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
307 unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
308 unsigned long w;
309
310 MCPCIA_FROB_MMIO;
311
312 w = __kernel_inswl(b, addr & 3);
313 *(vuip) ((addr << 5) + hose + 0x08) = w;
314 }
315
316 __EXTERN_INLINE unsigned int mcpcia_ioread32(void __iomem *xaddr)
317 {
318 unsigned long addr = (unsigned long)xaddr;
319
320 if (!__mcpcia_is_mmio(addr))
321 addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
322
323 return *(vuip)addr;
324 }
325
326 __EXTERN_INLINE void mcpcia_iowrite32(u32 b, void __iomem *xaddr)
327 {
328 unsigned long addr = (unsigned long)xaddr;
329
330 if (!__mcpcia_is_mmio(addr))
331 addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
332
333 *(vuip)addr = b;
334 }
335
336
337 __EXTERN_INLINE void __iomem *mcpcia_ioportmap(unsigned long addr)
338 {
339 return (void __iomem *)(addr + MCPCIA_IO_BIAS);
340 }
341
342 __EXTERN_INLINE void __iomem *mcpcia_ioremap(unsigned long addr,
343 unsigned long size)
344 {
345 return (void __iomem *)(addr + MCPCIA_MEM_BIAS);
346 }
347
348 __EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr)
349 {
350 return addr >= MCPCIA_SPARSE(0);
351 }
352
353 __EXTERN_INLINE int mcpcia_is_mmio(const volatile void __iomem *xaddr)
354 {
355 unsigned long addr = (unsigned long) xaddr;
356 return __mcpcia_is_mmio(addr);
357 }
358
359 #undef MCPCIA_FROB_MMIO
360
361 #undef vip
362 #undef vuip
363
364 #undef __IO_PREFIX
365 #define __IO_PREFIX mcpcia
366 #define mcpcia_trivial_rw_bw 2
367 #define mcpcia_trivial_rw_lq 1
368 #define mcpcia_trivial_io_bw 0
369 #define mcpcia_trivial_io_lq 0
370 #define mcpcia_trivial_iounmap 1
371 #include <asm/io_trivial.h>
372
373 #ifdef __IO_EXTERN_INLINE
374 #undef __EXTERN_INLINE
375 #undef __IO_EXTERN_INLINE
376 #endif
377
378 #endif /* __KERNEL__ */
379
380 #endif /* __ALPHA_MCPCIA__H__ */