| blob | be16a48007b4b79fc5db0d3e48b016242b68d760 |
1 /*
2 * linux/arch/arm/kernel/entry-armv.S
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Low-level vector interface routines
13 *
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
15 * that causes it to save wrong values... Be aware!
16 */
18 #include <asm/memory.h>
19 #include <asm/glue-df.h>
20 #include <asm/glue-pf.h>
21 #include <asm/vfpmacros.h>
22 #include <mach/entry-macro.S>
23 #include <asm/thread_notify.h>
24 #include <asm/unwind.h>
25 #include <asm/unistd.h>
26 #include <asm/tls.h>
27 #include <asm/system.h>
29 #include "entry-header.S"
30 #include <asm/entry-macro-multi.S>
32 /*
33 * Interrupt handling.
34 */
35 .macro irq_handler
36 #ifdef CONFIG_MULTI_IRQ_HANDLER
37 ldr r1, =handle_arch_irq
38 mov r0, sp
39 adr lr, BSYM(9997f)
40 ldr pc, [r1]
41 #else
42 arch_irq_handler_default
43 #endif
44 9997:
45 .endm
47 .macro pabt_helper
48 @ PABORT handler takes pt_regs in r2, fault address in r4 and psr in r5
49 #ifdef MULTI_PABORT
50 ldr ip, .LCprocfns
51 mov lr, pc
52 ldr pc, [ip, #PROCESSOR_PABT_FUNC]
53 #else
54 bl CPU_PABORT_HANDLER
55 #endif
56 .endm
58 .macro dabt_helper
60 @
61 @ Call the processor-specific abort handler:
62 @
63 @ r2 - pt_regs
64 @ r4 - aborted context pc
65 @ r5 - aborted context psr
66 @
67 @ The abort handler must return the aborted address in r0, and
68 @ the fault status register in r1. r9 must be preserved.
69 @
70 #ifdef MULTI_DABORT
71 ldr ip, .LCprocfns
72 mov lr, pc
73 ldr pc, [ip, #PROCESSOR_DABT_FUNC]
74 #else
75 bl CPU_DABORT_HANDLER
76 #endif
77 .endm
79 #ifdef CONFIG_KPROBES
80 .section .kprobes.text,"ax",%progbits
81 #else
82 .text
83 #endif
85 /*
86 * Invalid mode handlers
87 */
88 .macro inv_entry, reason
89 sub sp, sp, #S_FRAME_SIZE
90 ARM( stmib sp, {r1 - lr} )
91 THUMB( stmia sp, {r0 - r12} )
92 THUMB( str sp, [sp, #S_SP] )
93 THUMB( str lr, [sp, #S_LR] )
94 mov r1, #\reason
95 .endm
97 __pabt_invalid:
98 inv_entry BAD_PREFETCH
99 b common_invalid
100 ENDPROC(__pabt_invalid)
102 __dabt_invalid:
103 inv_entry BAD_DATA
104 b common_invalid
105 ENDPROC(__dabt_invalid)
107 __irq_invalid:
108 inv_entry BAD_IRQ
109 b common_invalid
110 ENDPROC(__irq_invalid)
112 __und_invalid:
113 inv_entry BAD_UNDEFINSTR
115 @
116 @ XXX fall through to common_invalid
117 @
119 @
120 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
121 @
122 common_invalid:
123 zero_fp
125 ldmia r0, {r4 - r6}
126 add r0, sp, #S_PC @ here for interlock avoidance
127 mov r7, #-1 @ "" "" "" ""
128 str r4, [sp] @ save preserved r0
129 stmia r0, {r5 - r7} @ lr_<exception>,
130 @ cpsr_<exception>, "old_r0"
132 mov r0, sp
133 b bad_mode
134 ENDPROC(__und_invalid)
136 /*
137 * SVC mode handlers
138 */
140 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
141 #define SPFIX(code...) code
142 #else
143 #define SPFIX(code...)
144 #endif
146 .macro svc_entry, stack_hole=0
147 UNWIND(.fnstart )
148 UNWIND(.save {r0 - pc} )
149 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
150 #ifdef CONFIG_THUMB2_KERNEL
151 SPFIX( str r0, [sp] ) @ temporarily saved
152 SPFIX( mov r0, sp )
153 SPFIX( tst r0, #4 ) @ test original stack alignment
154 SPFIX( ldr r0, [sp] ) @ restored
155 #else
156 SPFIX( tst sp, #4 )
157 #endif
158 SPFIX( subeq sp, sp, #4 )
159 stmia sp, {r1 - r12}
161 ldmia r0, {r3 - r5}
162 add r7, sp, #S_SP - 4 @ here for interlock avoidance
163 mov r6, #-1 @ "" "" "" ""
164 add r2, sp, #(S_FRAME_SIZE + \stack_hole - 4)
165 SPFIX( addeq r2, r2, #4 )
166 str r3, [sp, #-4]! @ save the "real" r0 copied
167 @ from the exception stack
169 mov r3, lr
171 @
172 @ We are now ready to fill in the remaining blanks on the stack:
173 @
174 @ r2 - sp_svc
175 @ r3 - lr_svc
176 @ r4 - lr_<exception>, already fixed up for correct return/restart
177 @ r5 - spsr_<exception>
178 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
179 @
180 stmia r7, {r2 - r6}
182 #ifdef CONFIG_TRACE_IRQFLAGS
183 bl trace_hardirqs_off
184 #endif
185 .endm
187 .align 5
188 __dabt_svc:
189 svc_entry
190 mov r2, sp
191 dabt_helper
193 @
194 @ IRQs off again before pulling preserved data off the stack
195 @
196 disable_irq_notrace
198 #ifdef CONFIG_TRACE_IRQFLAGS
199 tst r5, #PSR_I_BIT
200 bleq trace_hardirqs_on
201 tst r5, #PSR_I_BIT
202 blne trace_hardirqs_off
203 #endif
204 svc_exit r5 @ return from exception
205 UNWIND(.fnend )
206 ENDPROC(__dabt_svc)
208 .align 5
209 __irq_svc:
210 svc_entry
211 irq_handler
213 #ifdef CONFIG_PREEMPT
214 get_thread_info tsk
215 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
216 ldr r0, [tsk, #TI_FLAGS] @ get flags
217 teq r8, #0 @ if preempt count != 0
218 movne r0, #0 @ force flags to 0
219 tst r0, #_TIF_NEED_RESCHED
220 blne svc_preempt
221 #endif
223 #ifdef CONFIG_TRACE_IRQFLAGS
224 @ The parent context IRQs must have been enabled to get here in
225 @ the first place, so there's no point checking the PSR I bit.
226 bl trace_hardirqs_on
227 #endif
228 svc_exit r5 @ return from exception
229 UNWIND(.fnend )
230 ENDPROC(__irq_svc)
232 .ltorg
234 #ifdef CONFIG_PREEMPT
235 svc_preempt:
236 mov r8, lr
237 1: bl preempt_schedule_irq @ irq en/disable is done inside
238 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
239 tst r0, #_TIF_NEED_RESCHED
240 moveq pc, r8 @ go again
241 b 1b
242 #endif
244 .align 5
245 __und_svc:
246 #ifdef CONFIG_KPROBES
247 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
248 @ it obviously needs free stack space which then will belong to
249 @ the saved context.
250 svc_entry 64
251 #else
252 svc_entry
253 #endif
254 @
255 @ call emulation code, which returns using r9 if it has emulated
256 @ the instruction, or the more conventional lr if we are to treat
257 @ this as a real undefined instruction
258 @
259 @ r0 - instruction
260 @
261 #ifndef CONFIG_THUMB2_KERNEL
262 ldr r0, [r4, #-4]
263 #else
264 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
265 cmp r0, #0xe800 @ 32-bit instruction if xx >= 0
266 ldrhhs r9, [r4] @ bottom 16 bits
267 orrhs r0, r9, r0, lsl #16
268 #endif
269 adr r9, BSYM(1f)
270 mov r2, r4
271 bl call_fpe
273 mov r0, sp @ struct pt_regs *regs
274 bl do_undefinstr
276 @
277 @ IRQs off again before pulling preserved data off the stack
278 @
279 1: disable_irq_notrace
281 @
282 @ restore SPSR and restart the instruction
283 @
284 ldr r5, [sp, #S_PSR] @ Get SVC cpsr
285 #ifdef CONFIG_TRACE_IRQFLAGS
286 tst r5, #PSR_I_BIT
287 bleq trace_hardirqs_on
288 tst r5, #PSR_I_BIT
289 blne trace_hardirqs_off
290 #endif
291 svc_exit r5 @ return from exception
292 UNWIND(.fnend )
293 ENDPROC(__und_svc)
295 .align 5
296 __pabt_svc:
297 svc_entry
298 mov r2, sp @ regs
299 pabt_helper
301 @
302 @ IRQs off again before pulling preserved data off the stack
303 @
304 disable_irq_notrace
306 #ifdef CONFIG_TRACE_IRQFLAGS
307 tst r5, #PSR_I_BIT
308 bleq trace_hardirqs_on
309 tst r5, #PSR_I_BIT
310 blne trace_hardirqs_off
311 #endif
312 svc_exit r5 @ return from exception
313 UNWIND(.fnend )
314 ENDPROC(__pabt_svc)
316 .align 5
317 .LCcralign:
318 .word cr_alignment
319 #ifdef MULTI_DABORT
320 .LCprocfns:
321 .word processor
322 #endif
323 .LCfp:
324 .word fp_enter
326 /*
327 * User mode handlers
328 *
329 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
330 */
332 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
333 #error "sizeof(struct pt_regs) must be a multiple of 8"
334 #endif
336 .macro usr_entry
337 UNWIND(.fnstart )
338 UNWIND(.cantunwind ) @ don't unwind the user space
339 sub sp, sp, #S_FRAME_SIZE
340 ARM( stmib sp, {r1 - r12} )
341 THUMB( stmia sp, {r0 - r12} )
343 ldmia r0, {r3 - r5}
344 add r0, sp, #S_PC @ here for interlock avoidance
345 mov r6, #-1 @ "" "" "" ""
347 str r3, [sp] @ save the "real" r0 copied
348 @ from the exception stack
350 @
351 @ We are now ready to fill in the remaining blanks on the stack:
352 @
353 @ r4 - lr_<exception>, already fixed up for correct return/restart
354 @ r5 - spsr_<exception>
355 @ r6 - orig_r0 (see pt_regs definition in ptrace.h)
356 @
357 @ Also, separately save sp_usr and lr_usr
358 @
359 stmia r0, {r4 - r6}
360 ARM( stmdb r0, {sp, lr}^ )
361 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
363 @
364 @ Enable the alignment trap while in kernel mode
365 @
366 alignment_trap r0
368 @
369 @ Clear FP to mark the first stack frame
370 @
371 zero_fp
373 #ifdef CONFIG_IRQSOFF_TRACER
374 bl trace_hardirqs_off
375 #endif
376 .endm
378 .macro kuser_cmpxchg_check
379 #if !defined(CONFIG_CPU_32v6K) && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
380 #ifndef CONFIG_MMU
381 #warning "NPTL on non MMU needs fixing"
382 #else
383 @ Make sure our user space atomic helper is restarted
384 @ if it was interrupted in a critical region. Here we
385 @ perform a quick test inline since it should be false
386 @ 99.9999% of the time. The rest is done out of line.
387 cmp r4, #TASK_SIZE
388 blhs kuser_cmpxchg64_fixup
389 #endif
390 #endif
391 .endm
393 .align 5
394 __dabt_usr:
395 usr_entry
396 kuser_cmpxchg_check
397 mov r2, sp
398 dabt_helper
399 b ret_from_exception
400 UNWIND(.fnend )
401 ENDPROC(__dabt_usr)
403 .align 5
404 __irq_usr:
405 usr_entry
406 kuser_cmpxchg_check
407 irq_handler
408 get_thread_info tsk
409 mov why, #0
410 b ret_to_user_from_irq
411 UNWIND(.fnend )
412 ENDPROC(__irq_usr)
414 .ltorg
416 .align 5
417 __und_usr:
418 usr_entry
420 mov r2, r4
421 mov r3, r5
423 @
424 @ fall through to the emulation code, which returns using r9 if
425 @ it has emulated the instruction, or the more conventional lr
426 @ if we are to treat this as a real undefined instruction
427 @
428 @ r0 - instruction
429 @
430 adr r9, BSYM(ret_from_exception)
431 adr lr, BSYM(__und_usr_unknown)
432 tst r3, #PSR_T_BIT @ Thumb mode?
433 itet eq @ explicit IT needed for the 1f label
434 subeq r4, r2, #4 @ ARM instr at LR - 4
435 subne r4, r2, #2 @ Thumb instr at LR - 2
436 1: ldreqt r0, [r4]
437 #ifdef CONFIG_CPU_ENDIAN_BE8
438 reveq r0, r0 @ little endian instruction
439 #endif
440 beq call_fpe
441 @ Thumb instruction
442 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
443 /*
444 * Thumb-2 instruction handling. Note that because pre-v6 and >= v6 platforms
445 * can never be supported in a single kernel, this code is not applicable at
446 * all when __LINUX_ARM_ARCH__ < 6. This allows simplifying assumptions to be
447 * made about .arch directives.
448 */
449 #if __LINUX_ARM_ARCH__ < 7
450 /* If the target CPU may not be Thumb-2-capable, a run-time check is needed: */
451 #define NEED_CPU_ARCHITECTURE
452 ldr r5, .LCcpu_architecture
453 ldr r5, [r5]
454 cmp r5, #CPU_ARCH_ARMv7
455 blo __und_usr_unknown
456 /*
457 * The following code won't get run unless the running CPU really is v7, so
458 * coding round the lack of ldrht on older arches is pointless. Temporarily
459 * override the assembler target arch with the minimum required instead:
460 */
461 .arch armv6t2
462 #endif
463 2:
464 ARM( ldrht r5, [r4], #2 )
465 THUMB( ldrht r5, [r4] )
466 THUMB( add r4, r4, #2 )
467 cmp r5, #0xe800 @ 32bit instruction if xx != 0
468 blo __und_usr_unknown
469 3: ldrht r0, [r4]
470 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
471 orr r0, r0, r5, lsl #16
473 #if __LINUX_ARM_ARCH__ < 7
474 /* If the target arch was overridden, change it back: */
475 #ifdef CONFIG_CPU_32v6K
476 .arch armv6k
477 #else
478 .arch armv6
479 #endif
480 #endif /* __LINUX_ARM_ARCH__ < 7 */
481 #else /* !(CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7) */
482 b __und_usr_unknown
483 #endif
484 UNWIND(.fnend )
485 ENDPROC(__und_usr)
487 @
488 @ fallthrough to call_fpe
489 @
491 /*
492 * The out of line fixup for the ldrt above.
493 */
494 .pushsection .fixup, "ax"
495 4: mov pc, r9
496 .popsection
497 .pushsection __ex_table,"a"
498 .long 1b, 4b
499 #if CONFIG_ARM_THUMB && __LINUX_ARM_ARCH__ >= 6 && CONFIG_CPU_V7
500 .long 2b, 4b
501 .long 3b, 4b
502 #endif
503 .popsection
505 /*
506 * Check whether the instruction is a co-processor instruction.
507 * If yes, we need to call the relevant co-processor handler.
508 *
509 * Note that we don't do a full check here for the co-processor
510 * instructions; all instructions with bit 27 set are well
511 * defined. The only instructions that should fault are the
512 * co-processor instructions. However, we have to watch out
513 * for the ARM6/ARM7 SWI bug.
514 *
515 * NEON is a special case that has to be handled here. Not all
516 * NEON instructions are co-processor instructions, so we have
517 * to make a special case of checking for them. Plus, there's
518 * five groups of them, so we have a table of mask/opcode pairs
519 * to check against, and if any match then we branch off into the
520 * NEON handler code.
521 *
522 * Emulators may wish to make use of the following registers:
523 * r0 = instruction opcode.
524 * r2 = PC+4
525 * r9 = normal "successful" return address
526 * r10 = this threads thread_info structure.
527 * lr = unrecognised instruction return address
528 */
529 @
530 @ Fall-through from Thumb-2 __und_usr
531 @
532 #ifdef CONFIG_NEON
533 adr r6, .LCneon_thumb_opcodes
534 b 2f
535 #endif
536 call_fpe:
537 #ifdef CONFIG_NEON
538 adr r6, .LCneon_arm_opcodes
539 2:
540 ldr r7, [r6], #4 @ mask value
541 cmp r7, #0 @ end mask?
542 beq 1f
543 and r8, r0, r7
544 ldr r7, [r6], #4 @ opcode bits matching in mask
545 cmp r8, r7 @ NEON instruction?
546 bne 2b
547 get_thread_info r10
548 mov r7, #1
549 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
550 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
551 b do_vfp @ let VFP handler handle this
552 1:
553 #endif
554 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
555 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
556 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
557 and r8, r0, #0x0f000000 @ mask out op-code bits
558 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
559 #endif
560 moveq pc, lr
561 get_thread_info r10 @ get current thread
562 and r8, r0, #0x00000f00 @ mask out CP number
563 THUMB( lsr r8, r8, #8 )
564 mov r7, #1
565 add r6, r10, #TI_USED_CP
566 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
567 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
568 #ifdef CONFIG_IWMMXT
569 @ Test if we need to give access to iWMMXt coprocessors
570 ldr r5, [r10, #TI_FLAGS]
571 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
572 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
573 bcs iwmmxt_task_enable
574 #endif
575 ARM( add pc, pc, r8, lsr #6 )
576 THUMB( lsl r8, r8, #2 )
577 THUMB( add pc, r8 )
578 nop
580 movw_pc lr @ CP#0
581 W(b) do_fpe @ CP#1 (FPE)
582 W(b) do_fpe @ CP#2 (FPE)
583 movw_pc lr @ CP#3
584 #ifdef CONFIG_CRUNCH
585 b crunch_task_enable @ CP#4 (MaverickCrunch)
586 b crunch_task_enable @ CP#5 (MaverickCrunch)
587 b crunch_task_enable @ CP#6 (MaverickCrunch)
588 #else
589 movw_pc lr @ CP#4
590 movw_pc lr @ CP#5
591 movw_pc lr @ CP#6
592 #endif
593 movw_pc lr @ CP#7
594 movw_pc lr @ CP#8
595 movw_pc lr @ CP#9
596 #ifdef CONFIG_VFP
597 W(b) do_vfp @ CP#10 (VFP)
598 W(b) do_vfp @ CP#11 (VFP)
599 #else
600 movw_pc lr @ CP#10 (VFP)
601 movw_pc lr @ CP#11 (VFP)
602 #endif
603 movw_pc lr @ CP#12
604 movw_pc lr @ CP#13
605 movw_pc lr @ CP#14 (Debug)
606 movw_pc lr @ CP#15 (Control)
608 #ifdef NEED_CPU_ARCHITECTURE
609 .align 2
610 .LCcpu_architecture:
611 .word __cpu_architecture
612 #endif
614 #ifdef CONFIG_NEON
615 .align 6
617 .LCneon_arm_opcodes:
618 .word 0xfe000000 @ mask
619 .word 0xf2000000 @ opcode
621 .word 0xff100000 @ mask
622 .word 0xf4000000 @ opcode
624 .word 0x00000000 @ mask
625 .word 0x00000000 @ opcode
627 .LCneon_thumb_opcodes:
628 .word 0xef000000 @ mask
629 .word 0xef000000 @ opcode
631 .word 0xff100000 @ mask
632 .word 0xf9000000 @ opcode
634 .word 0x00000000 @ mask
635 .word 0x00000000 @ opcode
636 #endif
638 do_fpe:
639 enable_irq
640 ldr r4, .LCfp
641 add r10, r10, #TI_FPSTATE @ r10 = workspace
642 ldr pc, [r4] @ Call FP module USR entry point
644 /*
645 * The FP module is called with these registers set:
646 * r0 = instruction
647 * r2 = PC+4
648 * r9 = normal "successful" return address
649 * r10 = FP workspace
650 * lr = unrecognised FP instruction return address
651 */
653 .pushsection .data
654 ENTRY(fp_enter)
655 .word no_fp
656 .popsection
658 ENTRY(no_fp)
659 mov pc, lr
660 ENDPROC(no_fp)
662 __und_usr_unknown:
663 enable_irq
664 mov r0, sp
665 adr lr, BSYM(ret_from_exception)
666 b do_undefinstr
667 ENDPROC(__und_usr_unknown)
669 .align 5
670 __pabt_usr:
671 usr_entry
672 mov r2, sp @ regs
673 pabt_helper
674 UNWIND(.fnend )
675 /* fall through */
676 /*
677 * This is the return code to user mode for abort handlers
678 */
679 ENTRY(ret_from_exception)
680 UNWIND(.fnstart )
681 UNWIND(.cantunwind )
682 get_thread_info tsk
683 mov why, #0
684 b ret_to_user
685 UNWIND(.fnend )
686 ENDPROC(__pabt_usr)
687 ENDPROC(ret_from_exception)
689 /*
690 * Register switch for ARMv3 and ARMv4 processors
691 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
692 * previous and next are guaranteed not to be the same.
693 */
694 ENTRY(__switch_to)
695 UNWIND(.fnstart )
696 UNWIND(.cantunwind )
697 add ip, r1, #TI_CPU_SAVE
698 ldr r3, [r2, #TI_TP_VALUE]
699 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
700 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
701 THUMB( str sp, [ip], #4 )
702 THUMB( str lr, [ip], #4 )
703 #ifdef CONFIG_CPU_USE_DOMAINS
704 ldr r6, [r2, #TI_CPU_DOMAIN]
705 #endif
706 set_tls r3, r4, r5
707 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
708 ldr r7, [r2, #TI_TASK]
709 ldr r8, =__stack_chk_guard
710 ldr r7, [r7, #TSK_STACK_CANARY]
711 #endif
712 #ifdef CONFIG_CPU_USE_DOMAINS
713 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
714 #endif
715 mov r5, r0
716 add r4, r2, #TI_CPU_SAVE
717 ldr r0, =thread_notify_head
718 mov r1, #THREAD_NOTIFY_SWITCH
719 bl atomic_notifier_call_chain
720 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
721 str r7, [r8]
722 #endif
723 THUMB( mov ip, r4 )
724 mov r0, r5
725 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
726 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
727 THUMB( ldr sp, [ip], #4 )
728 THUMB( ldr pc, [ip] )
729 UNWIND(.fnend )
730 ENDPROC(__switch_to)
732 __INIT
734 /*
735 * User helpers.
736 *
737 * Each segment is 32-byte aligned and will be moved to the top of the high
738 * vector page. New segments (if ever needed) must be added in front of
739 * existing ones. This mechanism should be used only for things that are
740 * really small and justified, and not be abused freely.
741 *
742 * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
743 */
744 THUMB( .arm )
746 .macro usr_ret, reg
747 #ifdef CONFIG_ARM_THUMB
748 bx \reg
749 #else
750 mov pc, \reg
751 #endif
752 .endm
754 .align 5
755 .globl __kuser_helper_start
756 __kuser_helper_start:
758 /*
759 * Due to the length of some sequences, __kuser_cmpxchg64 spans 2 regular
760 * kuser "slots", therefore 0xffff0f80 is not used as a valid entry point.
761 */
763 __kuser_cmpxchg64: @ 0xffff0f60
765 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
767 /*
768 * Poor you. No fast solution possible...
769 * The kernel itself must perform the operation.
770 * A special ghost syscall is used for that (see traps.c).
771 */
772 stmfd sp!, {r7, lr}
773 ldr r7, 1f @ it's 20 bits
774 swi __ARM_NR_cmpxchg64
775 ldmfd sp!, {r7, pc}
776 1: .word __ARM_NR_cmpxchg64
778 #elif defined(CONFIG_CPU_32v6K)
780 stmfd sp!, {r4, r5, r6, r7}
781 ldrd r4, r5, [r0] @ load old val
782 ldrd r6, r7, [r1] @ load new val
783 smp_dmb arm
784 1: ldrexd r0, r1, [r2] @ load current val
785 eors r3, r0, r4 @ compare with oldval (1)
786 eoreqs r3, r1, r5 @ compare with oldval (2)
787 strexdeq r3, r6, r7, [r2] @ store newval if eq
788 teqeq r3, #1 @ success?
789 beq 1b @ if no then retry
790 smp_dmb arm
791 rsbs r0, r3, #0 @ set returned val and C flag
792 ldmfd sp!, {r4, r5, r6, r7}
793 usr_ret lr
795 #elif !defined(CONFIG_SMP)
797 #ifdef CONFIG_MMU
799 /*
800 * The only thing that can break atomicity in this cmpxchg64
801 * implementation is either an IRQ or a data abort exception
802 * causing another process/thread to be scheduled in the middle of
803 * the critical sequence. The same strategy as for cmpxchg is used.
804 */
805 stmfd sp!, {r4, r5, r6, lr}
806 ldmia r0, {r4, r5} @ load old val
807 ldmia r1, {r6, lr} @ load new val
808 1: ldmia r2, {r0, r1} @ load current val
809 eors r3, r0, r4 @ compare with oldval (1)
810 eoreqs r3, r1, r5 @ compare with oldval (2)
811 2: stmeqia r2, {r6, lr} @ store newval if eq
812 rsbs r0, r3, #0 @ set return val and C flag
813 ldmfd sp!, {r4, r5, r6, pc}
815 .text
816 kuser_cmpxchg64_fixup:
817 @ Called from kuser_cmpxchg_fixup.
818 @ r4 = address of interrupted insn (must be preserved).
819 @ sp = saved regs. r7 and r8 are clobbered.
820 @ 1b = first critical insn, 2b = last critical insn.
821 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
822 mov r7, #0xffff0fff
823 sub r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
824 subs r8, r4, r7
825 rsbcss r8, r8, #(2b - 1b)
826 strcs r7, [sp, #S_PC]
827 #if __LINUX_ARM_ARCH__ < 6
828 bcc kuser_cmpxchg32_fixup
829 #endif
830 mov pc, lr
831 .previous
833 #else
834 #warning "NPTL on non MMU needs fixing"
835 mov r0, #-1
836 adds r0, r0, #0
837 usr_ret lr
838 #endif
840 #else
841 #error "incoherent kernel configuration"
842 #endif
844 /* pad to next slot */
845 .rept (16 - (. - __kuser_cmpxchg64)/4)
846 .word 0
847 .endr
849 .align 5
851 __kuser_memory_barrier: @ 0xffff0fa0
852 smp_dmb arm
853 usr_ret lr
855 .align 5
857 __kuser_cmpxchg: @ 0xffff0fc0
859 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
861 /*
862 * Poor you. No fast solution possible...
863 * The kernel itself must perform the operation.
864 * A special ghost syscall is used for that (see traps.c).
865 */
866 stmfd sp!, {r7, lr}
867 ldr r7, 1f @ it's 20 bits
868 swi __ARM_NR_cmpxchg
869 ldmfd sp!, {r7, pc}
870 1: .word __ARM_NR_cmpxchg
872 #elif __LINUX_ARM_ARCH__ < 6
874 #ifdef CONFIG_MMU
876 /*
877 * The only thing that can break atomicity in this cmpxchg
878 * implementation is either an IRQ or a data abort exception
879 * causing another process/thread to be scheduled in the middle
880 * of the critical sequence. To prevent this, code is added to
881 * the IRQ and data abort exception handlers to set the pc back
882 * to the beginning of the critical section if it is found to be
883 * within that critical section (see kuser_cmpxchg_fixup).
884 */
885 1: ldr r3, [r2] @ load current val
886 subs r3, r3, r0 @ compare with oldval
887 2: streq r1, [r2] @ store newval if eq
888 rsbs r0, r3, #0 @ set return val and C flag
889 usr_ret lr
891 .text
892 kuser_cmpxchg32_fixup:
893 @ Called from kuser_cmpxchg_check macro.
894 @ r4 = address of interrupted insn (must be preserved).
895 @ sp = saved regs. r7 and r8 are clobbered.
896 @ 1b = first critical insn, 2b = last critical insn.
897 @ If r4 >= 1b and r4 <= 2b then saved pc_usr is set to 1b.
898 mov r7, #0xffff0fff
899 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
900 subs r8, r4, r7
901 rsbcss r8, r8, #(2b - 1b)
902 strcs r7, [sp, #S_PC]
903 mov pc, lr
904 .previous
906 #else
907 #warning "NPTL on non MMU needs fixing"
908 mov r0, #-1
909 adds r0, r0, #0
910 usr_ret lr
911 #endif
913 #else
915 smp_dmb arm
916 1: ldrex r3, [r2]
917 subs r3, r3, r0
918 strexeq r3, r1, [r2]
919 teqeq r3, #1
920 beq 1b
921 rsbs r0, r3, #0
922 /* beware -- each __kuser slot must be 8 instructions max */
923 ALT_SMP(b __kuser_memory_barrier)
924 ALT_UP(usr_ret lr)
926 #endif
928 .align 5
930 __kuser_get_tls: @ 0xffff0fe0
931 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
932 usr_ret lr
933 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
934 .rep 4
935 .word 0 @ 0xffff0ff0 software TLS value, then
936 .endr @ pad up to __kuser_helper_version
938 __kuser_helper_version: @ 0xffff0ffc
939 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
941 .globl __kuser_helper_end
942 __kuser_helper_end:
944 THUMB( .thumb )
946 /*
947 * Vector stubs.
948 *
949 * This code is copied to 0xffff0200 so we can use branches in the
950 * vectors, rather than ldr's. Note that this code must not
951 * exceed 0x300 bytes.
952 *
953 * Common stub entry macro:
954 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
955 *
956 * SP points to a minimal amount of processor-private memory, the address
957 * of which is copied into r0 for the mode specific abort handler.
958 */
959 .macro vector_stub, name, mode, correction=0
960 .align 5
962 vector_\name:
963 .if \correction
964 sub lr, lr, #\correction
965 .endif
967 @
968 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
969 @ (parent CPSR)
970 @
971 stmia sp, {r0, lr} @ save r0, lr
972 mrs lr, spsr
973 str lr, [sp, #8] @ save spsr
975 @
976 @ Prepare for SVC32 mode. IRQs remain disabled.
977 @
978 mrs r0, cpsr
979 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
980 msr spsr_cxsf, r0
982 @
983 @ the branch table must immediately follow this code
984 @
985 and lr, lr, #0x0f
986 THUMB( adr r0, 1f )
987 THUMB( ldr lr, [r0, lr, lsl #2] )
988 mov r0, sp
989 ARM( ldr lr, [pc, lr, lsl #2] )
990 movs pc, lr @ branch to handler in SVC mode
991 ENDPROC(vector_\name)
993 .align 2
994 @ handler addresses follow this label
995 1:
996 .endm
998 .globl __stubs_start
999 __stubs_start:
1000 /*
1001 * Interrupt dispatcher
1002 */
1003 vector_stub irq, IRQ_MODE, 4
1005 .long __irq_usr @ 0 (USR_26 / USR_32)
1006 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1007 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1008 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1009 .long __irq_invalid @ 4
1010 .long __irq_invalid @ 5
1011 .long __irq_invalid @ 6
1012 .long __irq_invalid @ 7
1013 .long __irq_invalid @ 8
1014 .long __irq_invalid @ 9
1015 .long __irq_invalid @ a
1016 .long __irq_invalid @ b
1017 .long __irq_invalid @ c
1018 .long __irq_invalid @ d
1019 .long __irq_invalid @ e
1020 .long __irq_invalid @ f
1022 /*
1023 * Data abort dispatcher
1024 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1025 */
1026 vector_stub dabt, ABT_MODE, 8
1028 .long __dabt_usr @ 0 (USR_26 / USR_32)
1029 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1030 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1031 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1032 .long __dabt_invalid @ 4
1033 .long __dabt_invalid @ 5
1034 .long __dabt_invalid @ 6
1035 .long __dabt_invalid @ 7
1036 .long __dabt_invalid @ 8
1037 .long __dabt_invalid @ 9
1038 .long __dabt_invalid @ a
1039 .long __dabt_invalid @ b
1040 .long __dabt_invalid @ c
1041 .long __dabt_invalid @ d
1042 .long __dabt_invalid @ e
1043 .long __dabt_invalid @ f
1045 /*
1046 * Prefetch abort dispatcher
1047 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1048 */
1049 vector_stub pabt, ABT_MODE, 4
1051 .long __pabt_usr @ 0 (USR_26 / USR_32)
1052 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1053 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1054 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1055 .long __pabt_invalid @ 4
1056 .long __pabt_invalid @ 5
1057 .long __pabt_invalid @ 6
1058 .long __pabt_invalid @ 7
1059 .long __pabt_invalid @ 8
1060 .long __pabt_invalid @ 9
1061 .long __pabt_invalid @ a
1062 .long __pabt_invalid @ b
1063 .long __pabt_invalid @ c
1064 .long __pabt_invalid @ d
1065 .long __pabt_invalid @ e
1066 .long __pabt_invalid @ f
1068 /*
1069 * Undef instr entry dispatcher
1070 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1071 */
1072 vector_stub und, UND_MODE
1074 .long __und_usr @ 0 (USR_26 / USR_32)
1075 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1076 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1077 .long __und_svc @ 3 (SVC_26 / SVC_32)
1078 .long __und_invalid @ 4
1079 .long __und_invalid @ 5
1080 .long __und_invalid @ 6
1081 .long __und_invalid @ 7
1082 .long __und_invalid @ 8
1083 .long __und_invalid @ 9
1084 .long __und_invalid @ a
1085 .long __und_invalid @ b
1086 .long __und_invalid @ c
1087 .long __und_invalid @ d
1088 .long __und_invalid @ e
1089 .long __und_invalid @ f
1091 .align 5
1093 /*=============================================================================
1094 * Undefined FIQs
1095 *-----------------------------------------------------------------------------
1096 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1097 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1098 * Basically to switch modes, we *HAVE* to clobber one register... brain
1099 * damage alert! I don't think that we can execute any code in here in any
1100 * other mode than FIQ... Ok you can switch to another mode, but you can't
1101 * get out of that mode without clobbering one register.
1102 */
1103 vector_fiq:
1104 disable_fiq
1105 subs pc, lr, #4
1107 /*=============================================================================
1108 * Address exception handler
1109 *-----------------------------------------------------------------------------
1110 * These aren't too critical.
1111 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1112 */
1114 vector_addrexcptn:
1115 b vector_addrexcptn
1117 /*
1118 * We group all the following data together to optimise
1119 * for CPUs with separate I & D caches.
1120 */
1121 .align 5
1123 .LCvswi:
1124 .word vector_swi
1126 .globl __stubs_end
1127 __stubs_end:
1129 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1131 .globl __vectors_start
1132 __vectors_start:
1133 ARM( swi SYS_ERROR0 )
1134 THUMB( svc #0 )
1135 THUMB( nop )
1136 W(b) vector_und + stubs_offset
1137 W(ldr) pc, .LCvswi + stubs_offset
1138 W(b) vector_pabt + stubs_offset
1139 W(b) vector_dabt + stubs_offset
1140 W(b) vector_addrexcptn + stubs_offset
1141 W(b) vector_irq + stubs_offset
1142 W(b) vector_fiq + stubs_offset
1144 .globl __vectors_end
1145 __vectors_end:
1147 .data
1149 .globl cr_alignment
1150 .globl cr_no_alignment
1151 cr_alignment:
1152 .space 4
1153 cr_no_alignment:
1154 .space 4
1156 #ifdef CONFIG_MULTI_IRQ_HANDLER
1157 .globl handle_arch_irq
1158 handle_arch_irq:
1159 .space 4
1160 #endif