arch/arm/mach-at91/include/mach/at91_aic.h

   1 /*
   2  * arch/arm/mach-at91/include/mach/at91_aic.h
   3  *
   4  * Copyright (C) 2005 Ivan Kokshaysky
   5  * Copyright (C) SAN People
   6  *
   7  * Advanced Interrupt Controller (AIC) - System peripherals registers.
   8  * Based on AT91RM9200 datasheet revision E.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #ifndef AT91_AIC_H
  17 #define AT91_AIC_H
  18
  19 #ifndef __ASSEMBLY__
  20 extern void __iomem *at91_aic_base;
  21
  22 #define at91_aic_read(field) \
  23         __raw_readl(at91_aic_base + field)
  24
  25 #define at91_aic_write(field, value) \
  26         __raw_writel(value, at91_aic_base + field);
  27 #else
  28 .extern at91_aic_base
  29 #endif
  30
  31 #define AT91_AIC_SMR(n)         ((n) * 4)               /* Source Mode Registers 0-31 */
  32 #define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
  33 #define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
  34 #define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
  35 #define                 AT91_AIC_SRCTYPE_FALLING        (1 << 5)
  36 #define                 AT91_AIC_SRCTYPE_HIGH           (2 << 5)
  37 #define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
  38
  39 #define AT91_AIC_SVR(n)         (0x80 + ((n) * 4))      /* Source Vector Registers 0-31 */
  40 #define AT91_AIC_IVR            0x100                   /* Interrupt Vector Register */
  41 #define AT91_AIC_FVR            0x104                   /* Fast Interrupt Vector Register */
  42 #define AT91_AIC_ISR            0x108                   /* Interrupt Status Register */
  43 #define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
  44
  45 #define AT91_AIC_IPR            0x10c                   /* Interrupt Pending Register */
  46 #define AT91_AIC_IMR            0x110                   /* Interrupt Mask Register */
  47 #define AT91_AIC_CISR           0x114                   /* Core Interrupt Status Register */
  48 #define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
  49 #define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
  50
  51 #define AT91_AIC_IECR           0x120                   /* Interrupt Enable Command Register */
  52 #define AT91_AIC_IDCR           0x124                   /* Interrupt Disable Command Register */
  53 #define AT91_AIC_ICCR           0x128                   /* Interrupt Clear Command Register */
  54 #define AT91_AIC_ISCR           0x12c                   /* Interrupt Set Command Register */
  55 #define AT91_AIC_EOICR          0x130                   /* End of Interrupt Command Register */
  56 #define AT91_AIC_SPU            0x134                   /* Spurious Interrupt Vector Register */
  57 #define AT91_AIC_DCR            0x138                   /* Debug Control Register */
  58 #define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
  59 #define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
  60
  61 #define AT91_AIC_FFER           0x140                   /* Fast Forcing Enable Register [SAM9 only] */
  62 #define AT91_AIC_FFDR           0x144                   /* Fast Forcing Disable Register [SAM9 only] */
  63 #define AT91_AIC_FFSR           0x148                   /* Fast Forcing Status Register [SAM9 only] */
  64
  65 #endif