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spi-topcliff-pch: Fix issue for transmitting over 4KByte
[zen-stable.git] / arch / arm / mach-davinci / board-dm646x-evm.c
blob872ac69fa0490af84501ac13d73a792bf5f6aea7
1 /*
2 * TI DaVinci DM646X EVM board
3 *
4 * Derived from: arch/arm/mach-davinci/board-evm.c
5 * Copyright (C) 2006 Texas Instruments.
6 *
7 * (C) 2007-2008, MontaVista Software, Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 *
13 */
14
15 /**************************************************************************
16 * Included Files
17 **************************************************************************/
18
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/leds.h>
22 #include <linux/gpio.h>
23 #include <linux/platform_device.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c/at24.h>
26 #include <linux/i2c/pcf857x.h>
27
28 #include <media/tvp514x.h>
29
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/clk.h>
34 #include <linux/export.h>
35
36 #include <asm/mach-types.h>
37 #include <asm/mach/arch.h>
38
39 #include <mach/dm646x.h>
40 #include <mach/common.h>
41 #include <mach/serial.h>
42 #include <mach/i2c.h>
43 #include <mach/nand.h>
44 #include <mach/clock.h>
45 #include <mach/cdce949.h>
46 #include <mach/aemif.h>
47
48 #include "clock.h"
49
50 #define NAND_BLOCK_SIZE SZ_128K
51
52 /* Note: We are setting first partition as 'bootloader' constituting UBL, U-Boot
53 * and U-Boot environment this avoids dependency on any particular combination
54 * of UBL, U-Boot or flashing tools etc.
55 */
56 static struct mtd_partition davinci_nand_partitions[] = {
57 {
58 /* UBL, U-Boot with environment */
59 .name = "bootloader",
60 .offset = MTDPART_OFS_APPEND,
61 .size = 16 * NAND_BLOCK_SIZE,
62 .mask_flags = MTD_WRITEABLE, /* force read-only */
63 }, {
64 .name = "kernel",
65 .offset = MTDPART_OFS_APPEND,
66 .size = SZ_4M,
67 .mask_flags = 0,
68 }, {
69 .name = "filesystem",
70 .offset = MTDPART_OFS_APPEND,
71 .size = MTDPART_SIZ_FULL,
72 .mask_flags = 0,
73 }
74 };
75
76 static struct davinci_aemif_timing dm6467tevm_nandflash_timing = {
77 .wsetup = 29,
78 .wstrobe = 24,
79 .whold = 14,
80 .rsetup = 19,
81 .rstrobe = 33,
82 .rhold = 0,
83 .ta = 29,
84 };
85
86 static struct davinci_nand_pdata davinci_nand_data = {
87 .mask_cle = 0x80000,
88 .mask_ale = 0x40000,
89 .parts = davinci_nand_partitions,
90 .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
91 .ecc_mode = NAND_ECC_HW,
92 .options = 0,
93 };
94
95 static struct resource davinci_nand_resources[] = {
96 {
97 .start = DM646X_ASYNC_EMIF_CS2_SPACE_BASE,
98 .end = DM646X_ASYNC_EMIF_CS2_SPACE_BASE + SZ_32M - 1,
99 .flags = IORESOURCE_MEM,
100 }, {
101 .start = DM646X_ASYNC_EMIF_CONTROL_BASE,
102 .end = DM646X_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
103 .flags = IORESOURCE_MEM,
104 },
105 };
106
107 static struct platform_device davinci_nand_device = {
108 .name = "davinci_nand",
109 .id = 0,
110
111 .num_resources = ARRAY_SIZE(davinci_nand_resources),
112 .resource = davinci_nand_resources,
113
114 .dev = {
115 .platform_data = &davinci_nand_data,
116 },
117 };
118
119 #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
120 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
121 #define HAS_ATA 1
122 #else
123 #define HAS_ATA 0
124 #endif
125
126 /* CPLD Register 0 bits to control ATA */
127 #define DM646X_EVM_ATA_RST BIT(0)
128 #define DM646X_EVM_ATA_PWD BIT(1)
129
130 /* CPLD Register 0 Client: used for I/O Control */
131 static int cpld_reg0_probe(struct i2c_client *client,
132 const struct i2c_device_id *id)
133 {
134 if (HAS_ATA) {
135 u8 data;
136 struct i2c_msg msg[2] = {
137 {
138 .addr = client->addr,
139 .flags = I2C_M_RD,
140 .len = 1,
141 .buf = &data,
142 },
143 {
144 .addr = client->addr,
145 .flags = 0,
146 .len = 1,
147 .buf = &data,
148 },
149 };
150
151 /* Clear ATA_RSTn and ATA_PWD bits to enable ATA operation. */
152 i2c_transfer(client->adapter, msg, 1);
153 data &= ~(DM646X_EVM_ATA_RST | DM646X_EVM_ATA_PWD);
154 i2c_transfer(client->adapter, msg + 1, 1);
155 }
156
157 return 0;
158 }
159
160 static const struct i2c_device_id cpld_reg_ids[] = {
161 { "cpld_reg0", 0, },
162 { },
163 };
164
165 static struct i2c_driver dm6467evm_cpld_driver = {
166 .driver.name = "cpld_reg0",
167 .id_table = cpld_reg_ids,
168 .probe = cpld_reg0_probe,
169 };
170
171 /* LEDS */
172
173 static struct gpio_led evm_leds[] = {
174 { .name = "DS1", .active_low = 1, },
175 { .name = "DS2", .active_low = 1, },
176 { .name = "DS3", .active_low = 1, },
177 { .name = "DS4", .active_low = 1, },
178 };
179
180 static const struct gpio_led_platform_data evm_led_data = {
181 .num_leds = ARRAY_SIZE(evm_leds),
182 .leds = evm_leds,
183 };
184
185 static struct platform_device *evm_led_dev;
186
187 static int evm_led_setup(struct i2c_client *client, int gpio,
188 unsigned int ngpio, void *c)
189 {
190 struct gpio_led *leds = evm_leds;
191 int status;
192
193 while (ngpio--) {
194 leds->gpio = gpio++;
195 leds++;
196 };
197
198 evm_led_dev = platform_device_alloc("leds-gpio", 0);
199 platform_device_add_data(evm_led_dev, &evm_led_data,
200 sizeof(evm_led_data));
201
202 evm_led_dev->dev.parent = &client->dev;
203 status = platform_device_add(evm_led_dev);
204 if (status < 0) {
205 platform_device_put(evm_led_dev);
206 evm_led_dev = NULL;
207 }
208 return status;
209 }
210
211 static int evm_led_teardown(struct i2c_client *client, int gpio,
212 unsigned ngpio, void *c)
213 {
214 if (evm_led_dev) {
215 platform_device_unregister(evm_led_dev);
216 evm_led_dev = NULL;
217 }
218 return 0;
219 }
220
221 static int evm_sw_gpio[4] = { -EINVAL, -EINVAL, -EINVAL, -EINVAL };
222
223 static int evm_sw_setup(struct i2c_client *client, int gpio,
224 unsigned ngpio, void *c)
225 {
226 int status;
227 int i;
228 char label[10];
229
230 for (i = 0; i < 4; ++i) {
231 snprintf(label, 10, "user_sw%d", i);
232 status = gpio_request(gpio, label);
233 if (status)
234 goto out_free;
235 evm_sw_gpio[i] = gpio++;
236
237 status = gpio_direction_input(evm_sw_gpio[i]);
238 if (status) {
239 gpio_free(evm_sw_gpio[i]);
240 evm_sw_gpio[i] = -EINVAL;
241 goto out_free;
242 }
243
244 status = gpio_export(evm_sw_gpio[i], 0);
245 if (status) {
246 gpio_free(evm_sw_gpio[i]);
247 evm_sw_gpio[i] = -EINVAL;
248 goto out_free;
249 }
250 }
251 return status;
252 out_free:
253 for (i = 0; i < 4; ++i) {
254 if (evm_sw_gpio[i] != -EINVAL) {
255 gpio_free(evm_sw_gpio[i]);
256 evm_sw_gpio[i] = -EINVAL;
257 }
258 }
259 return status;
260 }
261
262 static int evm_sw_teardown(struct i2c_client *client, int gpio,
263 unsigned ngpio, void *c)
264 {
265 int i;
266
267 for (i = 0; i < 4; ++i) {
268 if (evm_sw_gpio[i] != -EINVAL) {
269 gpio_unexport(evm_sw_gpio[i]);
270 gpio_free(evm_sw_gpio[i]);
271 evm_sw_gpio[i] = -EINVAL;
272 }
273 }
274 return 0;
275 }
276
277 static int evm_pcf_setup(struct i2c_client *client, int gpio,
278 unsigned int ngpio, void *c)
279 {
280 int status;
281
282 if (ngpio < 8)
283 return -EINVAL;
284
285 status = evm_sw_setup(client, gpio, 4, c);
286 if (status)
287 return status;
288
289 return evm_led_setup(client, gpio+4, 4, c);
290 }
291
292 static int evm_pcf_teardown(struct i2c_client *client, int gpio,
293 unsigned int ngpio, void *c)
294 {
295 BUG_ON(ngpio < 8);
296
297 evm_sw_teardown(client, gpio, 4, c);
298 evm_led_teardown(client, gpio+4, 4, c);
299
300 return 0;
301 }
302
303 static struct pcf857x_platform_data pcf_data = {
304 .gpio_base = DAVINCI_N_GPIO+1,
305 .setup = evm_pcf_setup,
306 .teardown = evm_pcf_teardown,
307 };
308
309 /* Most of this EEPROM is unused, but U-Boot uses some data:
310 * - 0x7f00, 6 bytes Ethernet Address
311 * - ... newer boards may have more
312 */
313
314 static struct at24_platform_data eeprom_info = {
315 .byte_len = (256*1024) / 8,
316 .page_size = 64,
317 .flags = AT24_FLAG_ADDR16,
318 .setup = davinci_get_mac_addr,
319 .context = (void *)0x7f00,
320 };
321
322 static u8 dm646x_iis_serializer_direction[] = {
323 TX_MODE, RX_MODE, INACTIVE_MODE, INACTIVE_MODE,
324 };
325
326 static u8 dm646x_dit_serializer_direction[] = {
327 TX_MODE,
328 };
329
330 static struct snd_platform_data dm646x_evm_snd_data[] = {
331 {
332 .tx_dma_offset = 0x400,
333 .rx_dma_offset = 0x400,
334 .op_mode = DAVINCI_MCASP_IIS_MODE,
335 .num_serializer = ARRAY_SIZE(dm646x_iis_serializer_direction),
336 .tdm_slots = 2,
337 .serial_dir = dm646x_iis_serializer_direction,
338 .asp_chan_q = EVENTQ_0,
339 },
340 {
341 .tx_dma_offset = 0x400,
342 .rx_dma_offset = 0,
343 .op_mode = DAVINCI_MCASP_DIT_MODE,
344 .num_serializer = ARRAY_SIZE(dm646x_dit_serializer_direction),
345 .tdm_slots = 32,
346 .serial_dir = dm646x_dit_serializer_direction,
347 .asp_chan_q = EVENTQ_0,
348 },
349 };
350
351 static struct i2c_client *cpld_client;
352
353 static int cpld_video_probe(struct i2c_client *client,
354 const struct i2c_device_id *id)
355 {
356 cpld_client = client;
357 return 0;
358 }
359
360 static int __devexit cpld_video_remove(struct i2c_client *client)
361 {
362 cpld_client = NULL;
363 return 0;
364 }
365
366 static const struct i2c_device_id cpld_video_id[] = {
367 { "cpld_video", 0 },
368 { }
369 };
370
371 static struct i2c_driver cpld_video_driver = {
372 .driver = {
373 .name = "cpld_video",
374 },
375 .probe = cpld_video_probe,
376 .remove = cpld_video_remove,
377 .id_table = cpld_video_id,
378 };
379
380 static void evm_init_cpld(void)
381 {
382 i2c_add_driver(&cpld_video_driver);
383 }
384
385 static struct i2c_board_info __initdata i2c_info[] = {
386 {
387 I2C_BOARD_INFO("24c256", 0x50),
388 .platform_data = &eeprom_info,
389 },
390 {
391 I2C_BOARD_INFO("pcf8574a", 0x38),
392 .platform_data = &pcf_data,
393 },
394 {
395 I2C_BOARD_INFO("cpld_reg0", 0x3a),
396 },
397 {
398 I2C_BOARD_INFO("tlv320aic33", 0x18),
399 },
400 {
401 I2C_BOARD_INFO("cpld_video", 0x3b),
402 },
403 {
404 I2C_BOARD_INFO("cdce949", 0x6c),
405 },
406 };
407
408 static struct davinci_i2c_platform_data i2c_pdata = {
409 .bus_freq = 100 /* kHz */,
410 .bus_delay = 0 /* usec */,
411 };
412
413 #define VIDCLKCTL_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x38)
414 #define VSCLKDIS_OFFSET (DAVINCI_SYSTEM_MODULE_BASE + 0x6c)
415 #define VCH2CLK_MASK (BIT_MASK(10) | BIT_MASK(9) | BIT_MASK(8))
416 #define VCH2CLK_SYSCLK8 (BIT(9))
417 #define VCH2CLK_AUXCLK (BIT(9) | BIT(8))
418 #define VCH3CLK_MASK (BIT_MASK(14) | BIT_MASK(13) | BIT_MASK(12))
419 #define VCH3CLK_SYSCLK8 (BIT(13))
420 #define VCH3CLK_AUXCLK (BIT(14) | BIT(13))
421
422 #define VIDCH2CLK (BIT(10))
423 #define VIDCH3CLK (BIT(11))
424 #define VIDCH1CLK (BIT(4))
425 #define TVP7002_INPUT (BIT(4))
426 #define TVP5147_INPUT (~BIT(4))
427 #define VPIF_INPUT_ONE_CHANNEL (BIT(5))
428 #define VPIF_INPUT_TWO_CHANNEL (~BIT(5))
429 #define TVP5147_CH0 "tvp514x-0"
430 #define TVP5147_CH1 "tvp514x-1"
431
432 static void __iomem *vpif_vidclkctl_reg;
433 static void __iomem *vpif_vsclkdis_reg;
434 /* spin lock for updating above registers */
435 static spinlock_t vpif_reg_lock;
436
437 static int set_vpif_clock(int mux_mode, int hd)
438 {
439 unsigned long flags;
440 unsigned int value;
441 int val = 0;
442 int err = 0;
443
444 if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg || !cpld_client)
445 return -ENXIO;
446
447 /* disable the clock */
448 spin_lock_irqsave(&vpif_reg_lock, flags);
449 value = __raw_readl(vpif_vsclkdis_reg);
450 value |= (VIDCH3CLK | VIDCH2CLK);
451 __raw_writel(value, vpif_vsclkdis_reg);
452 spin_unlock_irqrestore(&vpif_reg_lock, flags);
453
454 val = i2c_smbus_read_byte(cpld_client);
455 if (val < 0)
456 return val;
457
458 if (mux_mode == 1)
459 val &= ~0x40;
460 else
461 val |= 0x40;
462
463 err = i2c_smbus_write_byte(cpld_client, val);
464 if (err)
465 return err;
466
467 value = __raw_readl(vpif_vidclkctl_reg);
468 value &= ~(VCH2CLK_MASK);
469 value &= ~(VCH3CLK_MASK);
470
471 if (hd >= 1)
472 value |= (VCH2CLK_SYSCLK8 | VCH3CLK_SYSCLK8);
473 else
474 value |= (VCH2CLK_AUXCLK | VCH3CLK_AUXCLK);
475
476 __raw_writel(value, vpif_vidclkctl_reg);
477
478 spin_lock_irqsave(&vpif_reg_lock, flags);
479 value = __raw_readl(vpif_vsclkdis_reg);
480 /* enable the clock */
481 value &= ~(VIDCH3CLK | VIDCH2CLK);
482 __raw_writel(value, vpif_vsclkdis_reg);
483 spin_unlock_irqrestore(&vpif_reg_lock, flags);
484
485 return 0;
486 }
487
488 static struct vpif_subdev_info dm646x_vpif_subdev[] = {
489 {
490 .name = "adv7343",
491 .board_info = {
492 I2C_BOARD_INFO("adv7343", 0x2a),
493 },
494 },
495 {
496 .name = "ths7303",
497 .board_info = {
498 I2C_BOARD_INFO("ths7303", 0x2c),
499 },
500 },
501 };
502
503 static const char *output[] = {
504 "Composite",
505 "Component",
506 "S-Video",
507 };
508
509 static struct vpif_display_config dm646x_vpif_display_config = {
510 .set_clock = set_vpif_clock,
511 .subdevinfo = dm646x_vpif_subdev,
512 .subdev_count = ARRAY_SIZE(dm646x_vpif_subdev),
513 .output = output,
514 .output_count = ARRAY_SIZE(output),
515 .card_name = "DM646x EVM",
516 };
517
518 /**
519 * setup_vpif_input_path()
520 * @channel: channel id (0 - CH0, 1 - CH1)
521 * @sub_dev_name: ptr sub device name
522 *
523 * This will set vpif input to capture data from tvp514x or
524 * tvp7002.
525 */
526 static int setup_vpif_input_path(int channel, const char *sub_dev_name)
527 {
528 int err = 0;
529 int val;
530
531 /* for channel 1, we don't do anything */
532 if (channel != 0)
533 return 0;
534
535 if (!cpld_client)
536 return -ENXIO;
537
538 val = i2c_smbus_read_byte(cpld_client);
539 if (val < 0)
540 return val;
541
542 if (!strcmp(sub_dev_name, TVP5147_CH0) ||
543 !strcmp(sub_dev_name, TVP5147_CH1))
544 val &= TVP5147_INPUT;
545 else
546 val |= TVP7002_INPUT;
547
548 err = i2c_smbus_write_byte(cpld_client, val);
549 if (err)
550 return err;
551 return 0;
552 }
553
554 /**
555 * setup_vpif_input_channel_mode()
556 * @mux_mode: mux mode. 0 - 1 channel or (1) - 2 channel
557 *
558 * This will setup input mode to one channel (TVP7002) or 2 channel (TVP5147)
559 */
560 static int setup_vpif_input_channel_mode(int mux_mode)
561 {
562 unsigned long flags;
563 int err = 0;
564 int val;
565 u32 value;
566
567 if (!vpif_vidclkctl_reg || !cpld_client)
568 return -ENXIO;
569
570 val = i2c_smbus_read_byte(cpld_client);
571 if (val < 0)
572 return val;
573
574 spin_lock_irqsave(&vpif_reg_lock, flags);
575 value = __raw_readl(vpif_vidclkctl_reg);
576 if (mux_mode) {
577 val &= VPIF_INPUT_TWO_CHANNEL;
578 value |= VIDCH1CLK;
579 } else {
580 val |= VPIF_INPUT_ONE_CHANNEL;
581 value &= ~VIDCH1CLK;
582 }
583 __raw_writel(value, vpif_vidclkctl_reg);
584 spin_unlock_irqrestore(&vpif_reg_lock, flags);
585
586 err = i2c_smbus_write_byte(cpld_client, val);
587 if (err)
588 return err;
589
590 return 0;
591 }
592
593 static struct tvp514x_platform_data tvp5146_pdata = {
594 .clk_polarity = 0,
595 .hs_polarity = 1,
596 .vs_polarity = 1
597 };
598
599 #define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
600
601 static struct vpif_subdev_info vpif_capture_sdev_info[] = {
602 {
603 .name = TVP5147_CH0,
604 .board_info = {
605 I2C_BOARD_INFO("tvp5146", 0x5d),
606 .platform_data = &tvp5146_pdata,
607 },
608 .input = INPUT_CVBS_VI2B,
609 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
610 .can_route = 1,
611 .vpif_if = {
612 .if_type = VPIF_IF_BT656,
613 .hd_pol = 1,
614 .vd_pol = 1,
615 .fid_pol = 0,
616 },
617 },
618 {
619 .name = TVP5147_CH1,
620 .board_info = {
621 I2C_BOARD_INFO("tvp5146", 0x5c),
622 .platform_data = &tvp5146_pdata,
623 },
624 .input = INPUT_SVIDEO_VI2C_VI1C,
625 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
626 .can_route = 1,
627 .vpif_if = {
628 .if_type = VPIF_IF_BT656,
629 .hd_pol = 1,
630 .vd_pol = 1,
631 .fid_pol = 0,
632 },
633 },
634 };
635
636 static const struct vpif_input dm6467_ch0_inputs[] = {
637 {
638 .input = {
639 .index = 0,
640 .name = "Composite",
641 .type = V4L2_INPUT_TYPE_CAMERA,
642 .std = TVP514X_STD_ALL,
643 },
644 .subdev_name = TVP5147_CH0,
645 },
646 };
647
648 static const struct vpif_input dm6467_ch1_inputs[] = {
649 {
650 .input = {
651 .index = 0,
652 .name = "S-Video",
653 .type = V4L2_INPUT_TYPE_CAMERA,
654 .std = TVP514X_STD_ALL,
655 },
656 .subdev_name = TVP5147_CH1,
657 },
658 };
659
660 static struct vpif_capture_config dm646x_vpif_capture_cfg = {
661 .setup_input_path = setup_vpif_input_path,
662 .setup_input_channel_mode = setup_vpif_input_channel_mode,
663 .subdev_info = vpif_capture_sdev_info,
664 .subdev_count = ARRAY_SIZE(vpif_capture_sdev_info),
665 .chan_config[0] = {
666 .inputs = dm6467_ch0_inputs,
667 .input_count = ARRAY_SIZE(dm6467_ch0_inputs),
668 },
669 .chan_config[1] = {
670 .inputs = dm6467_ch1_inputs,
671 .input_count = ARRAY_SIZE(dm6467_ch1_inputs),
672 },
673 };
674
675 static void __init evm_init_video(void)
676 {
677 vpif_vidclkctl_reg = ioremap(VIDCLKCTL_OFFSET, 4);
678 vpif_vsclkdis_reg = ioremap(VSCLKDIS_OFFSET, 4);
679 if (!vpif_vidclkctl_reg || !vpif_vsclkdis_reg) {
680 pr_err("Can't map VPIF VIDCLKCTL or VSCLKDIS registers\n");
681 return;
682 }
683 spin_lock_init(&vpif_reg_lock);
684
685 dm646x_setup_vpif(&dm646x_vpif_display_config,
686 &dm646x_vpif_capture_cfg);
687 }
688
689 static void __init evm_init_i2c(void)
690 {
691 davinci_init_i2c(&i2c_pdata);
692 i2c_add_driver(&dm6467evm_cpld_driver);
693 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
694 evm_init_cpld();
695 evm_init_video();
696 }
697
698 #define CDCE949_XIN_RATE 27000000
699
700 /* CDCE949 support - "lpsc" field is overridden to work as clock number */
701 static struct clk cdce_clk_in = {
702 .name = "cdce_xin",
703 .rate = CDCE949_XIN_RATE,
704 };
705
706 static struct clk_lookup cdce_clks[] = {
707 CLK(NULL, "xin", &cdce_clk_in),
708 CLK(NULL, NULL, NULL),
709 };
710
711 static void __init cdce_clk_init(void)
712 {
713 struct clk_lookup *c;
714 struct clk *clk;
715
716 for (c = cdce_clks; c->clk; c++) {
717 clk = c->clk;
718 clkdev_add(c);
719 clk_register(clk);
720 }
721 }
722
723 #define DM6467T_EVM_REF_FREQ 33000000
724
725 static void __init davinci_map_io(void)
726 {
727 dm646x_init();
728
729 if (machine_is_davinci_dm6467tevm())
730 davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
731
732 cdce_clk_init();
733 }
734
735 static struct davinci_uart_config uart_config __initdata = {
736 .enabled_uarts = (1 << 0),
737 };
738
739 #define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
740 /*
741 * The following EDMA channels/slots are not being used by drivers (for
742 * example: Timer, GPIO, UART events etc) on dm646x, hence they are being
743 * reserved for codecs on the DSP side.
744 */
745 static const s16 dm646x_dma_rsv_chans[][2] = {
746 /* (offset, number) */
747 { 0, 4},
748 {13, 3},
749 {24, 4},
750 {30, 2},
751 {54, 3},
752 {-1, -1}
753 };
754
755 static const s16 dm646x_dma_rsv_slots[][2] = {
756 /* (offset, number) */
757 { 0, 4},
758 {13, 3},
759 {24, 4},
760 {30, 2},
761 {54, 3},
762 {128, 384},
763 {-1, -1}
764 };
765
766 static struct edma_rsv_info dm646x_edma_rsv[] = {
767 {
768 .rsv_chans = dm646x_dma_rsv_chans,
769 .rsv_slots = dm646x_dma_rsv_slots,
770 },
771 };
772
773 static __init void evm_init(void)
774 {
775 struct davinci_soc_info *soc_info = &davinci_soc_info;
776
777 evm_init_i2c();
778 davinci_serial_init(&uart_config);
779 dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
780 dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
781
782 if (machine_is_davinci_dm6467tevm())
783 davinci_nand_data.timing = &dm6467tevm_nandflash_timing;
784
785 platform_device_register(&davinci_nand_device);
786
787 dm646x_init_edma(dm646x_edma_rsv);
788
789 if (HAS_ATA)
790 davinci_init_ide();
791
792 soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
793 }
794
795 MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
796 .atag_offset = 0x100,
797 .map_io = davinci_map_io,
798 .init_irq = davinci_irq_init,
799 .timer = &davinci_timer,
800 .init_machine = evm_init,
801 .dma_zone_size = SZ_128M,
802 .restart = davinci_restart,
803 MACHINE_END
804
805 MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
806 .atag_offset = 0x100,
807 .map_io = davinci_map_io,
808 .init_irq = davinci_irq_init,
809 .timer = &davinci_timer,
810 .init_machine = evm_init,
811 .dma_zone_size = SZ_128M,
812 .restart = davinci_restart,
813 MACHINE_END
814