2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/dma-mapping.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/serial_8250.h>
15 #include <linux/platform_device.h>
17 #include <asm/mach/map.h>
19 #include <mach/dm646x.h>
20 #include <mach/cputype.h>
21 #include <mach/edma.h>
22 #include <mach/irqs.h>
25 #include <mach/time.h>
26 #include <mach/serial.h>
27 #include <mach/common.h>
29 #include <mach/gpio-davinci.h>
34 #define DAVINCI_VPIF_BASE (0x01C12000)
35 #define VDD3P3V_PWDN_OFFSET (0x48)
36 #define VSCLKDIS_OFFSET (0x6C)
38 #define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
40 #define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
44 * Device specific clocks
46 #define DM646X_REF_FREQ 27000000
47 #define DM646X_AUX_FREQ 24000000
49 static struct pll_data pll1_data
= {
51 .phys_base
= DAVINCI_PLL1_BASE
,
54 static struct pll_data pll2_data
= {
56 .phys_base
= DAVINCI_PLL2_BASE
,
59 static struct clk ref_clk
= {
61 .rate
= DM646X_REF_FREQ
,
62 .set_rate
= davinci_simple_set_rate
,
65 static struct clk aux_clkin
= {
67 .rate
= DM646X_AUX_FREQ
,
70 static struct clk pll1_clk
= {
73 .pll_data
= &pll1_data
,
77 static struct clk pll1_sysclk1
= {
78 .name
= "pll1_sysclk1",
84 static struct clk pll1_sysclk2
= {
85 .name
= "pll1_sysclk2",
91 static struct clk pll1_sysclk3
= {
92 .name
= "pll1_sysclk3",
98 static struct clk pll1_sysclk4
= {
99 .name
= "pll1_sysclk4",
105 static struct clk pll1_sysclk5
= {
106 .name
= "pll1_sysclk5",
112 static struct clk pll1_sysclk6
= {
113 .name
= "pll1_sysclk6",
119 static struct clk pll1_sysclk8
= {
120 .name
= "pll1_sysclk8",
126 static struct clk pll1_sysclk9
= {
127 .name
= "pll1_sysclk9",
133 static struct clk pll1_sysclkbp
= {
134 .name
= "pll1_sysclkbp",
136 .flags
= CLK_PLL
| PRE_PLL
,
140 static struct clk pll1_aux_clk
= {
141 .name
= "pll1_aux_clk",
143 .flags
= CLK_PLL
| PRE_PLL
,
146 static struct clk pll2_clk
= {
149 .pll_data
= &pll2_data
,
153 static struct clk pll2_sysclk1
= {
154 .name
= "pll2_sysclk1",
160 static struct clk dsp_clk
= {
162 .parent
= &pll1_sysclk1
,
163 .lpsc
= DM646X_LPSC_C64X_CPU
,
164 .usecount
= 1, /* REVISIT how to disable? */
167 static struct clk arm_clk
= {
169 .parent
= &pll1_sysclk2
,
170 .lpsc
= DM646X_LPSC_ARM
,
171 .flags
= ALWAYS_ENABLED
,
174 static struct clk edma_cc_clk
= {
176 .parent
= &pll1_sysclk2
,
177 .lpsc
= DM646X_LPSC_TPCC
,
178 .flags
= ALWAYS_ENABLED
,
181 static struct clk edma_tc0_clk
= {
183 .parent
= &pll1_sysclk2
,
184 .lpsc
= DM646X_LPSC_TPTC0
,
185 .flags
= ALWAYS_ENABLED
,
188 static struct clk edma_tc1_clk
= {
190 .parent
= &pll1_sysclk2
,
191 .lpsc
= DM646X_LPSC_TPTC1
,
192 .flags
= ALWAYS_ENABLED
,
195 static struct clk edma_tc2_clk
= {
197 .parent
= &pll1_sysclk2
,
198 .lpsc
= DM646X_LPSC_TPTC2
,
199 .flags
= ALWAYS_ENABLED
,
202 static struct clk edma_tc3_clk
= {
204 .parent
= &pll1_sysclk2
,
205 .lpsc
= DM646X_LPSC_TPTC3
,
206 .flags
= ALWAYS_ENABLED
,
209 static struct clk uart0_clk
= {
211 .parent
= &aux_clkin
,
212 .lpsc
= DM646X_LPSC_UART0
,
215 static struct clk uart1_clk
= {
217 .parent
= &aux_clkin
,
218 .lpsc
= DM646X_LPSC_UART1
,
221 static struct clk uart2_clk
= {
223 .parent
= &aux_clkin
,
224 .lpsc
= DM646X_LPSC_UART2
,
227 static struct clk i2c_clk
= {
229 .parent
= &pll1_sysclk3
,
230 .lpsc
= DM646X_LPSC_I2C
,
233 static struct clk gpio_clk
= {
235 .parent
= &pll1_sysclk3
,
236 .lpsc
= DM646X_LPSC_GPIO
,
239 static struct clk mcasp0_clk
= {
241 .parent
= &pll1_sysclk3
,
242 .lpsc
= DM646X_LPSC_McASP0
,
245 static struct clk mcasp1_clk
= {
247 .parent
= &pll1_sysclk3
,
248 .lpsc
= DM646X_LPSC_McASP1
,
251 static struct clk aemif_clk
= {
253 .parent
= &pll1_sysclk3
,
254 .lpsc
= DM646X_LPSC_AEMIF
,
255 .flags
= ALWAYS_ENABLED
,
258 static struct clk emac_clk
= {
260 .parent
= &pll1_sysclk3
,
261 .lpsc
= DM646X_LPSC_EMAC
,
264 static struct clk pwm0_clk
= {
266 .parent
= &pll1_sysclk3
,
267 .lpsc
= DM646X_LPSC_PWM0
,
268 .usecount
= 1, /* REVIST: disabling hangs system */
271 static struct clk pwm1_clk
= {
273 .parent
= &pll1_sysclk3
,
274 .lpsc
= DM646X_LPSC_PWM1
,
275 .usecount
= 1, /* REVIST: disabling hangs system */
278 static struct clk timer0_clk
= {
280 .parent
= &pll1_sysclk3
,
281 .lpsc
= DM646X_LPSC_TIMER0
,
284 static struct clk timer1_clk
= {
286 .parent
= &pll1_sysclk3
,
287 .lpsc
= DM646X_LPSC_TIMER1
,
290 static struct clk timer2_clk
= {
292 .parent
= &pll1_sysclk3
,
293 .flags
= ALWAYS_ENABLED
, /* no LPSC, always enabled; c.f. spruep9a */
297 static struct clk ide_clk
= {
299 .parent
= &pll1_sysclk4
,
300 .lpsc
= DAVINCI_LPSC_ATA
,
303 static struct clk vpif0_clk
= {
306 .lpsc
= DM646X_LPSC_VPSSMSTR
,
307 .flags
= ALWAYS_ENABLED
,
310 static struct clk vpif1_clk
= {
313 .lpsc
= DM646X_LPSC_VPSSSLV
,
314 .flags
= ALWAYS_ENABLED
,
317 static struct clk_lookup dm646x_clks
[] = {
318 CLK(NULL
, "ref", &ref_clk
),
319 CLK(NULL
, "aux", &aux_clkin
),
320 CLK(NULL
, "pll1", &pll1_clk
),
321 CLK(NULL
, "pll1_sysclk", &pll1_sysclk1
),
322 CLK(NULL
, "pll1_sysclk", &pll1_sysclk2
),
323 CLK(NULL
, "pll1_sysclk", &pll1_sysclk3
),
324 CLK(NULL
, "pll1_sysclk", &pll1_sysclk4
),
325 CLK(NULL
, "pll1_sysclk", &pll1_sysclk5
),
326 CLK(NULL
, "pll1_sysclk", &pll1_sysclk6
),
327 CLK(NULL
, "pll1_sysclk", &pll1_sysclk8
),
328 CLK(NULL
, "pll1_sysclk", &pll1_sysclk9
),
329 CLK(NULL
, "pll1_sysclk", &pll1_sysclkbp
),
330 CLK(NULL
, "pll1_aux", &pll1_aux_clk
),
331 CLK(NULL
, "pll2", &pll2_clk
),
332 CLK(NULL
, "pll2_sysclk1", &pll2_sysclk1
),
333 CLK(NULL
, "dsp", &dsp_clk
),
334 CLK(NULL
, "arm", &arm_clk
),
335 CLK(NULL
, "edma_cc", &edma_cc_clk
),
336 CLK(NULL
, "edma_tc0", &edma_tc0_clk
),
337 CLK(NULL
, "edma_tc1", &edma_tc1_clk
),
338 CLK(NULL
, "edma_tc2", &edma_tc2_clk
),
339 CLK(NULL
, "edma_tc3", &edma_tc3_clk
),
340 CLK(NULL
, "uart0", &uart0_clk
),
341 CLK(NULL
, "uart1", &uart1_clk
),
342 CLK(NULL
, "uart2", &uart2_clk
),
343 CLK("i2c_davinci.1", NULL
, &i2c_clk
),
344 CLK(NULL
, "gpio", &gpio_clk
),
345 CLK("davinci-mcasp.0", NULL
, &mcasp0_clk
),
346 CLK("davinci-mcasp.1", NULL
, &mcasp1_clk
),
347 CLK(NULL
, "aemif", &aemif_clk
),
348 CLK("davinci_emac.1", NULL
, &emac_clk
),
349 CLK(NULL
, "pwm0", &pwm0_clk
),
350 CLK(NULL
, "pwm1", &pwm1_clk
),
351 CLK(NULL
, "timer0", &timer0_clk
),
352 CLK(NULL
, "timer1", &timer1_clk
),
353 CLK("watchdog", NULL
, &timer2_clk
),
354 CLK("palm_bk3710", NULL
, &ide_clk
),
355 CLK(NULL
, "vpif0", &vpif0_clk
),
356 CLK(NULL
, "vpif1", &vpif1_clk
),
357 CLK(NULL
, NULL
, NULL
),
360 static struct emac_platform_data dm646x_emac_pdata
= {
361 .ctrl_reg_offset
= DM646X_EMAC_CNTRL_OFFSET
,
362 .ctrl_mod_reg_offset
= DM646X_EMAC_CNTRL_MOD_OFFSET
,
363 .ctrl_ram_offset
= DM646X_EMAC_CNTRL_RAM_OFFSET
,
364 .ctrl_ram_size
= DM646X_EMAC_CNTRL_RAM_SIZE
,
365 .version
= EMAC_VERSION_2
,
368 static struct resource dm646x_emac_resources
[] = {
370 .start
= DM646X_EMAC_BASE
,
371 .end
= DM646X_EMAC_BASE
+ SZ_16K
- 1,
372 .flags
= IORESOURCE_MEM
,
375 .start
= IRQ_DM646X_EMACRXTHINT
,
376 .end
= IRQ_DM646X_EMACRXTHINT
,
377 .flags
= IORESOURCE_IRQ
,
380 .start
= IRQ_DM646X_EMACRXINT
,
381 .end
= IRQ_DM646X_EMACRXINT
,
382 .flags
= IORESOURCE_IRQ
,
385 .start
= IRQ_DM646X_EMACTXINT
,
386 .end
= IRQ_DM646X_EMACTXINT
,
387 .flags
= IORESOURCE_IRQ
,
390 .start
= IRQ_DM646X_EMACMISCINT
,
391 .end
= IRQ_DM646X_EMACMISCINT
,
392 .flags
= IORESOURCE_IRQ
,
396 static struct platform_device dm646x_emac_device
= {
397 .name
= "davinci_emac",
400 .platform_data
= &dm646x_emac_pdata
,
402 .num_resources
= ARRAY_SIZE(dm646x_emac_resources
),
403 .resource
= dm646x_emac_resources
,
406 static struct resource dm646x_mdio_resources
[] = {
408 .start
= DM646X_EMAC_MDIO_BASE
,
409 .end
= DM646X_EMAC_MDIO_BASE
+ SZ_4K
- 1,
410 .flags
= IORESOURCE_MEM
,
414 static struct platform_device dm646x_mdio_device
= {
415 .name
= "davinci_mdio",
417 .num_resources
= ARRAY_SIZE(dm646x_mdio_resources
),
418 .resource
= dm646x_mdio_resources
,
422 * Device specific mux setup
424 * soc description mux mode mode mux dbg
425 * reg offset mask mode
427 static const struct mux_config dm646x_pins
[] = {
428 #ifdef CONFIG_DAVINCI_MUX
429 MUX_CFG(DM646X
, ATAEN
, 0, 0, 5, 1, true)
431 MUX_CFG(DM646X
, AUDCK1
, 0, 29, 1, 0, false)
433 MUX_CFG(DM646X
, AUDCK0
, 0, 28, 1, 0, false)
435 MUX_CFG(DM646X
, CRGMUX
, 0, 24, 7, 5, true)
437 MUX_CFG(DM646X
, STSOMUX_DISABLE
, 0, 22, 3, 0, true)
439 MUX_CFG(DM646X
, STSIMUX_DISABLE
, 0, 20, 3, 0, true)
441 MUX_CFG(DM646X
, PTSOMUX_DISABLE
, 0, 18, 3, 0, true)
443 MUX_CFG(DM646X
, PTSIMUX_DISABLE
, 0, 16, 3, 0, true)
445 MUX_CFG(DM646X
, STSOMUX
, 0, 22, 3, 2, true)
447 MUX_CFG(DM646X
, STSIMUX
, 0, 20, 3, 2, true)
449 MUX_CFG(DM646X
, PTSOMUX_PARALLEL
, 0, 18, 3, 2, true)
451 MUX_CFG(DM646X
, PTSIMUX_PARALLEL
, 0, 16, 3, 2, true)
453 MUX_CFG(DM646X
, PTSOMUX_SERIAL
, 0, 18, 3, 3, true)
455 MUX_CFG(DM646X
, PTSIMUX_SERIAL
, 0, 16, 3, 3, true)
459 static u8 dm646x_default_priorities
[DAVINCI_N_AINTC_IRQ
] = {
460 [IRQ_DM646X_VP_VERTINT0
] = 7,
461 [IRQ_DM646X_VP_VERTINT1
] = 7,
462 [IRQ_DM646X_VP_VERTINT2
] = 7,
463 [IRQ_DM646X_VP_VERTINT3
] = 7,
464 [IRQ_DM646X_VP_ERRINT
] = 7,
465 [IRQ_DM646X_RESERVED_1
] = 7,
466 [IRQ_DM646X_RESERVED_2
] = 7,
467 [IRQ_DM646X_WDINT
] = 7,
468 [IRQ_DM646X_CRGENINT0
] = 7,
469 [IRQ_DM646X_CRGENINT1
] = 7,
470 [IRQ_DM646X_TSIFINT0
] = 7,
471 [IRQ_DM646X_TSIFINT1
] = 7,
472 [IRQ_DM646X_VDCEINT
] = 7,
473 [IRQ_DM646X_USBINT
] = 7,
474 [IRQ_DM646X_USBDMAINT
] = 7,
475 [IRQ_DM646X_PCIINT
] = 7,
476 [IRQ_CCINT0
] = 7, /* dma */
477 [IRQ_CCERRINT
] = 7, /* dma */
478 [IRQ_TCERRINT0
] = 7, /* dma */
479 [IRQ_TCERRINT
] = 7, /* dma */
480 [IRQ_DM646X_TCERRINT2
] = 7,
481 [IRQ_DM646X_TCERRINT3
] = 7,
482 [IRQ_DM646X_IDE
] = 7,
483 [IRQ_DM646X_HPIINT
] = 7,
484 [IRQ_DM646X_EMACRXTHINT
] = 7,
485 [IRQ_DM646X_EMACRXINT
] = 7,
486 [IRQ_DM646X_EMACTXINT
] = 7,
487 [IRQ_DM646X_EMACMISCINT
] = 7,
488 [IRQ_DM646X_MCASP0TXINT
] = 7,
489 [IRQ_DM646X_MCASP0RXINT
] = 7,
491 [IRQ_DM646X_RESERVED_3
] = 7,
492 [IRQ_DM646X_MCASP1TXINT
] = 7, /* clockevent */
493 [IRQ_TINT0_TINT34
] = 7, /* clocksource */
494 [IRQ_TINT1_TINT12
] = 7, /* DSP timer */
495 [IRQ_TINT1_TINT34
] = 7, /* system tick */
498 [IRQ_DM646X_VLQINT
] = 7,
502 [IRQ_DM646X_UARTINT2
] = 7,
503 [IRQ_DM646X_SPINT0
] = 7,
504 [IRQ_DM646X_SPINT1
] = 7,
505 [IRQ_DM646X_DSP2ARMINT
] = 7,
506 [IRQ_DM646X_RESERVED_4
] = 7,
507 [IRQ_DM646X_PSCINT
] = 7,
508 [IRQ_DM646X_GPIO0
] = 7,
509 [IRQ_DM646X_GPIO1
] = 7,
510 [IRQ_DM646X_GPIO2
] = 7,
511 [IRQ_DM646X_GPIO3
] = 7,
512 [IRQ_DM646X_GPIO4
] = 7,
513 [IRQ_DM646X_GPIO5
] = 7,
514 [IRQ_DM646X_GPIO6
] = 7,
515 [IRQ_DM646X_GPIO7
] = 7,
516 [IRQ_DM646X_GPIOBNK0
] = 7,
517 [IRQ_DM646X_GPIOBNK1
] = 7,
518 [IRQ_DM646X_GPIOBNK2
] = 7,
519 [IRQ_DM646X_DDRINT
] = 7,
520 [IRQ_DM646X_AEMIFINT
] = 7,
526 /*----------------------------------------------------------------------*/
528 /* Four Transfer Controllers on DM646x */
530 dm646x_queue_tc_mapping
[][2] = {
531 /* {event queue no, TC no} */
540 dm646x_queue_priority_mapping
[][2] = {
541 /* {event queue no, Priority} */
549 static struct edma_soc_info edma_cc0_info
= {
551 .n_region
= 6, /* 0-1, 4-7 */
555 .queue_tc_mapping
= dm646x_queue_tc_mapping
,
556 .queue_priority_mapping
= dm646x_queue_priority_mapping
,
557 .default_queue
= EVENTQ_1
,
560 static struct edma_soc_info
*dm646x_edma_info
[EDMA_MAX_CC
] = {
564 static struct resource edma_resources
[] = {
568 .end
= 0x01c00000 + SZ_64K
- 1,
569 .flags
= IORESOURCE_MEM
,
574 .end
= 0x01c10000 + SZ_1K
- 1,
575 .flags
= IORESOURCE_MEM
,
580 .end
= 0x01c10400 + SZ_1K
- 1,
581 .flags
= IORESOURCE_MEM
,
586 .end
= 0x01c10800 + SZ_1K
- 1,
587 .flags
= IORESOURCE_MEM
,
592 .end
= 0x01c10c00 + SZ_1K
- 1,
593 .flags
= IORESOURCE_MEM
,
598 .flags
= IORESOURCE_IRQ
,
602 .start
= IRQ_CCERRINT
,
603 .flags
= IORESOURCE_IRQ
,
605 /* not using TC*_ERR */
608 static struct platform_device dm646x_edma_device
= {
611 .dev
.platform_data
= dm646x_edma_info
,
612 .num_resources
= ARRAY_SIZE(edma_resources
),
613 .resource
= edma_resources
,
616 static struct resource dm646x_mcasp0_resources
[] = {
619 .start
= DAVINCI_DM646X_MCASP0_REG_BASE
,
620 .end
= DAVINCI_DM646X_MCASP0_REG_BASE
+ (SZ_1K
<< 1) - 1,
621 .flags
= IORESOURCE_MEM
,
623 /* first TX, then RX */
625 .start
= DAVINCI_DM646X_DMA_MCASP0_AXEVT0
,
626 .end
= DAVINCI_DM646X_DMA_MCASP0_AXEVT0
,
627 .flags
= IORESOURCE_DMA
,
630 .start
= DAVINCI_DM646X_DMA_MCASP0_AREVT0
,
631 .end
= DAVINCI_DM646X_DMA_MCASP0_AREVT0
,
632 .flags
= IORESOURCE_DMA
,
636 static struct resource dm646x_mcasp1_resources
[] = {
639 .start
= DAVINCI_DM646X_MCASP1_REG_BASE
,
640 .end
= DAVINCI_DM646X_MCASP1_REG_BASE
+ (SZ_1K
<< 1) - 1,
641 .flags
= IORESOURCE_MEM
,
643 /* DIT mode, only TX event */
645 .start
= DAVINCI_DM646X_DMA_MCASP1_AXEVT1
,
646 .end
= DAVINCI_DM646X_DMA_MCASP1_AXEVT1
,
647 .flags
= IORESOURCE_DMA
,
649 /* DIT mode, dummy entry */
653 .flags
= IORESOURCE_DMA
,
657 static struct platform_device dm646x_mcasp0_device
= {
658 .name
= "davinci-mcasp",
660 .num_resources
= ARRAY_SIZE(dm646x_mcasp0_resources
),
661 .resource
= dm646x_mcasp0_resources
,
664 static struct platform_device dm646x_mcasp1_device
= {
665 .name
= "davinci-mcasp",
667 .num_resources
= ARRAY_SIZE(dm646x_mcasp1_resources
),
668 .resource
= dm646x_mcasp1_resources
,
671 static struct platform_device dm646x_dit_device
= {
676 static u64 vpif_dma_mask
= DMA_BIT_MASK(32);
678 static struct resource vpif_resource
[] = {
680 .start
= DAVINCI_VPIF_BASE
,
681 .end
= DAVINCI_VPIF_BASE
+ 0x03ff,
682 .flags
= IORESOURCE_MEM
,
686 static struct platform_device vpif_dev
= {
690 .dma_mask
= &vpif_dma_mask
,
691 .coherent_dma_mask
= DMA_BIT_MASK(32),
693 .resource
= vpif_resource
,
694 .num_resources
= ARRAY_SIZE(vpif_resource
),
697 static struct resource vpif_display_resource
[] = {
699 .start
= IRQ_DM646X_VP_VERTINT2
,
700 .end
= IRQ_DM646X_VP_VERTINT2
,
701 .flags
= IORESOURCE_IRQ
,
704 .start
= IRQ_DM646X_VP_VERTINT3
,
705 .end
= IRQ_DM646X_VP_VERTINT3
,
706 .flags
= IORESOURCE_IRQ
,
710 static struct platform_device vpif_display_dev
= {
711 .name
= "vpif_display",
714 .dma_mask
= &vpif_dma_mask
,
715 .coherent_dma_mask
= DMA_BIT_MASK(32),
717 .resource
= vpif_display_resource
,
718 .num_resources
= ARRAY_SIZE(vpif_display_resource
),
721 static struct resource vpif_capture_resource
[] = {
723 .start
= IRQ_DM646X_VP_VERTINT0
,
724 .end
= IRQ_DM646X_VP_VERTINT0
,
725 .flags
= IORESOURCE_IRQ
,
728 .start
= IRQ_DM646X_VP_VERTINT1
,
729 .end
= IRQ_DM646X_VP_VERTINT1
,
730 .flags
= IORESOURCE_IRQ
,
734 static struct platform_device vpif_capture_dev
= {
735 .name
= "vpif_capture",
738 .dma_mask
= &vpif_dma_mask
,
739 .coherent_dma_mask
= DMA_BIT_MASK(32),
741 .resource
= vpif_capture_resource
,
742 .num_resources
= ARRAY_SIZE(vpif_capture_resource
),
745 /*----------------------------------------------------------------------*/
747 static struct map_desc dm646x_io_desc
[] = {
750 .pfn
= __phys_to_pfn(IO_PHYS
),
755 .virtual = SRAM_VIRT
,
756 .pfn
= __phys_to_pfn(0x00010000),
758 .type
= MT_MEMORY_NONCACHED
,
762 /* Contents of JTAG ID register used to identify exact cpu type */
763 static struct davinci_id dm646x_ids
[] = {
767 .manufacturer
= 0x017,
768 .cpu_id
= DAVINCI_CPU_ID_DM6467
,
769 .name
= "dm6467_rev1.x",
774 .manufacturer
= 0x017,
775 .cpu_id
= DAVINCI_CPU_ID_DM6467
,
776 .name
= "dm6467_rev3.x",
780 static u32 dm646x_psc_bases
[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE
};
783 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
784 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
785 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
786 * T1_TOP: Timer 1, top : <unused>
788 static struct davinci_timer_info dm646x_timer_info
= {
789 .timers
= davinci_timer_instance
,
790 .clockevent_id
= T0_BOT
,
791 .clocksource_id
= T0_TOP
,
794 static struct plat_serial8250_port dm646x_serial_platform_data
[] = {
796 .mapbase
= DAVINCI_UART0_BASE
,
798 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
800 .iotype
= UPIO_MEM32
,
804 .mapbase
= DAVINCI_UART1_BASE
,
806 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
808 .iotype
= UPIO_MEM32
,
812 .mapbase
= DAVINCI_UART2_BASE
,
813 .irq
= IRQ_DM646X_UARTINT2
,
814 .flags
= UPF_BOOT_AUTOCONF
| UPF_SKIP_TEST
|
816 .iotype
= UPIO_MEM32
,
824 static struct platform_device dm646x_serial_device
= {
825 .name
= "serial8250",
826 .id
= PLAT8250_DEV_PLATFORM
,
828 .platform_data
= dm646x_serial_platform_data
,
832 static struct davinci_soc_info davinci_soc_info_dm646x
= {
833 .io_desc
= dm646x_io_desc
,
834 .io_desc_num
= ARRAY_SIZE(dm646x_io_desc
),
835 .jtag_id_reg
= 0x01c40028,
837 .ids_num
= ARRAY_SIZE(dm646x_ids
),
838 .cpu_clks
= dm646x_clks
,
839 .psc_bases
= dm646x_psc_bases
,
840 .psc_bases_num
= ARRAY_SIZE(dm646x_psc_bases
),
841 .pinmux_base
= DAVINCI_SYSTEM_MODULE_BASE
,
842 .pinmux_pins
= dm646x_pins
,
843 .pinmux_pins_num
= ARRAY_SIZE(dm646x_pins
),
844 .intc_base
= DAVINCI_ARM_INTC_BASE
,
845 .intc_type
= DAVINCI_INTC_TYPE_AINTC
,
846 .intc_irq_prios
= dm646x_default_priorities
,
847 .intc_irq_num
= DAVINCI_N_AINTC_IRQ
,
848 .timer_info
= &dm646x_timer_info
,
849 .gpio_type
= GPIO_TYPE_DAVINCI
,
850 .gpio_base
= DAVINCI_GPIO_BASE
,
851 .gpio_num
= 43, /* Only 33 usable */
852 .gpio_irq
= IRQ_DM646X_GPIOBNK0
,
853 .serial_dev
= &dm646x_serial_device
,
854 .emac_pdata
= &dm646x_emac_pdata
,
855 .sram_dma
= 0x10010000,
859 void __init
dm646x_init_mcasp0(struct snd_platform_data
*pdata
)
861 dm646x_mcasp0_device
.dev
.platform_data
= pdata
;
862 platform_device_register(&dm646x_mcasp0_device
);
865 void __init
dm646x_init_mcasp1(struct snd_platform_data
*pdata
)
867 dm646x_mcasp1_device
.dev
.platform_data
= pdata
;
868 platform_device_register(&dm646x_mcasp1_device
);
869 platform_device_register(&dm646x_dit_device
);
872 void dm646x_setup_vpif(struct vpif_display_config
*display_config
,
873 struct vpif_capture_config
*capture_config
)
876 void __iomem
*base
= IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE
);
878 value
= __raw_readl(base
+ VSCLKDIS_OFFSET
);
879 value
&= ~VSCLKDIS_MASK
;
880 __raw_writel(value
, base
+ VSCLKDIS_OFFSET
);
882 value
= __raw_readl(base
+ VDD3P3V_PWDN_OFFSET
);
883 value
&= ~VDD3P3V_VID_MASK
;
884 __raw_writel(value
, base
+ VDD3P3V_PWDN_OFFSET
);
886 davinci_cfg_reg(DM646X_STSOMUX_DISABLE
);
887 davinci_cfg_reg(DM646X_STSIMUX_DISABLE
);
888 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE
);
889 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE
);
891 vpif_display_dev
.dev
.platform_data
= display_config
;
892 vpif_capture_dev
.dev
.platform_data
= capture_config
;
893 platform_device_register(&vpif_dev
);
894 platform_device_register(&vpif_display_dev
);
895 platform_device_register(&vpif_capture_dev
);
898 int __init
dm646x_init_edma(struct edma_rsv_info
*rsv
)
900 edma_cc0_info
.rsv
= rsv
;
902 return platform_device_register(&dm646x_edma_device
);
905 void __init
dm646x_init(void)
907 davinci_common_init(&davinci_soc_info_dm646x
);
910 static int __init
dm646x_init_devices(void)
912 if (!cpu_is_davinci_dm646x())
915 platform_device_register(&dm646x_mdio_device
);
916 platform_device_register(&dm646x_emac_device
);
917 clk_add_alias(NULL
, dev_name(&dm646x_mdio_device
.dev
),
918 NULL
, &dm646x_emac_device
.dev
);
922 postcore_initcall(dm646x_init_devices
);