arch/arm/mach-imx/include/mach/dma-v1.h

   1 /*
   2  *  linux/arch/arm/mach-imx/include/mach/dma-v1.h
   3  *
   4  *  i.MX DMA registration and IRQ dispatching
   5  *
   6  * Copyright 2006 Pavel Pisa <pisa@cmp.felk.cvut.cz>
   7  * Copyright 2008 Juergen Beisert, <kernel@pengutronix.de>
   8  * Copyright 2008 Sascha Hauer, <s.hauer@pengutronix.de>
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  22  * MA 02110-1301, USA.
  23  */
  24
  25 #ifndef __MACH_DMA_V1_H__
  26 #define __MACH_DMA_V1_H__
  27
  28 #define imx_has_dma_v1()        (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
  29
  30 #include <mach/dma.h>
  31
  32 #define IMX_DMA_CHANNELS  16
  33
  34 #define DMA_MODE_READ           0
  35 #define DMA_MODE_WRITE          1
  36 #define DMA_MODE_MASK           1
  37
  38 #define MX1_DMA_REG(offset)     MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
  39
  40 /* DMA Interrupt Mask Register */
  41 #define MX1_DMA_DIMR            MX1_DMA_REG(0x08)
  42
  43 /* Channel Control Register */
  44 #define MX1_DMA_CCR(x)          MX1_DMA_REG(0x8c + ((x) << 6))
  45
  46 #define IMX_DMA_MEMSIZE_32      (0 << 4)
  47 #define IMX_DMA_MEMSIZE_8       (1 << 4)
  48 #define IMX_DMA_MEMSIZE_16      (2 << 4)
  49 #define IMX_DMA_TYPE_LINEAR     (0 << 10)
  50 #define IMX_DMA_TYPE_2D         (1 << 10)
  51 #define IMX_DMA_TYPE_FIFO       (2 << 10)
  52
  53 #define IMX_DMA_ERR_BURST     (1 << 0)
  54 #define IMX_DMA_ERR_REQUEST   (1 << 1)
  55 #define IMX_DMA_ERR_TRANSFER  (1 << 2)
  56 #define IMX_DMA_ERR_BUFFER    (1 << 3)
  57 #define IMX_DMA_ERR_TIMEOUT   (1 << 4)
  58
  59 int
  60 imx_dma_config_channel(int channel, unsigned int config_port,
  61         unsigned int config_mem, unsigned int dmareq, int hw_chaining);
  62
  63 void
  64 imx_dma_config_burstlen(int channel, unsigned int burstlen);
  65
  66 int
  67 imx_dma_setup_single(int channel, dma_addr_t dma_address,
  68                 unsigned int dma_length, unsigned int dev_addr,
  69                 unsigned int dmamode);
  70
  71
  72 /*
  73  * Use this flag as the dma_length argument to imx_dma_setup_sg()
  74  * to create an endless running dma loop. The end of the scatterlist
  75  * must be linked to the beginning for this to work.
  76  */
  77 #define IMX_DMA_LENGTH_LOOP     ((unsigned int)-1)
  78
  79 int
  80 imx_dma_setup_sg(int channel, struct scatterlist *sg,
  81                 unsigned int sgcount, unsigned int dma_length,
  82                 unsigned int dev_addr, unsigned int dmamode);
  83
  84 int
  85 imx_dma_setup_handlers(int channel,
  86                 void (*irq_handler) (int, void *),
  87                 void (*err_handler) (int, void *, int), void *data);
  88
  89 int
  90 imx_dma_setup_progression_handler(int channel,
  91                 void (*prog_handler) (int, void*, struct scatterlist*));
  92
  93 void imx_dma_enable(int channel);
  94
  95 void imx_dma_disable(int channel);
  96
  97 int imx_dma_request(int channel, const char *name);
  98
  99 void imx_dma_free(int channel);
 100
 101 int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
 102
 103 #endif  /* __MACH_DMA_V1_H__ */