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spi-topcliff-pch: Fix issue for transmitting over 4KByte
[zen-stable.git] / arch / arm / mach-imx / mach-pcm037.c
blobe48854b9d9907a7c76095b5531c3a9f63eb0db23
1 /*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/types.h>
16 #include <linux/init.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/platform_device.h>
19 #include <linux/mtd/physmap.h>
20 #include <linux/mtd/plat-ram.h>
21 #include <linux/memory.h>
22 #include <linux/gpio.h>
23 #include <linux/smsc911x.h>
24 #include <linux/interrupt.h>
25 #include <linux/i2c.h>
26 #include <linux/i2c/at24.h>
27 #include <linux/delay.h>
28 #include <linux/spi/spi.h>
29 #include <linux/irq.h>
30 #include <linux/can/platform/sja1000.h>
31 #include <linux/usb/otg.h>
32 #include <linux/usb/ulpi.h>
33 #include <linux/gfp.h>
34 #include <linux/memblock.h>
35
36 #include <media/soc_camera.h>
37
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
41 #include <asm/mach/map.h>
42 #include <asm/memblock.h>
43 #include <mach/common.h>
44 #include <mach/hardware.h>
45 #include <mach/iomux-mx3.h>
46 #include <mach/ulpi.h>
47
48 #include "devices-imx31.h"
49 #include "pcm037.h"
50
51 static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
52
53 static int __init pcm037_variant_setup(char *str)
54 {
55 if (!strcmp("eet", str))
56 pcm037_instance = PCM037_EET;
57 else if (strcmp("pcm970", str))
58 pr_warning("Unknown pcm037 baseboard variant %s\n", str);
59
60 return 1;
61 }
62
63 /* Supported values: "pcm970" (default) and "eet" */
64 __setup("pcm037_variant=", pcm037_variant_setup);
65
66 enum pcm037_board_variant pcm037_variant(void)
67 {
68 return pcm037_instance;
69 }
70
71 /* UART1 with RTS/CTS handshake signals */
72 static unsigned int pcm037_uart1_handshake_pins[] = {
73 MX31_PIN_CTS1__CTS1,
74 MX31_PIN_RTS1__RTS1,
75 MX31_PIN_TXD1__TXD1,
76 MX31_PIN_RXD1__RXD1,
77 };
78
79 /* UART1 without RTS/CTS handshake signals */
80 static unsigned int pcm037_uart1_pins[] = {
81 MX31_PIN_TXD1__TXD1,
82 MX31_PIN_RXD1__RXD1,
83 };
84
85 static unsigned int pcm037_pins[] = {
86 /* I2C */
87 MX31_PIN_CSPI2_MOSI__SCL,
88 MX31_PIN_CSPI2_MISO__SDA,
89 MX31_PIN_CSPI2_SS2__I2C3_SDA,
90 MX31_PIN_CSPI2_SCLK__I2C3_SCL,
91 /* SDHC1 */
92 MX31_PIN_SD1_DATA3__SD1_DATA3,
93 MX31_PIN_SD1_DATA2__SD1_DATA2,
94 MX31_PIN_SD1_DATA1__SD1_DATA1,
95 MX31_PIN_SD1_DATA0__SD1_DATA0,
96 MX31_PIN_SD1_CLK__SD1_CLK,
97 MX31_PIN_SD1_CMD__SD1_CMD,
98 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
99 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
100 /* SPI1 */
101 MX31_PIN_CSPI1_MOSI__MOSI,
102 MX31_PIN_CSPI1_MISO__MISO,
103 MX31_PIN_CSPI1_SCLK__SCLK,
104 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
105 MX31_PIN_CSPI1_SS0__SS0,
106 MX31_PIN_CSPI1_SS1__SS1,
107 MX31_PIN_CSPI1_SS2__SS2,
108 /* UART2 */
109 MX31_PIN_TXD2__TXD2,
110 MX31_PIN_RXD2__RXD2,
111 MX31_PIN_CTS2__CTS2,
112 MX31_PIN_RTS2__RTS2,
113 /* UART3 */
114 MX31_PIN_CSPI3_MOSI__RXD3,
115 MX31_PIN_CSPI3_MISO__TXD3,
116 MX31_PIN_CSPI3_SCLK__RTS3,
117 MX31_PIN_CSPI3_SPI_RDY__CTS3,
118 /* LAN9217 irq pin */
119 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
120 /* Onewire */
121 MX31_PIN_BATT_LINE__OWIRE,
122 /* Framebuffer */
123 MX31_PIN_LD0__LD0,
124 MX31_PIN_LD1__LD1,
125 MX31_PIN_LD2__LD2,
126 MX31_PIN_LD3__LD3,
127 MX31_PIN_LD4__LD4,
128 MX31_PIN_LD5__LD5,
129 MX31_PIN_LD6__LD6,
130 MX31_PIN_LD7__LD7,
131 MX31_PIN_LD8__LD8,
132 MX31_PIN_LD9__LD9,
133 MX31_PIN_LD10__LD10,
134 MX31_PIN_LD11__LD11,
135 MX31_PIN_LD12__LD12,
136 MX31_PIN_LD13__LD13,
137 MX31_PIN_LD14__LD14,
138 MX31_PIN_LD15__LD15,
139 MX31_PIN_LD16__LD16,
140 MX31_PIN_LD17__LD17,
141 MX31_PIN_VSYNC3__VSYNC3,
142 MX31_PIN_HSYNC__HSYNC,
143 MX31_PIN_FPSHIFT__FPSHIFT,
144 MX31_PIN_DRDY0__DRDY0,
145 MX31_PIN_D3_REV__D3_REV,
146 MX31_PIN_CONTRAST__CONTRAST,
147 MX31_PIN_D3_SPL__D3_SPL,
148 MX31_PIN_D3_CLS__D3_CLS,
149 MX31_PIN_LCS0__GPI03_23,
150 /* CSI */
151 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
152 MX31_PIN_CSI_D6__CSI_D6,
153 MX31_PIN_CSI_D7__CSI_D7,
154 MX31_PIN_CSI_D8__CSI_D8,
155 MX31_PIN_CSI_D9__CSI_D9,
156 MX31_PIN_CSI_D10__CSI_D10,
157 MX31_PIN_CSI_D11__CSI_D11,
158 MX31_PIN_CSI_D12__CSI_D12,
159 MX31_PIN_CSI_D13__CSI_D13,
160 MX31_PIN_CSI_D14__CSI_D14,
161 MX31_PIN_CSI_D15__CSI_D15,
162 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
163 MX31_PIN_CSI_MCLK__CSI_MCLK,
164 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
165 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
166 /* GPIO */
167 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
168 /* OTG */
169 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
170 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
171 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
172 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
173 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
174 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
175 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
176 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
177 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
178 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
179 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
180 MX31_PIN_USBOTG_STP__USBOTG_STP,
181 /* USB host 2 */
182 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
183 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
184 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
185 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
186 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
187 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
188 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
189 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
190 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
191 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
192 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
193 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
194 };
195
196 static struct physmap_flash_data pcm037_flash_data = {
197 .width = 2,
198 };
199
200 static struct resource pcm037_flash_resource = {
201 .start = 0xa0000000,
202 .end = 0xa1ffffff,
203 .flags = IORESOURCE_MEM,
204 };
205
206 static struct platform_device pcm037_flash = {
207 .name = "physmap-flash",
208 .id = 0,
209 .dev = {
210 .platform_data = &pcm037_flash_data,
211 },
212 .resource = &pcm037_flash_resource,
213 .num_resources = 1,
214 };
215
216 static const struct imxuart_platform_data uart_pdata __initconst = {
217 .flags = IMXUART_HAVE_RTSCTS,
218 };
219
220 static struct resource smsc911x_resources[] = {
221 {
222 .start = MX31_CS1_BASE_ADDR + 0x300,
223 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
224 .flags = IORESOURCE_MEM,
225 }, {
226 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
227 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
228 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
229 },
230 };
231
232 static struct smsc911x_platform_config smsc911x_info = {
233 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
234 SMSC911X_SAVE_MAC_ADDRESS,
235 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
236 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
237 .phy_interface = PHY_INTERFACE_MODE_MII,
238 };
239
240 static struct platform_device pcm037_eth = {
241 .name = "smsc911x",
242 .id = -1,
243 .num_resources = ARRAY_SIZE(smsc911x_resources),
244 .resource = smsc911x_resources,
245 .dev = {
246 .platform_data = &smsc911x_info,
247 },
248 };
249
250 static struct platdata_mtd_ram pcm038_sram_data = {
251 .bankwidth = 2,
252 };
253
254 static struct resource pcm038_sram_resource = {
255 .start = MX31_CS4_BASE_ADDR,
256 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
257 .flags = IORESOURCE_MEM,
258 };
259
260 static struct platform_device pcm037_sram_device = {
261 .name = "mtd-ram",
262 .id = 0,
263 .dev = {
264 .platform_data = &pcm038_sram_data,
265 },
266 .num_resources = 1,
267 .resource = &pcm038_sram_resource,
268 };
269
270 static const struct mxc_nand_platform_data
271 pcm037_nand_board_info __initconst = {
272 .width = 1,
273 .hw_ecc = 1,
274 };
275
276 static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
277 .bitrate = 100000,
278 };
279
280 static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
281 .bitrate = 20000,
282 };
283
284 static struct at24_platform_data board_eeprom = {
285 .byte_len = 4096,
286 .page_size = 32,
287 .flags = AT24_FLAG_ADDR16,
288 };
289
290 static int pcm037_camera_power(struct device *dev, int on)
291 {
292 /* disable or enable the camera in X7 or X8 PCM970 connector */
293 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
294 return 0;
295 }
296
297 static struct i2c_board_info pcm037_i2c_camera[] = {
298 {
299 I2C_BOARD_INFO("mt9t031", 0x5d),
300 }, {
301 I2C_BOARD_INFO("mt9v022", 0x48),
302 },
303 };
304
305 static struct soc_camera_link iclink_mt9v022 = {
306 .bus_id = 0, /* Must match with the camera ID */
307 .board_info = &pcm037_i2c_camera[1],
308 .i2c_adapter_id = 2,
309 };
310
311 static struct soc_camera_link iclink_mt9t031 = {
312 .bus_id = 0, /* Must match with the camera ID */
313 .power = pcm037_camera_power,
314 .board_info = &pcm037_i2c_camera[0],
315 .i2c_adapter_id = 2,
316 };
317
318 static struct i2c_board_info pcm037_i2c_devices[] = {
319 {
320 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
321 .platform_data = &board_eeprom,
322 }, {
323 I2C_BOARD_INFO("pcf8563", 0x51),
324 }
325 };
326
327 static struct platform_device pcm037_mt9t031 = {
328 .name = "soc-camera-pdrv",
329 .id = 0,
330 .dev = {
331 .platform_data = &iclink_mt9t031,
332 },
333 };
334
335 static struct platform_device pcm037_mt9v022 = {
336 .name = "soc-camera-pdrv",
337 .id = 1,
338 .dev = {
339 .platform_data = &iclink_mt9v022,
340 },
341 };
342
343 /* Not connected by default */
344 #ifdef PCM970_SDHC_RW_SWITCH
345 static int pcm970_sdhc1_get_ro(struct device *dev)
346 {
347 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
348 }
349 #endif
350
351 #define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
352 #define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
353
354 static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
355 void *data)
356 {
357 int ret;
358
359 ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
360 if (ret)
361 return ret;
362
363 gpio_direction_input(SDHC1_GPIO_DET);
364
365 #ifdef PCM970_SDHC_RW_SWITCH
366 ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
367 if (ret)
368 goto err_gpio_free;
369 gpio_direction_input(SDHC1_GPIO_WP);
370 #endif
371
372 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
373 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
374 "sdhc-detect", data);
375 if (ret)
376 goto err_gpio_free_2;
377
378 return 0;
379
380 err_gpio_free_2:
381 #ifdef PCM970_SDHC_RW_SWITCH
382 gpio_free(SDHC1_GPIO_WP);
383 err_gpio_free:
384 #endif
385 gpio_free(SDHC1_GPIO_DET);
386
387 return ret;
388 }
389
390 static void pcm970_sdhc1_exit(struct device *dev, void *data)
391 {
392 free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
393 gpio_free(SDHC1_GPIO_DET);
394 gpio_free(SDHC1_GPIO_WP);
395 }
396
397 static const struct imxmmc_platform_data sdhc_pdata __initconst = {
398 #ifdef PCM970_SDHC_RW_SWITCH
399 .get_ro = pcm970_sdhc1_get_ro,
400 #endif
401 .init = pcm970_sdhc1_init,
402 .exit = pcm970_sdhc1_exit,
403 };
404
405 struct mx3_camera_pdata camera_pdata __initdata = {
406 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
407 .mclk_10khz = 2000,
408 };
409
410 static phys_addr_t mx3_camera_base __initdata;
411 #define MX3_CAMERA_BUF_SIZE SZ_4M
412
413 static int __init pcm037_init_camera(void)
414 {
415 int dma, ret = -ENOMEM;
416 struct platform_device *pdev = imx31_alloc_mx3_camera(&camera_pdata);
417
418 if (IS_ERR(pdev))
419 return PTR_ERR(pdev);
420
421 dma = dma_declare_coherent_memory(&pdev->dev,
422 mx3_camera_base, mx3_camera_base,
423 MX3_CAMERA_BUF_SIZE,
424 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
425 if (!(dma & DMA_MEMORY_MAP))
426 goto err;
427
428 ret = platform_device_add(pdev);
429 if (ret)
430 err:
431 platform_device_put(pdev);
432
433 return ret;
434 }
435
436 static struct platform_device *devices[] __initdata = {
437 &pcm037_flash,
438 &pcm037_sram_device,
439 &pcm037_mt9t031,
440 &pcm037_mt9v022,
441 };
442
443 static const struct ipu_platform_data mx3_ipu_data __initconst = {
444 .irq_base = MXC_IPU_IRQ_START,
445 };
446
447 static const struct fb_videomode fb_modedb[] = {
448 {
449 /* 240x320 @ 60 Hz Sharp */
450 .name = "Sharp-LQ035Q7DH06-QVGA",
451 .refresh = 60,
452 .xres = 240,
453 .yres = 320,
454 .pixclock = 185925,
455 .left_margin = 9,
456 .right_margin = 16,
457 .upper_margin = 7,
458 .lower_margin = 9,
459 .hsync_len = 1,
460 .vsync_len = 1,
461 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
462 FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
463 .vmode = FB_VMODE_NONINTERLACED,
464 .flag = 0,
465 }, {
466 /* 240x320 @ 60 Hz */
467 .name = "TX090",
468 .refresh = 60,
469 .xres = 240,
470 .yres = 320,
471 .pixclock = 38255,
472 .left_margin = 144,
473 .right_margin = 0,
474 .upper_margin = 7,
475 .lower_margin = 40,
476 .hsync_len = 96,
477 .vsync_len = 1,
478 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
479 .vmode = FB_VMODE_NONINTERLACED,
480 .flag = 0,
481 }, {
482 /* 240x320 @ 60 Hz */
483 .name = "CMEL-OLED",
484 .refresh = 60,
485 .xres = 240,
486 .yres = 320,
487 .pixclock = 185925,
488 .left_margin = 9,
489 .right_margin = 16,
490 .upper_margin = 7,
491 .lower_margin = 9,
492 .hsync_len = 1,
493 .vsync_len = 1,
494 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
495 .vmode = FB_VMODE_NONINTERLACED,
496 .flag = 0,
497 },
498 };
499
500 static struct mx3fb_platform_data mx3fb_pdata = {
501 .name = "Sharp-LQ035Q7DH06-QVGA",
502 .mode = fb_modedb,
503 .num_modes = ARRAY_SIZE(fb_modedb),
504 };
505
506 static struct resource pcm970_sja1000_resources[] = {
507 {
508 .start = MX31_CS5_BASE_ADDR,
509 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
510 .flags = IORESOURCE_MEM,
511 }, {
512 .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
513 .end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
514 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
515 },
516 };
517
518 struct sja1000_platform_data pcm970_sja1000_platform_data = {
519 .osc_freq = 16000000,
520 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
521 .cdr = CDR_CBP,
522 };
523
524 static struct platform_device pcm970_sja1000 = {
525 .name = "sja1000_platform",
526 .dev = {
527 .platform_data = &pcm970_sja1000_platform_data,
528 },
529 .resource = pcm970_sja1000_resources,
530 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
531 };
532
533 static int pcm037_otg_init(struct platform_device *pdev)
534 {
535 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
536 }
537
538 static struct mxc_usbh_platform_data otg_pdata __initdata = {
539 .init = pcm037_otg_init,
540 .portsc = MXC_EHCI_MODE_ULPI,
541 };
542
543 static int pcm037_usbh2_init(struct platform_device *pdev)
544 {
545 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
546 }
547
548 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
549 .init = pcm037_usbh2_init,
550 .portsc = MXC_EHCI_MODE_ULPI,
551 };
552
553 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
554 .operating_mode = FSL_USB2_DR_DEVICE,
555 .phy_mode = FSL_USB2_PHY_ULPI,
556 };
557
558 static int otg_mode_host;
559
560 static int __init pcm037_otg_mode(char *options)
561 {
562 if (!strcmp(options, "host"))
563 otg_mode_host = 1;
564 else if (!strcmp(options, "device"))
565 otg_mode_host = 0;
566 else
567 pr_info("otg_mode neither \"host\" nor \"device\". "
568 "Defaulting to device\n");
569 return 0;
570 }
571 __setup("otg_mode=", pcm037_otg_mode);
572
573 /*
574 * Board specific initialization.
575 */
576 static void __init pcm037_init(void)
577 {
578 int ret;
579
580 imx31_soc_init();
581
582 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
583
584 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
585 "pcm037");
586
587 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
588 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
589
590 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
591 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
592 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
593 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
594 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
595 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
596 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
597 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
598 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
599 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
600 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
601 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
602
603 if (pcm037_variant() == PCM037_EET)
604 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
605 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
606 else
607 mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
608 ARRAY_SIZE(pcm037_uart1_handshake_pins),
609 "pcm037_uart1");
610
611 platform_add_devices(devices, ARRAY_SIZE(devices));
612
613 imx31_add_imx2_wdt(NULL);
614 imx31_add_imx_uart0(&uart_pdata);
615 /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
616 imx31_add_imx_uart1(&uart_pdata);
617 imx31_add_imx_uart2(&uart_pdata);
618
619 imx31_add_mxc_w1(NULL);
620
621 /* LAN9217 IRQ pin */
622 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
623 if (ret)
624 pr_warning("could not get LAN irq gpio\n");
625 else {
626 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
627 platform_device_register(&pcm037_eth);
628 }
629
630
631 /* I2C adapters and devices */
632 i2c_register_board_info(1, pcm037_i2c_devices,
633 ARRAY_SIZE(pcm037_i2c_devices));
634
635 imx31_add_imx_i2c1(&pcm037_i2c1_data);
636 imx31_add_imx_i2c2(&pcm037_i2c2_data);
637
638 imx31_add_mxc_nand(&pcm037_nand_board_info);
639 imx31_add_mxc_mmc(0, &sdhc_pdata);
640 imx31_add_ipu_core(&mx3_ipu_data);
641 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
642
643 /* CSI */
644 /* Camera power: default - off */
645 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
646 if (!ret)
647 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
648 else
649 iclink_mt9t031.power = NULL;
650
651 pcm037_init_camera();
652
653 platform_device_register(&pcm970_sja1000);
654
655 if (otg_mode_host) {
656 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
657 ULPI_OTG_DRVVBUS_EXT);
658 if (otg_pdata.otg)
659 imx31_add_mxc_ehci_otg(&otg_pdata);
660 }
661
662 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
663 ULPI_OTG_DRVVBUS_EXT);
664 if (usbh2_pdata.otg)
665 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
666
667 if (!otg_mode_host)
668 imx31_add_fsl_usb2_udc(&otg_device_pdata);
669
670 }
671
672 static void __init pcm037_timer_init(void)
673 {
674 mx31_clocks_init(26000000);
675 }
676
677 struct sys_timer pcm037_timer = {
678 .init = pcm037_timer_init,
679 };
680
681 static void __init pcm037_reserve(void)
682 {
683 /* reserve 4 MiB for mx3-camera */
684 mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE,
685 MX3_CAMERA_BUF_SIZE);
686 }
687
688 MACHINE_START(PCM037, "Phytec Phycore pcm037")
689 /* Maintainer: Pengutronix */
690 .atag_offset = 0x100,
691 .reserve = pcm037_reserve,
692 .map_io = mx31_map_io,
693 .init_early = imx31_init_early,
694 .init_irq = mx31_init_irq,
695 .handle_irq = imx31_handle_irq,
696 .timer = &pcm037_timer,
697 .init_machine = pcm037_init,
698 .restart = mxc_restart,
699 MACHINE_END