arch/arm/mach-iop13xx/include/mach/iop13xx.h

   1 #ifndef _IOP13XX_HW_H_
   2 #define _IOP13XX_HW_H_
   3
   4 #ifndef __ASSEMBLY__
   5 /* The ATU offsets can change based on the strapping */
   6 extern u32 iop13xx_atux_pmmr_offset;
   7 extern u32 iop13xx_atue_pmmr_offset;
   8 void iop13xx_init_irq(void);
   9 void iop13xx_map_io(void);
  10 void iop13xx_platform_init(void);
  11 void iop13xx_add_tpmi_devices(void);
  12 void iop13xx_init_irq(void);
  13 void iop13xx_restart(char, const char *);
  14
  15 /* CPUID CP6 R0 Page 0 */
  16 static inline int iop13xx_cpu_id(void)
  17 {
  18         int id;
  19         asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
  20         return id;
  21 }
  22
  23 /* WDTCR CP6 R7 Page 9 */
  24 static inline u32 read_wdtcr(void)
  25 {
  26         u32 val;
  27         asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
  28         return val;
  29 }
  30 static inline void write_wdtcr(u32 val)
  31 {
  32         asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
  33 }
  34
  35 /* WDTSR CP6 R8 Page 9 */
  36 static inline u32 read_wdtsr(void)
  37 {
  38         u32 val;
  39         asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
  40         return val;
  41 }
  42 static inline void write_wdtsr(u32 val)
  43 {
  44         asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
  45 }
  46
  47 /* RCSR - Reset Cause Status Register  */
  48 static inline u32 read_rcsr(void)
  49 {
  50         u32 val;
  51         asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
  52         return val;
  53 }
  54
  55 extern unsigned long get_iop_tick_rate(void);
  56 #endif
  57
  58 /*
  59  * IOP13XX I/O and Mem space regions for PCI autoconfiguration
  60  */
  61 #define IOP13XX_MAX_RAM_SIZE    0x80000000UL  /* 2GB */
  62 #define IOP13XX_PCI_OFFSET       IOP13XX_MAX_RAM_SIZE
  63
  64 /* PCI MAP
  65  * bus range            cpu phys        cpu virt        note
  66  * 0x0000.0000 + 2GB    (n/a)           (n/a)           inbound, 1:1 mapping with Physical RAM
  67  * 0x8000.0000 + 928M   0x1.8000.0000   (ioremap)       PCIX outbound memory window
  68  * 0x8000.0000 + 928M   0x2.8000.0000   (ioremap)       PCIE outbound memory window
  69  *
  70  * IO MAP
  71  * 0x1000 + 64K 0x0.fffb.1000   0xfec6.1000     PCIX outbound i/o window
  72  * 0x1000 + 64K 0x0.fffd.1000   0xfed7.1000     PCIE outbound i/o window
  73  */
  74 #define IOP13XX_PCIX_IO_WINDOW_SIZE   0x10000UL
  75 #define IOP13XX_PCIX_LOWER_IO_PA      0xfffb0000UL
  76 #define IOP13XX_PCIX_LOWER_IO_VA      0xfec60000UL
  77 #define IOP13XX_PCIX_LOWER_IO_BA      0x0UL /* OIOTVR */
  78 #define IOP13XX_PCIX_IO_BUS_OFFSET    0x1000UL
  79 #define IOP13XX_PCIX_UPPER_IO_PA      (IOP13XX_PCIX_LOWER_IO_PA +\
  80                                        IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
  81 #define IOP13XX_PCIX_UPPER_IO_VA      (IOP13XX_PCIX_LOWER_IO_VA +\
  82                                        IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
  83 #define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
  84                                            (IOP13XX_PCIX_LOWER_IO_PA\
  85                                            - IOP13XX_PCIX_LOWER_IO_VA))
  86
  87 #define IOP13XX_PCIX_MEM_PHYS_OFFSET  0x100000000ULL
  88 #define IOP13XX_PCIX_MEM_WINDOW_SIZE  0x3a000000UL
  89 #define IOP13XX_PCIX_LOWER_MEM_BA     (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
  90 #define IOP13XX_PCIX_LOWER_MEM_PA     (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
  91                                        IOP13XX_PCIX_LOWER_MEM_BA)
  92 #define IOP13XX_PCIX_UPPER_MEM_PA     (IOP13XX_PCIX_LOWER_MEM_PA +\
  93                                        IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
  94 #define IOP13XX_PCIX_UPPER_MEM_BA     (IOP13XX_PCIX_LOWER_MEM_BA +\
  95                                        IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
  96
  97 #define IOP13XX_PCIX_MEM_COOKIE        0x80000000UL
  98 #define IOP13XX_PCIX_LOWER_MEM_RA      IOP13XX_PCIX_MEM_COOKIE
  99 #define IOP13XX_PCIX_UPPER_MEM_RA      (IOP13XX_PCIX_LOWER_MEM_RA +\
 100                                         IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
 101 #define IOP13XX_PCIX_MEM_OFFSET        (IOP13XX_PCIX_MEM_COOKIE -\
 102                                         IOP13XX_PCIX_LOWER_MEM_BA)
 103
 104 /* PCI-E ranges */
 105 #define IOP13XX_PCIE_IO_WINDOW_SIZE      0x10000UL
 106 #define IOP13XX_PCIE_LOWER_IO_PA         0xfffd0000UL
 107 #define IOP13XX_PCIE_LOWER_IO_VA         0xfed70000UL
 108 #define IOP13XX_PCIE_LOWER_IO_BA         0x0UL  /* OIOTVR */
 109 #define IOP13XX_PCIE_IO_BUS_OFFSET       0x1000UL
 110 #define IOP13XX_PCIE_UPPER_IO_PA         (IOP13XX_PCIE_LOWER_IO_PA +\
 111                                          IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
 112 #define IOP13XX_PCIE_UPPER_IO_VA         (IOP13XX_PCIE_LOWER_IO_VA +\
 113                                          IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
 114 #define IOP13XX_PCIE_UPPER_IO_BA         (IOP13XX_PCIE_LOWER_IO_BA +\
 115                                          IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
 116 #define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
 117                                            (IOP13XX_PCIE_LOWER_IO_PA\
 118                                            - IOP13XX_PCIE_LOWER_IO_VA))
 119
 120 #define IOP13XX_PCIE_MEM_PHYS_OFFSET     0x200000000ULL
 121 #define IOP13XX_PCIE_MEM_WINDOW_SIZE     0x3a000000UL
 122 #define IOP13XX_PCIE_LOWER_MEM_BA        (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
 123 #define IOP13XX_PCIE_LOWER_MEM_PA        (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
 124                                          IOP13XX_PCIE_LOWER_MEM_BA)
 125 #define IOP13XX_PCIE_UPPER_MEM_PA        (IOP13XX_PCIE_LOWER_MEM_PA +\
 126                                          IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
 127 #define IOP13XX_PCIE_UPPER_MEM_BA        (IOP13XX_PCIE_LOWER_MEM_BA +\
 128                                          IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
 129
 130 /* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
 131 #define IOP13XX_PCIE_MEM_COOKIE          0xc0000000UL
 132 #define IOP13XX_PCIE_LOWER_MEM_RA        IOP13XX_PCIE_MEM_COOKIE
 133 #define IOP13XX_PCIE_UPPER_MEM_RA        (IOP13XX_PCIE_LOWER_MEM_RA +\
 134                                          IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
 135 #define IOP13XX_PCIE_MEM_OFFSET          (IOP13XX_PCIE_MEM_COOKIE -\
 136                                          IOP13XX_PCIE_LOWER_MEM_BA)
 137
 138 /* PBI Ranges */
 139 #define IOP13XX_PBI_LOWER_MEM_PA          0xf0000000UL
 140 #define IOP13XX_PBI_MEM_WINDOW_SIZE       0x04000000UL
 141 #define IOP13XX_PBI_MEM_COOKIE            0xfa000000UL
 142 #define IOP13XX_PBI_LOWER_MEM_RA          IOP13XX_PBI_MEM_COOKIE
 143 #define IOP13XX_PBI_UPPER_MEM_RA          (IOP13XX_PBI_LOWER_MEM_RA +\
 144                                           IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
 145
 146 /*
 147  * IOP13XX chipset registers
 148  */
 149 #define IOP13XX_PMMR_PHYS_MEM_BASE         0xffd80000UL  /* PMMR phys. address */
 150 #define IOP13XX_PMMR_VIRT_MEM_BASE         0xfee80000UL  /* PMMR phys. address */
 151 #define IOP13XX_PMMR_MEM_WINDOW_SIZE       0x80000
 152 #define IOP13XX_PMMR_UPPER_MEM_VA          (IOP13XX_PMMR_VIRT_MEM_BASE +\
 153                                            IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
 154 #define IOP13XX_PMMR_UPPER_MEM_PA          (IOP13XX_PMMR_PHYS_MEM_BASE +\
 155                                            IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
 156 #define IOP13XX_PMMR_VIRT_TO_PHYS(addr)   (u32) ((u32) addr +\
 157                                            (IOP13XX_PMMR_PHYS_MEM_BASE\
 158                                            - IOP13XX_PMMR_VIRT_MEM_BASE))
 159 #define IOP13XX_PMMR_PHYS_TO_VIRT(addr)   (u32) ((u32) addr -\
 160                                            (IOP13XX_PMMR_PHYS_MEM_BASE\
 161                                            - IOP13XX_PMMR_VIRT_MEM_BASE))
 162 #define IOP13XX_REG_ADDR32(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 163 #define IOP13XX_REG_ADDR16(reg)            (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 164 #define IOP13XX_REG_ADDR8(reg)             (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
 165 #define IOP13XX_REG_ADDR32_PHYS(reg)      (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
 166 #define IOP13XX_REG_ADDR16_PHYS(reg)      (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
 167 #define IOP13XX_REG_ADDR8_PHYS(reg)       (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
 168 #define IOP13XX_PMMR_SIZE                  0x00080000
 169
 170 /*=================== Defines for Platform Devices =====================*/
 171 #define IOP13XX_UART0_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
 172 #define IOP13XX_UART1_PHYS  (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
 173 #define IOP13XX_UART0_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
 174 #define IOP13XX_UART1_VIRT  (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
 175
 176 #define IOP13XX_I2C0_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
 177 #define IOP13XX_I2C1_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
 178 #define IOP13XX_I2C2_PHYS   (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
 179 #define IOP13XX_I2C0_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
 180 #define IOP13XX_I2C1_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
 181 #define IOP13XX_I2C2_VIRT   (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
 182
 183 /* ATU selection flags */
 184 /* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
 185 #define IOP13XX_INIT_ATU_DEFAULT     (0)
 186 #define IOP13XX_INIT_ATU_ATUX         (1 << 0)
 187 #define IOP13XX_INIT_ATU_ATUE         (1 << 1)
 188 #define IOP13XX_INIT_ATU_NONE         (1 << 2)
 189
 190 /* UART selection flags */
 191 /* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
 192 #define IOP13XX_INIT_UART_DEFAULT    (0)
 193 #define IOP13XX_INIT_UART_0           (1 << 0)
 194 #define IOP13XX_INIT_UART_1           (1 << 1)
 195
 196 /* I2C selection flags */
 197 /* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
 198 #define IOP13XX_INIT_I2C_DEFAULT     (0)
 199 #define IOP13XX_INIT_I2C_0            (1 << 0)
 200 #define IOP13XX_INIT_I2C_1            (1 << 1)
 201 #define IOP13XX_INIT_I2C_2            (1 << 2)
 202
 203 /* ADMA selection flags */
 204 /* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */
 205 #define IOP13XX_INIT_ADMA_DEFAULT     (0)
 206 #define IOP13XX_INIT_ADMA_0           (1 << 0)
 207 #define IOP13XX_INIT_ADMA_1           (1 << 1)
 208 #define IOP13XX_INIT_ADMA_2           (1 << 2)
 209
 210 /* Platform devices */
 211 #define IQ81340_NUM_UART                2
 212 #define IQ81340_NUM_I2C                 3
 213 #define IQ81340_NUM_PHYS_MAP_FLASH      1
 214 #define IQ81340_NUM_ADMA                3
 215 #define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \
 216                                 IQ81340_NUM_I2C + \
 217                                 IQ81340_NUM_PHYS_MAP_FLASH + \
 218                                 IQ81340_NUM_ADMA)
 219
 220 /*========================== PMMR offsets for key registers ============*/
 221 #define IOP13XX_ATU0_PMMR_OFFSET        0x00048000
 222 #define IOP13XX_ATU1_PMMR_OFFSET        0x0004c000
 223 #define IOP13XX_ATU2_PMMR_OFFSET        0x0004d000
 224 #define IOP13XX_ADMA0_PMMR_OFFSET       0x00000000
 225 #define IOP13XX_ADMA1_PMMR_OFFSET       0x00000200
 226 #define IOP13XX_ADMA2_PMMR_OFFSET       0x00000400
 227 #define IOP13XX_PBI_PMMR_OFFSET         0x00001580
 228 #define IOP13XX_MU_PMMR_OFFSET          0x00004000
 229 #define IOP13XX_ESSR0_PMMR_OFFSET       0x00002188
 230 #define IOP13XX_ESSR0                   IOP13XX_REG_ADDR32(0x00002188)
 231
 232 #define IOP13XX_ESSR0_IFACE_MASK        0x00004000  /* Interface PCI-X / PCI-E */
 233 #define IOP13XX_CONTROLLER_ONLY         (1 << 14)
 234 #define IOP13XX_INTERFACE_SEL_PCIX      (1 << 15)
 235
 236 #define IOP13XX_PMON_PMMR_OFFSET        0x0001A000
 237 #define IOP13XX_PMON_BASE               (IOP13XX_PMMR_VIRT_MEM_BASE +\
 238                                         IOP13XX_PMON_PMMR_OFFSET)
 239 #define IOP13XX_PMON_PHYSBASE           (IOP13XX_PMMR_PHYS_MEM_BASE +\
 240                                         IOP13XX_PMON_PMMR_OFFSET)
 241
 242 #define IOP13XX_PMON_CMD0               (IOP13XX_PMON_BASE + 0x0)
 243 #define IOP13XX_PMON_EVR0               (IOP13XX_PMON_BASE + 0x4)
 244 #define IOP13XX_PMON_STS0               (IOP13XX_PMON_BASE + 0x8)
 245 #define IOP13XX_PMON_DATA0              (IOP13XX_PMON_BASE + 0xC)
 246
 247 #define IOP13XX_PMON_CMD3               (IOP13XX_PMON_BASE + 0x30)
 248 #define IOP13XX_PMON_EVR3               (IOP13XX_PMON_BASE + 0x34)
 249 #define IOP13XX_PMON_STS3               (IOP13XX_PMON_BASE + 0x38)
 250 #define IOP13XX_PMON_DATA3              (IOP13XX_PMON_BASE + 0x3C)
 251
 252 #define IOP13XX_PMON_CMD7               (IOP13XX_PMON_BASE + 0x70)
 253 #define IOP13XX_PMON_EVR7               (IOP13XX_PMON_BASE + 0x74)
 254 #define IOP13XX_PMON_STS7               (IOP13XX_PMON_BASE + 0x78)
 255 #define IOP13XX_PMON_DATA7              (IOP13XX_PMON_BASE + 0x7C)
 256
 257 #define IOP13XX_PMONEN                  (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
 258 #define IOP13XX_PMONSTAT                (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
 259
 260 /*================================ATU===================================*/
 261 #define IOP13XX_ATUX_OFFSET(ofs)        IOP13XX_REG_ADDR32(\
 262                                         iop13xx_atux_pmmr_offset + (ofs))
 263
 264 #define IOP13XX_ATUX_DID                IOP13XX_REG_ADDR16(\
 265                                         iop13xx_atux_pmmr_offset + 0x2)
 266
 267 #define IOP13XX_ATUX_ATUCMD             IOP13XX_REG_ADDR16(\
 268                                         iop13xx_atux_pmmr_offset + 0x4)
 269 #define IOP13XX_ATUX_ATUSR              IOP13XX_REG_ADDR16(\
 270                                         iop13xx_atux_pmmr_offset + 0x6)
 271
 272 #define IOP13XX_ATUX_IABAR0             IOP13XX_ATUX_OFFSET(0x10)
 273 #define IOP13XX_ATUX_IAUBAR0            IOP13XX_ATUX_OFFSET(0x14)
 274 #define IOP13XX_ATUX_IABAR1             IOP13XX_ATUX_OFFSET(0x18)
 275 #define IOP13XX_ATUX_IAUBAR1            IOP13XX_ATUX_OFFSET(0x1c)
 276 #define IOP13XX_ATUX_IABAR2             IOP13XX_ATUX_OFFSET(0x20)
 277 #define IOP13XX_ATUX_IAUBAR2            IOP13XX_ATUX_OFFSET(0x24)
 278 #define IOP13XX_ATUX_IALR0              IOP13XX_ATUX_OFFSET(0x40)
 279 #define IOP13XX_ATUX_IATVR0             IOP13XX_ATUX_OFFSET(0x44)
 280 #define IOP13XX_ATUX_IAUTVR0            IOP13XX_ATUX_OFFSET(0x48)
 281 #define IOP13XX_ATUX_IALR1              IOP13XX_ATUX_OFFSET(0x4c)
 282 #define IOP13XX_ATUX_IATVR1             IOP13XX_ATUX_OFFSET(0x50)
 283 #define IOP13XX_ATUX_IAUTVR1            IOP13XX_ATUX_OFFSET(0x54)
 284 #define IOP13XX_ATUX_IALR2              IOP13XX_ATUX_OFFSET(0x58)
 285 #define IOP13XX_ATUX_IATVR2             IOP13XX_ATUX_OFFSET(0x5c)
 286 #define IOP13XX_ATUX_IAUTVR2            IOP13XX_ATUX_OFFSET(0x60)
 287 #define IOP13XX_ATUX_ATUCR              IOP13XX_ATUX_OFFSET(0x70)
 288 #define IOP13XX_ATUX_PCSR               IOP13XX_ATUX_OFFSET(0x74)
 289 #define IOP13XX_ATUX_ATUISR             IOP13XX_ATUX_OFFSET(0x78)
 290 #define IOP13XX_ATUX_PCIXSR             IOP13XX_ATUX_OFFSET(0xD4)
 291 #define IOP13XX_ATUX_IABAR3             IOP13XX_ATUX_OFFSET(0x200)
 292 #define IOP13XX_ATUX_IAUBAR3            IOP13XX_ATUX_OFFSET(0x204)
 293 #define IOP13XX_ATUX_IALR3              IOP13XX_ATUX_OFFSET(0x208)
 294 #define IOP13XX_ATUX_IATVR3             IOP13XX_ATUX_OFFSET(0x20c)
 295 #define IOP13XX_ATUX_IAUTVR3            IOP13XX_ATUX_OFFSET(0x210)
 296
 297 #define IOP13XX_ATUX_OIOBAR             IOP13XX_ATUX_OFFSET(0x300)
 298 #define IOP13XX_ATUX_OIOWTVR            IOP13XX_ATUX_OFFSET(0x304)
 299 #define IOP13XX_ATUX_OUMBAR0            IOP13XX_ATUX_OFFSET(0x308)
 300 #define IOP13XX_ATUX_OUMWTVR0           IOP13XX_ATUX_OFFSET(0x30c)
 301 #define IOP13XX_ATUX_OUMBAR1            IOP13XX_ATUX_OFFSET(0x310)
 302 #define IOP13XX_ATUX_OUMWTVR1           IOP13XX_ATUX_OFFSET(0x314)
 303 #define IOP13XX_ATUX_OUMBAR2            IOP13XX_ATUX_OFFSET(0x318)
 304 #define IOP13XX_ATUX_OUMWTVR2           IOP13XX_ATUX_OFFSET(0x31c)
 305 #define IOP13XX_ATUX_OUMBAR3            IOP13XX_ATUX_OFFSET(0x320)
 306 #define IOP13XX_ATUX_OUMWTVR3           IOP13XX_ATUX_OFFSET(0x324)
 307 #define IOP13XX_ATUX_OUDMABAR           IOP13XX_ATUX_OFFSET(0x328)
 308 #define IOP13XX_ATUX_OUMSIBAR           IOP13XX_ATUX_OFFSET(0x32c)
 309 #define IOP13XX_ATUX_OCCAR              IOP13XX_ATUX_OFFSET(0x330)
 310 #define IOP13XX_ATUX_OCCDR              IOP13XX_ATUX_OFFSET(0x334)
 311
 312 #define IOP13XX_ATUX_ATUCR_OUT_EN               (1 << 1)
 313 #define IOP13XX_ATUX_PCSR_CENTRAL_RES           (1 << 25)
 314 #define IOP13XX_ATUX_PCSR_P_RSTOUT              (1 << 21)
 315 #define IOP13XX_ATUX_PCSR_OUT_Q_BUSY            (1 << 15)
 316 #define IOP13XX_ATUX_PCSR_IN_Q_BUSY             (1 << 14)
 317 #define IOP13XX_ATUX_PCSR_FREQ_OFFSET           (16)
 318
 319 #define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
 320 #define IOP13XX_ATUX_STAT_VPD_ADDR              (1 << 17)
 321 #define IOP13XX_ATUX_STAT_INT_PAR_ERR           (1 << 16)
 322 #define IOP13XX_ATUX_STAT_CFG_WRITE             (1 << 15)
 323 #define IOP13XX_ATUX_STAT_ERR_COR               (1 << 14)
 324 #define IOP13XX_ATUX_STAT_TX_SCEM               (1 << 13)
 325 #define IOP13XX_ATUX_STAT_REC_SCEM              (1 << 12)
 326 #define IOP13XX_ATUX_STAT_POWER_TRAN            (1 << 11)
 327 #define IOP13XX_ATUX_STAT_TX_SERR               (1 << 10)
 328 #define IOP13XX_ATUX_STAT_DET_PAR_ERR           (1 << 9 )
 329 #define IOP13XX_ATUX_STAT_BIST                  (1 << 8 )
 330 #define IOP13XX_ATUX_STAT_INT_REC_MABORT        (1 << 7 )
 331 #define IOP13XX_ATUX_STAT_REC_SERR              (1 << 4 )
 332 #define IOP13XX_ATUX_STAT_EXT_REC_MABORT        (1 << 3 )
 333 #define IOP13XX_ATUX_STAT_EXT_REC_TABORT        (1 << 2 )
 334 #define IOP13XX_ATUX_STAT_EXT_SIG_TABORT        (1 << 1 )
 335 #define IOP13XX_ATUX_STAT_MASTER_DATA_PAR       (1 << 0 )
 336
 337 #define IOP13XX_ATUX_PCIXSR_BUS_NUM     (8)
 338 #define IOP13XX_ATUX_PCIXSR_DEV_NUM     (3)
 339 #define IOP13XX_ATUX_PCIXSR_FUNC_NUM    (0)
 340
 341 #define IOP13XX_ATUX_IALR_DISABLE       0x00000001
 342 #define IOP13XX_ATUX_OUMBAR_ENABLE      0x80000000
 343
 344 #define IOP13XX_ATUE_OFFSET(ofs)        IOP13XX_REG_ADDR32(\
 345                                         iop13xx_atue_pmmr_offset + (ofs))
 346
 347 #define IOP13XX_ATUE_DID                IOP13XX_REG_ADDR16(\
 348                                         iop13xx_atue_pmmr_offset + 0x2)
 349 #define IOP13XX_ATUE_ATUCMD             IOP13XX_REG_ADDR16(\
 350                                         iop13xx_atue_pmmr_offset + 0x4)
 351 #define IOP13XX_ATUE_ATUSR              IOP13XX_REG_ADDR16(\
 352                                         iop13xx_atue_pmmr_offset + 0x6)
 353
 354 #define IOP13XX_ATUE_IABAR0             IOP13XX_ATUE_OFFSET(0x10)
 355 #define IOP13XX_ATUE_IAUBAR0            IOP13XX_ATUE_OFFSET(0x14)
 356 #define IOP13XX_ATUE_IABAR1             IOP13XX_ATUE_OFFSET(0x18)
 357 #define IOP13XX_ATUE_IAUBAR1            IOP13XX_ATUE_OFFSET(0x1c)
 358 #define IOP13XX_ATUE_IABAR2             IOP13XX_ATUE_OFFSET(0x20)
 359 #define IOP13XX_ATUE_IAUBAR2            IOP13XX_ATUE_OFFSET(0x24)
 360 #define IOP13XX_ATUE_IALR0              IOP13XX_ATUE_OFFSET(0x40)
 361 #define IOP13XX_ATUE_IATVR0             IOP13XX_ATUE_OFFSET(0x44)
 362 #define IOP13XX_ATUE_IAUTVR0            IOP13XX_ATUE_OFFSET(0x48)
 363 #define IOP13XX_ATUE_IALR1              IOP13XX_ATUE_OFFSET(0x4c)
 364 #define IOP13XX_ATUE_IATVR1             IOP13XX_ATUE_OFFSET(0x50)
 365 #define IOP13XX_ATUE_IAUTVR1            IOP13XX_ATUE_OFFSET(0x54)
 366 #define IOP13XX_ATUE_IALR2              IOP13XX_ATUE_OFFSET(0x58)
 367 #define IOP13XX_ATUE_IATVR2             IOP13XX_ATUE_OFFSET(0x5c)
 368 #define IOP13XX_ATUE_IAUTVR2            IOP13XX_ATUE_OFFSET(0x60)
 369 #define IOP13XX_ATUE_PE_LSTS            IOP13XX_REG_ADDR16(\
 370                                         iop13xx_atue_pmmr_offset + 0xe2)
 371 #define IOP13XX_ATUE_OIOWTVR            IOP13XX_ATUE_OFFSET(0x304)
 372 #define IOP13XX_ATUE_OUMBAR0            IOP13XX_ATUE_OFFSET(0x308)
 373 #define IOP13XX_ATUE_OUMWTVR0           IOP13XX_ATUE_OFFSET(0x30c)
 374 #define IOP13XX_ATUE_OUMBAR1            IOP13XX_ATUE_OFFSET(0x310)
 375 #define IOP13XX_ATUE_OUMWTVR1           IOP13XX_ATUE_OFFSET(0x314)
 376 #define IOP13XX_ATUE_OUMBAR2            IOP13XX_ATUE_OFFSET(0x318)
 377 #define IOP13XX_ATUE_OUMWTVR2           IOP13XX_ATUE_OFFSET(0x31c)
 378 #define IOP13XX_ATUE_OUMBAR3            IOP13XX_ATUE_OFFSET(0x320)
 379 #define IOP13XX_ATUE_OUMWTVR3           IOP13XX_ATUE_OFFSET(0x324)
 380
 381 #define IOP13XX_ATUE_ATUCR              IOP13XX_ATUE_OFFSET(0x70)
 382 #define IOP13XX_ATUE_PCSR               IOP13XX_ATUE_OFFSET(0x74)
 383 #define IOP13XX_ATUE_ATUISR             IOP13XX_ATUE_OFFSET(0x78)
 384 #define IOP13XX_ATUE_OIOBAR             IOP13XX_ATUE_OFFSET(0x300)
 385 #define IOP13XX_ATUE_OCCAR              IOP13XX_ATUE_OFFSET(0x32c)
 386 #define IOP13XX_ATUE_OCCDR              IOP13XX_ATUE_OFFSET(0x330)
 387
 388 #define IOP13XX_ATUE_PIE_STS            IOP13XX_ATUE_OFFSET(0x384)
 389 #define IOP13XX_ATUE_PIE_MSK            IOP13XX_ATUE_OFFSET(0x388)
 390
 391 #define IOP13XX_ATUE_ATUCR_IVM          (1 << 6)
 392 #define IOP13XX_ATUE_ATUCR_OUT_EN       (1 << 1)
 393 #define IOP13XX_ATUE_OCCAR_BUS_NUM      (24)
 394 #define IOP13XX_ATUE_OCCAR_DEV_NUM      (19)
 395 #define IOP13XX_ATUE_OCCAR_FUNC_NUM     (16)
 396 #define IOP13XX_ATUE_OCCAR_EXT_REG      (8)
 397 #define IOP13XX_ATUE_OCCAR_REG          (2)
 398
 399 #define IOP13XX_ATUE_PCSR_BUS_NUM       (24)
 400 #define IOP13XX_ATUE_PCSR_DEV_NUM       (19)
 401 #define IOP13XX_ATUE_PCSR_FUNC_NUM      (16)
 402 #define IOP13XX_ATUE_PCSR_OUT_Q_BUSY    (1 << 15)
 403 #define IOP13XX_ATUE_PCSR_IN_Q_BUSY     (1 << 14)
 404 #define IOP13XX_ATUE_PCSR_END_POINT     (1 << 13)
 405 #define IOP13XX_ATUE_PCSR_LLRB_BUSY     (1 << 12)
 406
 407 #define IOP13XX_ATUE_PCSR_BUS_NUM_MASK          (0xff)
 408 #define IOP13XX_ATUE_PCSR_DEV_NUM_MASK          (0x1f)
 409 #define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
 410
 411 #define IOP13XX_ATUE_PCSR_CORE_RESET            (8)
 412 #define IOP13XX_ATUE_PCSR_FUNC_NUM              (16)
 413
 414 #define IOP13XX_ATUE_LSTS_TRAINING              (1 << 11)
 415 #define IOP13XX_ATUE_STAT_SLOT_PWR_MSG          (1 << 28)
 416 #define IOP13XX_ATUE_STAT_PME                   (1 << 27)
 417 #define IOP13XX_ATUE_STAT_HOT_PLUG_MSG          (1 << 26)
 418 #define IOP13XX_ATUE_STAT_IVM                   (1 << 25)
 419 #define IOP13XX_ATUE_STAT_BIST                  (1 << 24)
 420 #define IOP13XX_ATUE_STAT_CFG_WRITE             (1 << 18)
 421 #define IOP13XX_ATUE_STAT_VPD_ADDR              (1 << 17)
 422 #define IOP13XX_ATUE_STAT_POWER_TRAN            (1 << 16)
 423 #define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
 424 #define IOP13XX_ATUE_STAT_ROOT_SYS_ERR          (1 << 12)
 425 #define IOP13XX_ATUE_STAT_ROOT_ERR_MSG          (1 << 11)
 426 #define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
 427 #define IOP13XX_ATUE_STAT_ERR_COR               (1 << 9 )
 428 #define IOP13XX_ATUE_STAT_ERR_UNCOR             (1 << 8 )
 429 #define IOP13XX_ATUE_STAT_CRS                   (1 << 7 )
 430 #define IOP13XX_ATUE_STAT_LNK_DWN               (1 << 6 )
 431 #define IOP13XX_ATUE_STAT_INT_REC_MABORT        (1 << 5 )
 432 #define IOP13XX_ATUE_STAT_DET_PAR_ERR           (1 << 4 )
 433 #define IOP13XX_ATUE_STAT_EXT_REC_MABORT        (1 << 3 )
 434 #define IOP13XX_ATUE_STAT_SIG_TABORT            (1 << 2 )
 435 #define IOP13XX_ATUE_STAT_EXT_REC_TABORT        (1 << 1 )
 436 #define IOP13XX_ATUE_STAT_MASTER_DATA_PAR       (1 << 0 )
 437
 438 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ     (1 << 31)
 439 #define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT          (1 << 30)
 440 #define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP              (1 << 29)
 441 #define IOP13XX_ATUE_ESTAT_TX_PAR_ERR                   (1 << 28)
 442 #define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ          (1 << 20)
 443 #define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR         (1 << 19)
 444 #define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP            (1 << 18)
 445 #define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
 446 #define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP          (1 << 16)
 447 #define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT               (1 << 15)
 448 #define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT         (1 << 14)
 449 #define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR             (1 << 13)
 450 #define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP             (1 << 12)
 451 #define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR         (1 << 4 )
 452 #define IOP13XX_ATUE_ESTAT_TRAINING_ERR         (1 << 0 )
 453
 454 #define IOP13XX_ATUE_IALR_DISABLE               (0x00000001)
 455 #define IOP13XX_ATUE_OUMBAR_ENABLE              (0x80000000)
 456 #define IOP13XX_ATU_OUMBAR_FUNC_NUM             (28)
 457 #define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK        (0x7)
 458 /*=======================================================================*/
 459
 460 /*============================MESSAGING UNIT=============================*/
 461 #define IOP13XX_MU_OFFSET(ofs)  IOP13XX_REG_ADDR32(IOP13XX_MU_PMMR_OFFSET +\
 462                                                         (ofs))
 463
 464 #define IOP13XX_MU_IMR0 IOP13XX_MU_OFFSET(0x10)
 465 #define IOP13XX_MU_IMR1 IOP13XX_MU_OFFSET(0x14)
 466 #define IOP13XX_MU_OMR0 IOP13XX_MU_OFFSET(0x18)
 467 #define IOP13XX_MU_OMR1 IOP13XX_MU_OFFSET(0x1C)
 468 #define IOP13XX_MU_IDR          IOP13XX_MU_OFFSET(0x20)
 469 #define IOP13XX_MU_IISR IOP13XX_MU_OFFSET(0x24)
 470 #define IOP13XX_MU_IIMR IOP13XX_MU_OFFSET(0x28)
 471 #define IOP13XX_MU_ODR          IOP13XX_MU_OFFSET(0x2C)
 472 #define IOP13XX_MU_OISR IOP13XX_MU_OFFSET(0x30)
 473 #define IOP13XX_MU_OIMR IOP13XX_MU_OFFSET(0x34)
 474 #define IOP13XX_MU_IRCSR        IOP13XX_MU_OFFSET(0x38)
 475 #define IOP13XX_MU_ORCSR        IOP13XX_MU_OFFSET(0x3C)
 476 #define IOP13XX_MU_MIMR IOP13XX_MU_OFFSET(0x48)
 477 #define IOP13XX_MU_MUCR IOP13XX_MU_OFFSET(0x50)
 478 #define IOP13XX_MU_QBAR IOP13XX_MU_OFFSET(0x54)
 479 #define IOP13XX_MU_MUBAR        IOP13XX_MU_OFFSET(0x84)
 480
 481 #define IOP13XX_MU_WINDOW_SIZE  (8 * 1024)
 482 #define IOP13XX_MU_BASE_PHYS    (0xff000000)
 483 #define IOP13XX_MU_BASE_PCI     (0xff000000)
 484 #define IOP13XX_MU_MIMR_PCI     (IOP13XX_MU_BASE_PCI + 0x48)
 485 #define IOP13XX_MU_MIMR_CORE_SELECT (15)
 486 /*=======================================================================*/
 487
 488 /*==============================ADMA UNITS===============================*/
 489 #define IOP13XX_ADMA_PHYS_BASE(chan)    IOP13XX_REG_ADDR32_PHYS((chan << 9))
 490 #define IOP13XX_ADMA_UPPER_PA(chan)     (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
 491
 492 /*==============================XSI BRIDGE===============================*/
 493 #define IOP13XX_XBG_BECSR               IOP13XX_REG_ADDR32(0x178c)
 494 #define IOP13XX_XBG_BERAR               IOP13XX_REG_ADDR32(0x1790)
 495 #define IOP13XX_XBG_BERUAR              IOP13XX_REG_ADDR32(0x1794)
 496 #define is_atue_occdr_error(x)  ((__raw_readl(IOP13XX_XBG_BERAR) == \
 497                                         IOP13XX_PMMR_VIRT_TO_PHYS(\
 498                                         IOP13XX_ATUE_OCCDR))\
 499                                         && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
 500 #define is_atux_occdr_error(x)  ((__raw_readl(IOP13XX_XBG_BERAR) == \
 501                                         IOP13XX_PMMR_VIRT_TO_PHYS(\
 502                                         IOP13XX_ATUX_OCCDR))\
 503                                         && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
 504 /*=======================================================================*/
 505
 506 #define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
 507                                                         (ofs))
 508
 509 #define IOP13XX_PBI_CR                  IOP13XX_PBI_OFFSET(0x0)
 510 #define IOP13XX_PBI_SR                  IOP13XX_PBI_OFFSET(0x4)
 511 #define IOP13XX_PBI_BAR0                IOP13XX_PBI_OFFSET(0x8)
 512 #define IOP13XX_PBI_LR0                 IOP13XX_PBI_OFFSET(0xc)
 513 #define IOP13XX_PBI_BAR1                IOP13XX_PBI_OFFSET(0x10)
 514 #define IOP13XX_PBI_LR1                 IOP13XX_PBI_OFFSET(0x14)
 515
 516 #define IOP13XX_PROCESSOR_FREQ          IOP13XX_REG_ADDR32(0x2180)
 517
 518 /* Watchdog timer definitions */
 519 #define IOP_WDTCR_EN_ARM        0x1e1e1e1e
 520 #define IOP_WDTCR_EN            0xe1e1e1e1
 521 #define IOP_WDTCR_DIS_ARM       0x1f1f1f1f
 522 #define IOP_WDTCR_DIS           0xf1f1f1f1
 523 #define IOP_RCSR_WDT            (1 << 5) /* reset caused by watchdog timer */
 524 #define IOP13XX_WDTSR_WRITE_EN  (1 << 31) /* used to speed up reset requests */
 525 #define IOP13XX_WDTCR_IB_RESET  (1 << 0)
 526
 527 #endif /* _IOP13XX_HW_H_ */